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L4-3 Magnitude Comparator Circuit Using Multiplexer

The document discusses register-level design using multiplexers, focusing on implementing a magnitude comparator circuit for 2-bit unsigned numbers. It provides solutions for creating the comparator using both a 16-input, 3-bit multiplexer and an 8-input, 2-bit multiplexer with additional NOR gates. The outputs indicate whether the two numbers are equal, greater, or less than each other.

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70 views5 pages

L4-3 Magnitude Comparator Circuit Using Multiplexer

The document discusses register-level design using multiplexers, focusing on implementing a magnitude comparator circuit for 2-bit unsigned numbers. It provides solutions for creating the comparator using both a 16-input, 3-bit multiplexer and an 8-input, 2-bit multiplexer with additional NOR gates. The outputs indicate whether the two numbers are equal, greater, or less than each other.

Uploaded by

khinsisthway36
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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4.

Register Level Design-I

1. Register-Level Components

2. Full-Adder and Full-Subtracter using Multiplexer

3. Magnitude Comparator Circuit using Multiplexer

Dr. Tha Pyay Win Faculty of Computer Systems and Technologies


Register Level Design using Multiplexer

Problem 1

A magnitude-comparator circuit compares two unsigned numbers X and Y and


produces three outputs 𝒛𝟏, 𝒛𝟐, and 𝒛𝟑, which indicate 𝑿 = 𝒀, 𝑿 > 𝒀, and 𝑿 < 𝒀,
respectively.
(a) Show how to implement a magnitude comparator for 2-bit numbers using a
single 16-input, 3-bit multiplexer of appropriate size,
(b) Show how to implement the same comparator using an eight-input, 2-bit
multiplexer and a few (not more than five) two-input NOR gates.

2
ㅡ
Dr. Tha Pyay Win Faculty of Computer Systems and Technologies 5
Register Level Design using Multiplexer
1
0 A0
Solution (a) using 16-input 3-bit MUX 0
0
0 A1
1
0
outputs 0 A2
inputs 0 1
0 A3
X Y 0 1
X=Y X>Y X<Y 1 A4
0
x1 x0 y1 y0 z1 z2 z3 1
0 A5 z1 (X = Y)
A0 0 0 0 0 1 0 0 0 0
0 A6
A1 0 0 0 1 0 0 1 0
1
16-input,
0 A7 z2 (X > Y)
A2 0 0 1 0 0 0 1 1 3-bit
0 MUX
A3 0 0 1 1 0 0 1 1 A8
A4 0 1 0 0 0 1 0 0
0 z3 (X < Y)
A5 0 1 0 1 1 0 0 1 A9
0
1
A6 0 1 1 0 0 0 1 0 A10
0
A7 0 1 1 1 0 0 1 0
A8 0 1 0 0 A11
1 0 0 0 0 1
A9 1 0 0 1 0 1 0 1 A12
A10 1 0 1 0 1 0 0 0
0 A magnitude-comparator
1 A13
A11 1 0 1 1 0 0 1 0
0
A12 1 1 0 0 0 1 0 1 A14
0
A13 1
1 1 0 1 0 1 0 0 A15
A14 1 1 1 0 0 1 0 0
A15 1 1 1 1 1 0 0
3
x1 x0 y1 y0 ㅡ
Dr. Tha Pyay Win Faculty of Computer Systems and Technologies 5
Register Level Design using Multiplexer
(b) using 8-input 2-bit MUX

inputs outputs
y0 A magnitude-comparator
X Y 0 A0
X=Y X>Y X<Y
x1 x0 y1 y0 z1 z2 z3 0 A1
0 8-way,
0 0 0 0 1 0 0 y0
A0 2-bit
0 0 0 1 0 0 1
y0 A2
MUX
0 0 1 0 0 0 1
A1
0 0 1 1 0 0 1
0 A3 z1
0
0 1 0 0 0 1 0 Z
A2
0 1 0 1 1 0 0 0 A4
0 1 1 0 0 0 1 1 z2
A3 0 1 1 1 0 0 1 y0
0 A5 z3
1 0 0 0 0 1 0
A4
1 0 0 1 0 1 0 0 A6
A5 1 0 1 0 1 0 0 1
1 0 1 1 0 0 1 y0 A7
A6 1 1 0 0 0 1 0 y0
1 1 0 1 0 1 0
A7 1 1 1 0 0 1 0
1 1 1 1 1 0 0 x 1 x0 y 1
4
ㅡ
Dr. Tha Pyay Win Faculty of Computer Systems and Technologies 5
Thank You
For your attention

5
ㅡ
Dr. Tha Pyay Win Faculty of Computer Systems and Technologies 5

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