Module 2

Computer Data Processing Hardware Architecture

2.1 Memory architectures
Memory storage can also have an architecture (configuration) that can aid in the storing and
fetching of memory contents. Generally a memory is organized as a regular structure, which can
be addressed using the memory address register and have data transferred through the memory
data register (Figure 2.1). The memory is accessed through the combination of addressing and
either drivers or sensors to write or read data from or to the memory data register. Memory
structures are built based on the organization of the memory words. The simplest form is a linear
two-dimensional structure. Each memory location has a unique word line, which, when
energized, gates the N-bit lines' (where N is the size of a data word in the computer) contents into
the memory data register.

Figure 2.1 : Memory Access Mechanism

A second organization is the two-and-a-half-dimension architecture. In this memory structure the

memory words are broken up into separate data planes, each consisting of one bit for all memory
locations. To access a word the n planes must be energized with the
composite X and Y coordinates, which correspond to the wanted memory word. The individual
plane drivers gate the proper bit into the memory data register for the addressed memory word.
Other data organizations have been derived and we leave it to the interested reader to investigate
these.

In a computer, the memory address register (MAR) is the CPU register that either stores the
memory address from which data will be fetched to the CPU registers, or the address to which
data will be sent and stored via system bus.
2.2 Memory Address Register
In a computer, the memory address register (MAR) is the CPU register that either stores
the memory address from which data will be fetched to the CPU registers, or the address to
which data will be sent and stored via system bus.

In other words, this register is used to access data and instructions from memory during the
execution phase of instruction. MAR holds the memory location of data that needs to be
accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory
data register) and then used by the CPU. When writing to memory, the CPU writes data from
MDR to the memory location whose address is stored in MAR. MAR, which is found inside the
CPU, goes either to the RAM (random-access memory) or cache.

The MAR register is half of a minimal interface between a microprogram and computer storage;
the other half is a MDR.

In general, MAR is a parallel load register that contains the next memory address to be
manipulated, for example the next address to be read or written.

2.3 How Microcomputers Work ( Operational Details)

2.3.1 Registers and the Arithmetic Logic Unit

The main circuit element in a CPU is the register. Usually the data to be processed by the CPU is
taken from memory and stored temporarily in a register. Like a memory location, a register
usually has a fixed length such as 8, 16, or 32 bits. But unlike a memory location, registers are
often used to manipulate data as well as store it. That is, the register can alter or process the data
in some way.
Examples of how a register can process data are shown in Fig. 2.2. A binary word in a register
can be shifted one or more bit positions to the right or left, or the register may be connected as an
up/down counter, so that it can be incremented (add one to the content) or decremented (subtract
one from the content). A register can also be reset or cleared, thereby erasing any data in it and
leaving the content zero.
2.3.2 Control Unit
CPUs also have several other registers, including the instruction register (IR);
the program counter (PC), also called the instruction counter; and the memory address
register (MAR), also called the address buffer.
The IR is used to store the instruction word. When the CPU fetches an instruction from
memory, it is temporarily stored in the IR. The instruction is a binary word or code that
defines a specific operation to be performed. The instruction word is also called the op
code or operation code. The CPU decodes the instruction, and then executes it.
The PC is really a counter and a register. It stores a binary word that is used as the
address for accessing the instructions in a program. If a program begins with an
instruction stored in mem location 43, the PC is first loaded with the address 43. The
address in the PC is applied to the memory, causing the instruction in location 43 to be
fetched and executed. After the instruction is executed, the PC is incremented (add 1) to
the next address in sequence, or 44. The instructions in a program are stored in
sequential memory locations.
The MAR or address buffer also stores the address that references memory. This
register directly drives the address bus and the memory address decoder in RAM or
ROM. The MAR gets input from the PC when an instruction is to be accessed (see Fig.
2.3). The MAR can also be loaded with an address that is used to access data words
stored in memory. To retrieve a data word used in an arithmetic operation, the MAR is
loaded with the binary word that points to the location of that word in RAM. This
address is often a part of the instruction.
 Figure 2.3. Program counter identifies the address in memory to be accessed.

It is important to note that the PC and the MAR (address buffer) have a fixed length of so many
bits. And that limits the amount of memory that can be accessed. For example, with a 16-bit
address register, the address bus has 16 bits to address RAM and ROM. With 16 bits, a
maximum of 216 = 65,536 words can be addressed.
There are usually two other registers, the flag and stack pointer registers. The flag or F
register is an 8-bit register whose individual flip-flops are set and reset by the ALU as the
various arithmetic and logic operations are carried out. Each flip-flop is called a flag. As an
example, there are zero (Z) and carry (C) flags. If the accumulator content is zero after an
operation is performed, the Z flag is set indicating this condition. If an arithmetic operation
(addition) results in a carry from the most significant bit (MSB) of the accumulator, the C flag is
set indicating this condition. These flags can be monitored or tested by the control circuitry to
change the sequence of processing.
The stack register is a 16-bit or larger register used to address a selected area of RAM known as
the stack. This memory is used to store register contents and status information when subroutines
and interrupts are used.

2.4 The Memory

The processor requires a RAM memory, with an address register (MAR) and a data register
(MDR). Thus therefore need to be a load signal for each of these registers: MDR load and
MAR load. As it is a memory, there also needs to be an enable signal (M_en), and also a signal
to denote Read or Write modes (M_rw). Finally, the connection to the system bus is a standard
inout vector as has been defined for the other registers in the microprocessor.
The basic VHDL for the entity of the memory block is given here:
1 library ieee;
2 use ieee . std_logic_1164 . all;
3 use work . processor_functions . all;
 4 entity memory is
5 port (
6 clk : in std_logic;
7 nrst : in std_logic;
8 mdr_load : in std_logic;
9 mar_load : in std_logic;
10 mar_valid : in std_logic;
11 m_en : in std_logic;
12 m_rw : in std_logic;
13 mem_bus : inout std_logic_vector (n −1 downto 0)
14 );
15 end entity memory;
The memory block has three aspects. The first is the function in which the memory address is
loaded into the memory address register (MAR). The second function is either reading from or
writing to the memory using the memory data register (MDR). The final function, or aspect, of
the memory is to store the actual program that the processor will run. In the VHDL model, we
will achieve this by using a constant array to store the program values.
The resulting basic VHDL architecture is given as follows:
1
2 architecture rtl of memory is
3 signal mdr : std_logic_vector (wordlen −1 downto 0);
4 signal mar : unsigned (wordlen − oplen −1 downto 0);
5 begin
6 mem_bus <= mdr
7 when mem_valid = 1 else (others => z);
8 process (clk, nrst) is
9 variable contents : memory_array;
10 constant program : contents :=
11 (
12 0 => 0000000000000011,
13 1 => 0010000000000100,
14 2 => 0001000000000101,
15 3 => 0000000000001100,
16 4 => 0000000000000011,
17 5 => 0000000000000000,
18 others => (others => 0)
19 );
20 begin
21 if nrst = 0 then
22 mdr <= (others => 0);
23 mdr <= (others => 0);
24 contents := program;
25 elsif rising_edge (clk) then
26 if mar_load = 1 then
27 mar <= unsigned (mem_bus (n − oplen −1 downto 0));
28 elsif mdr_load = 1 then
 29 mdr <= mem_bus;
30 elsif mem_en = 1 then
31 if mem_rw = 0 then
32 mdr <= contents (to_integer (mar));
33 else
34 mem (to_integer (mar)) := mdr;
35 end if;
36 end if;
37 end if;
38 end process;
39 end architecture rtl;
We can look at some of the VHDL in a bit more detail and explain what is going on at this stage.
There are two internal signals to the block, mdr and mar (the data and address, respectively). The
first aspect to notice is that we have defined the MAR as an unsigned rather than as a
std_logic_vector. We have done this to make indexing direct. The MDR remains as a
std_logic_vector. We can use an integer directly, but an unsigned translates easily into a
std_logic_vector.
1 signal mdr : std_logic_vector (wordlen −1 downto 0);
2 signal mar : unsigned (wordlen − oplen −1 downto 0);
The second aspect is to look at the actual program itself. We clearly have the possibility of a
large array of addresses, but in this case we are defining a simple three line program:
1c=a+b
The binary code is shown below:
1 0 => 0000000000000011
2 1 => 0010000000000100
3 2 => 0001000000000101
4 3 => 0000000000001100
5 4 => 0000000000000011
6 5 => 0000000000000000
7 Others => (others => 0)
For example, consider the line of the declared value for address 0. The 16 bits are defined as
0000000000000011. If we split this into the opcode and data parts we get the following:
1 Opcode 0000
2 Data 3000000000011
In other words, this means LOAD the variable from address 3. Similarly, the second line is ADD
from 4, finally the third command is STORE in 5. In addresses 3, 4, and 5, the three data
variables are stored.

2.5 Embedded Processor Register Allocation

The design of the registers partly depends on whether we wish to clone a “real” device or create
a modified version that has more custom behavior. In either case there are some mandatory
registers that must be defined as part of the design. We can assume that we need an accumulator
(ACC), a program counter (PC), and the three input/output ports (PORTA, PORTB, PORTC).
Also, we can define the instruction register (IR), Memory Address Register (MAR), Memory
Data Register (MDR).
In addition to the data for the ports, we need to have a definition of the port direction and this
requires three more registers for managing the tristate buffers into the data bus to and from the
ports (DIRA, DIRB, DIRC). In addition to this, we can define a number (essentially arbitrary) of
registers for general purpose usage. In the general case the naming, order, and numbering of
registers does not matter; however, if we intend to use a specific device as a template, and
perhaps use the same bit code, then it is vital that the registers are configured in exactly the same
way as the original device and in the same order.
In this example, we do not have a base device to worry about, and so we can define the general
purpose registers (24 in all) with the names REG0 to REG23. In conjunction with the general
purpose registers, we need to have a small decoder to select the correct register and put the
contents onto the data bus (F).

2.6 Microcomputer Buses

Data transfers inside a microprocessor take place in parallel. This means that all bits in a word
are transferred simultaneously from one place to another. It takes only a few nanoseconds (one
billionth of a second) for all data bits in one register to be moved to another register.
The parallel data transfers take place over a data bus. A bus is simply multiple parallel electrical
connections from a source to a destination. A number of these buses are contained within
the CPU and are known as internal buses.
Microprocessors usually have three major buses—a data bus, an address bus, and a control
bus. These are made available to external circuits in some micros. A typical 8-bit CPU has an 8-
bit data bus and a 16-bit address bus. The data bus sends data to and from the CPU, RAM, ROM,
and I/O sections. All data transfers between the CPU and memory or I/O sections take place over
the data bus. The address bus drives all of the memory and I/O devices.
When an instruction is fetched from RAM or ROM, it is transferred over the data bus from the
memory into the instruction register. Any data word retrieved from memory or a peripheral
device via the input section also passes over the data bus into the accumulator or GPR.
When a store instruction is executed, the word in the accumulator is transmitted over the data bus
into RAM. Data can also be transferred from the accumulator over the data bus to an external
device such as an LCD. Or, data from an input device such as a keyboard passes over the data
bus and is placed into the accumulator. The important point here is that data can move in either
direction over the data bus. We say that it is a bidirectional bus.
Another key point is that the data bus can be connected to only one data source at a time. Data
can originate only at a single source, but it can be sent to one or more destinations. To
accomplish this, circuits called bus multiplexers, or three-state line-driver circuits, are used to
connect or disconnect the various data sources to or from the bus. Figure 2.6 illustrates this
concept.
 Figure 2.6. Only one source may transmit at a time on a bus. Others are disconnected. All

destinations can receive the transmitted data. Dest=destination.

The address bus is a unidirectional bus. It transfers an address from the CPU to all external
circuits (memory and I/O). Address words are produced in the CPU. The PC generates the
address that points to the instruction to be fetched. The content of the PC is transferred over a
parallel 16-bit internal address bus to the memory address register or address buffer. The output
of the MAR or address buffer is the address bus.
The control bus consists of numerous signals generated by the microprocessor and used to
initiate various memory or I/O operations. The control bus also contains input lines from external
circuits that tell the CPU what to do and when. The number of control signals varies from CPU
to CPU.

2.7 Microprocessors
2.7.1 Control and timing unit
The basic operation of a computer or microprocessor is governed by the control and timing unit
(CTU) which generates the signals necessary to coordinate, synchronise and control the
movement and processing of all information within the system. A simple external clock usually
drives the unit, and this provides a time-reference signal from which the CTU generates the
timing and control signals for the various logic subsystems in the computer. Modern high-
performance processors may include a separate clock management subsystem which generates
multi-phase timing sequences for use by the CTU.
The control and timing unit is responsible for controlling the main operational cycle of the
processor which is known as the ‘instruction cycle’. The instruction cycle can be split into two
distinct phases, the instruction fetch and the execution of the instruction. During the instruction
fetch the address of the next instruction is obtained from the program-counter mechanism and
transferred to the memory address register (MAR). A memory reference operation is then
performed on the code part or code segment of memory to read the opcode which is the first part
of an instruction. The opcode data are transferred via the memory buffer register (MBR) to the
instruction register where it is decoded and then input to the CTU. The program-counter is then
updated to point to the next part of the instruction or to the next instruction.
The opcode identifies any further memory reference operations which are required to complete
the instruction ‘fetch’. The control unit uses the updated program counter to make reference to
successive addresses in the code part of memory to fetch any further parts of the instruction, such
as immediate data values or the addresses of the operands and the address of the resultand. This
information is transferred to various temporary registers in the CPU for use during the ‘execute’
cycle. At the end of the instruction ‘fetch’, the CPU will contain all the information it requires to
control the execution of the instruction and the program-counter will be pointing to the next
instruction to be fetched (assuming that the execution cycle does not compute a new program-
counter address). The various logic units used during the instruction ‘fetch’ cycle are shown
in Figure 15.9 in which the memory and input/output discriminator M¯/IO is used to distinguish
between memory reference operations and any operations involving peripheral systems which
may use the same address and data bus.
 Figure 2.7. Instruction ‘fetch’ logic structure

The opcode also defines the sequence of operations necessary to execute the instruction. During
the execution part of the instruction cycle the control and timing unit will synchronise the
transfer of data within the system and control the operation of the ALU. The control unit will
access operand data by transferring the operand addresses from the temporary registers to
the memory address register to perform memory reference operations. In practice, many
processors have a complex data reference pointer which will compute the address of the data
object using not only the temporary register but also base or segment registers, offset registers,
and index registers according to the addressing mode specified in the instruction. If the computer
has a memory-to-memory architecture, then operand data can be transferred direct from
immediate access memory to the arithmetic logic unit and resultands can be returned direct to
storage in immediate access memory. However, if the computer has a register-to-register
architecture, then the operand data is normally transferred to a CPU register before being
processed by the arithmetic logic unit and result and data is held in the accumulator or
transferred to another CPU register. The register-to-register architecture has distinct performance
advantages, particularly when used with a multiple-instruction pipeline CTU, as in modern
reduced instruction set (RISC) processors.

2.8 Instruction-Word Formats

There are three types of instruction formats used in typical 8-bit microprocessors, illustrated
in Figure 6.8. In the single-word format, the instruction is a single 8-bit word. This word is called
the op code. The op code tells the ALU, the registers, and other elements of the system what to
do. In this format, no address is used. The focus of the instruction is implied in the instruction.
That is, the data to be processed is already in a location designated by the instruction. Usually the
data is in a register. Typical instructions using this format are register-to-register transfer, shift
data left (or right), or clear to zero.

Figure 2.8. Three common instruction-word formats with addresses or data.

The two-word instruction format in Figure 2.8 requires two 8-bit words to define the operation.
These two words are stored in sequential memory locations. The first word is the op code. The
second word is usually an address that specifies a memory location where the data word to be
processed is stored. For example, if the op code calls for an add operation, the address word
designates the location in RAM of the number to be added to the contents of the accumulator.
The 256 bytes of RAM can be addressed with 1 byte of address.
In some 2-byte instructions, the second byte is not the address. Instead, it is the data itself. This is
called an immediate instruction since it is not necessary to address the data that is available
immediately within the instruction itself.
The three-word instruction format in Figure 6.8 is comprised of an 8-bit op code and two 8-bit
address words stored in sequential memory locations. The second and third bytes together form a
16-bit address word that designates the location in RAM of the data to be processed. In the 3-
byte instruction format, the first byte is the op code, the second byte is the least significant half
of the address, while the third byte is the most significant part of the address. Different formats
are used by other micros.
To access a word in RAM, the instruction address word must be stored in the MAR. This
happens during the instruction fetch operation. When an instruction is fetched from memory, the
op code is stored in the instruction register while the address is stored in the MAR. The
instrP a g e | 10uction is then executed. The MAR usually gets its input from the PC. Once an
instruction is fetched and executed, the PC is incremented.
The PC may be incremented once, twice, or three times, depending on the length of the
instruction just executed. If a 2-byte instruction is executed, the PC is incremented twice so that
the PC points to the address of the next instruction op code.