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CHAPTER 4: COMBINATORIAL
LOGIC CIRCUITS
Target skills :
By the end of this lesson, learners should be able to :

- Study and design combinatorial logic circuits based on a logic expression;

- Differentiate between half-adder, full-adder and comparator ;
- Design and use logic circuits such as decoders, encoders, multiplexers, demultiplexers, etc.

INTRODUCTION
A combinatorial logic function is any function defined from input variables only, whatever the time
of observation.
Combinatorial circuit: a circuit whose outputs depend solely on the combination of input states at
the moment of observation.
A combinational logic circuit is any circuit whose output state depends solely on the combination
of its inputs. The logic elements (logic gates) used up to now belonged to the SSI (Small Scale
Integration) category, simply because of their simplicity.
The evolution of electronics has led to the design of MSI (Medium Scale Integration) circuits,
which are a little more complex, integrating more gates (12 to 99 gates) and enabling the realization of
all combinatorial logic functions, including arithmetic circuits (adder, subtractor, comparator),
decoders, encoders, multiplexers and demultiplexers.

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Lesson 1: ARITHMETIC CIRCUITS

I. Adder
I. 1: Half-adder
A Half Adder (½ ADD) is a logic circuit that adds two binary numbers with one bit each at its
input and generates at its output two numbers with one bit each, namely: a sum bit ( ∑ or S ) and a
carry bit (C or R) if required.
f) Symbol g) Truth tableh ) Equations

A B S R 𝑆 = 𝐴̅𝐵 + 𝐴𝐵̅
A S 0 0 0 0 𝑆=𝐴𝐵
½ ADD 0 1 1 0

B R 1 0 1 0
𝑅 = 𝐴𝐵
1 1 0 1

i) Logigramj ) Limits
A B To add two multi-bit numbers, you need to t a k e i n t o
a c c o u n t any carry over from the previous stage.

S A half-adder can't do the job, so a three-input circuit is

needed: this is a full adder.

I.2 : Full adder

It's a logic circuit that sums two binary numbers at its input, taking into account the previous
carry, and produces two numbers at its output: a sum bit and a carry b i t .
a) Symbolsb) Truth table

A B Rn-1 S Rn

0 0 0 0 0
0 0 1 1 0

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A A S
S 0 1 0 1 0
0 1 1 0 1
ADD 1 0 0 1 0

s
Output
B
Inputs

B 1 0 1 0 1

Complete
Cin Rn
1 1 0 0 1
Rn-1 1 1 1 1 1
Cost

c) Equations
𝑆= 𝐴̅𝐵̅𝑅 𝑛 −1 + 𝐴̅𝐵 𝑅̅𝑛 -1 + 𝐴𝐵̅𝑅̅𝑛 -1 + 𝐴𝐵𝑅𝑛−1

𝑆 = 𝑅𝑛−1 (𝐴̅𝐵̅ + 𝐴𝐵) + 𝑅̅𝑛-1 (𝐴̅𝐵 + 𝑆 = 𝑅𝑛 −1 𝑋̅ + 𝑅̅𝑛-1𝑋 = 𝑛−1 𝑅𝑋

𝐴𝐵̅)

X X
𝑆 = 𝑅𝑛−1 𝐴 𝐵

𝑛 𝑅= 𝐴̅𝐵 𝑅 𝑛 −1 +𝑛−1 𝐴𝐵̅𝑅 + 𝐴𝐵𝑅̅𝑛-1 + 𝐴𝐵𝑅𝑛−1

𝑛 𝑅= 𝐵𝑅𝑛−1 (𝐴̅ + 𝐴) + 𝐴(𝐵̅𝑅 𝑛 −1 + 𝐵 𝑅̅𝑛 - 1 )
𝑛 𝑅= 𝐵𝑅𝑛−1 + 𝐴(𝐵 𝑅 ) 𝑛−1

Or
𝑛 𝑅= 𝐴𝐵( 𝑅̅𝑛 -1 + 𝑅𝑛−1 ) + 𝑅𝑛−1 (𝐴̅𝐵 + 𝐴𝐵̅)
𝑛 𝑅= 𝐴𝐵 + 𝑅𝑛−1 (𝐴 𝐵)

d) Flow chart
AB Rn-1

Rn

I.3 Structure of a complete adder using two half-adders

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R' = AB
A Rn

½ ADD
S' = A B
B
R'' = Rn-1(A B)
½ ADD
Rn-1 S=A B Rn-1

With 𝑅𝑛 = 𝐴𝐵 + 𝑅𝑛−1 (𝐴 𝐵)
II. Subtractor

II.1 Half-subtractor
It is a logic circuit capable of subtracting one bit from another, and generates at its output a
difference D and the carry R
a) Symbolb ) Truth tablec ) Equations

A S A B D R 𝐷 = 𝐴̅𝐵 + 𝐴𝐵̅
½
0 0 0 0 𝐷=𝐴𝐵
Subtractor
0 1 1 1
B R
1 0 1 0 𝑅 = 𝐴̅𝐵
1 1 0 0
d) Flow chart e) Limits
AB
Just like a half-adder, a subtractor cannot subtract the
difference between two bits, taking into account the previous
D
carry.

II.2 Complete subtractor

We want to obtain the difference D between two bits A and B, taking into account the carryover Rn-1
(or Ci-1 ) from the previous stage, and generate the carryover Rn (or Ci ) for the next stage.
a) Symbolb ) Truth table

A B Rn-1 D Rn

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1

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A A S
D 0 1 1 0 1
1 0 0 1 0

Subtractor 1 0 1 0 0

s
Output
B
Inputs

B 1 1 0 0 0
complet
e 1 1 1 1 1
Rn-1
Rn
Cin Cost

c) Equations
𝐷= 𝐴̅𝐵 ̅𝑅 𝑛 −1 + 𝐴̅𝐵 𝑅̅𝑛 -1 + 𝐴𝐵̅𝑅 ̅𝑛 -1 + 𝐴𝐵𝑅𝑛−1

𝐷 = 𝑅𝑛 −1 (𝐴̅𝐵 ̅ + 𝐴𝐵) + 𝑅̅𝑛-1 (𝐴̅𝐵 + 𝐴𝐵̅) 𝐷 = 𝑅𝑛−1 𝐴 𝐵

𝑛 𝑅= 𝐴̅𝐵 ̅𝑅 𝑛 −1 + 𝐴̅𝐵 𝑅̅𝑛 -1 + 𝐴̅𝐵𝑅𝑛−1 + 𝐴𝐵𝑅𝑛−1

𝑛 𝑅= 𝐵𝑅𝑛−1 (𝐴̅ + 𝐴) + 𝐴̅(𝐵̅𝑅 𝑛 −1 + 𝐵 𝑅 ̅𝑛 - 1 ) 𝑛 𝑅= 𝐵𝑅𝑛−1 + 𝐴̅( 𝐵 𝑅 ) 𝑛−1
Or 𝑛 𝑅= 𝐴̅𝐵 ( 𝑅̅𝑛-1 + 𝑅𝑛−1 ) + 𝑅𝑛 −1 (𝐴̅𝐵 ̅ + 𝐴𝐵) 𝑛𝑅=𝐴̅𝐵 + 𝑅 𝑛 −1̅ ̅ 𝐵
(̅𝐴̅̅ )

d) Flow chart
A B Rn-1

Rn

III. Comparators
A comparator is a combinatorial logic circuit that compares the magnitudes of two binary
quantities to determine the relationship between them (equality, superiority or inferiority).
Consider the following logic comparator with two inputs A and B and three outputs S, E and I:
a) Symbolsb ) Truth table

A B S E I
A S S: Superiority
0 0 0 1 0
s
Output
Inputs

E E: Equality
0 1 0 0 1

1 0 1 0 0
B I I: Inferiority
1 1 0 1 0

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d) Flow chart
c) Equation
A B

𝑆 = 𝐴𝐵̅

𝐸 = 𝐴̅𝐵̅ + 𝐴𝐵 = ̅ ̅𝐴
𝐵̅
̅̅ S

𝐼 = 𝐴̅𝐵 E

Lesson 2: DECODEURS, CODEURS, TRANSCODEURS

I. Decoder
A decoder is a logic circuit that maps an n-bit input code to a n-bit output code.
and M output lines. With 𝑀 ≤ 2𝑛 .
There are several types of decoder, including: classic decoders (1 of 2𝑛 ); DCB decoders; 7-
segment DCB decoders.

Note: Most decoders h a v e one or more enable inputs to control their operation.

I.1. Decoders 1 of 2𝑛
For each input combination, only one output line is enabled, i.e. only one of the available M=2𝑛
outputs is activated at a time according to the input binary value.

Example: Decoder 1of 2; 1of 4; 1of 8; 1of 16; ...

I.1.1. General structure

S0
A0 S1
A1 S2
S3 Outputs
Address
entries Decoder
1 of N
An-1
SN-1

E
A0 is the LSB

An-1 le MSB Validation input

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I.1.2. Study of two-input decoders (Decoder 1 of 4)

a) Symbolsb ) Truth table

S0 A1 A0 S3 S2 S1 S0

A0
S1 0 0 0 0 0 1
Decoder
S2 0 1 0 0 1 0
A1 1 of 4
S3
1 0 0 1 0 0

1 1 1 0 0 0
c) Equation

S3 = A1A0 ; S2 = A1A̅0 ; S1 = A̅1 A0 ; S0 = A ̅1 A ̅0

d) Flow chart

S3 S2 S1 S0

I.1.3. Decoder 1 of 8 with one validation input

𝑁=8 𝑜𝑟 2𝑛 = 8 ′ 𝑑𝑜ù 𝑛=3

a) Symbolsb ) Truth table

A2 A1 A0 S7 S6 S5 S4 S3 S2 S1 S0
S0

A0 S1 0 0 0 0 0 0 0 0 0 0 1
S2
0 0 1 0 0 0 0 0 0 1 0
S3
A1 Decoder S4
0 1 0 0 0 0 0 0 1 0 0
1 of 8 S5 0 1 1 0 0 0 0 1 0 0 0
A2 S6 1 0 0 0 0 0 1 0 0 0 0
S7 1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

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c) Output equations

S7 = A2A1A0 S5 = A2A̅1 A0 S3 = A̅2 A1A0 S1 = A ̅2 A ̅1 A 0

S6 = A2A1A̅0 S4 = A 2 A ̅1 A ̅0 S2 = A ̅2 A 1 A ̅0 S0 = A ̅2 A ̅1 A ̅0

d) Flow chart

Notes : Some decoders are equipped with one or more enable inputs that can be activated at either high
or low level to control operation.

✓ When this (these) input(s) at level (x) is (are) active, the decoder operates normally and the state
of the outputs depends on the combination of inputs.
✓ When not active, all outputs are deactivated.

Assume the following 74LS138 circuit:

a) Symbolsb ) Operating table
E3 E2 E1 Outputs Observation
A0 S0
S1
A1
S2 Code feedback
A2
S3
input addresses Normal
74LS138 S4 0 0 1
operation
E1 or S5

E2 74138 S6
1 X X All outputs in
E3 S7
x 1 X high state Blocking
x X 0

Cascading decoders

We use a lot more validation input in this case.

Example: Build a 3-input decoder using 2 2-input decoders.

StructureTruth table
Inputs DECO 2 outputs DECO 1 outputs

e2 e1 e0 S7 S6 S5 S4 S3 S2 S1 S0

0 0 0 0 0 0 1
0
0
0
0
1
1
1
0
1
0 0
0
1
0
1
0
1
0
0
0
0
0

1 0 0 0 0 0 1

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1 0 1 0 0 1 0
e0 S0
1 1 0 0 1 0 0
S1
e1
Decoder 1 S2
1 1 1 1 0 0 0
of 4
S3
V
S4

e0 S5
e1
Decoder S6
e2 1 of 4 S7

V
TAF: 1) Create a 16-output decoder using the 4-output decoders.

2) Create a 16-output decoder using the 8-output decoders.

I.2. Study of a DCB decoder (1 of 10) : Example of the 7442

This decoder has no validation or validity input. One of the outputs of this circuit goes to
"0" when an address corresponding to the DCB number is applied as input.

Truth table

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D C B A Active output
D C B A
0 0 0 0 ̅𝑆0
0 0 0 1 ̅𝑆1
0 0 1 0 ̅𝑆2
0 0 1 1 ̅𝑆3
0 1 0 0 ̅𝑆4

0 1 0 1

74 42
̅𝑆5
0 1 1 0 ̅𝑆6
0 1 1 1 ̅𝑆7
1 0 0 0 ̅𝑆8

1 0 0 1 ̅𝑆9
1 0 1 0
1 0 1 1
1 1 0 0
Blocking
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 1 1 0 1
1 1 1 0
1 1 1
Task: What logical state will the logic outputs be in when the following numbers are applied to the
input:

a) DCBA = 0010 ; b) DCBA = 1100

Answer:
For DCBA = 0010 = 2, ̅ 𝑆 2 = 0 and the other outputs are set to "1"; the decoder operates normally.
For DCBA = 1100 = 12 ; 12 𝑛′ 𝑎𝑝𝑝𝑎𝑟𝑡𝑖𝑒𝑛𝑡 𝑝𝑎𝑠 at [0 ; 9] so the decoder is blocked

I.3. Decoder applications

✓ Memory addressing
✓ Function generation

II. Decoders (or encoders)

II.1. General presentation
The encoder is a logic circuit that performs the inverse operation of the decoder; it has 𝑀 = 2𝑛
inputs and n outputs that encode in binary the rank of the only active input.

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A S0
0 S1
A1 n outputs
M entries CODEUR
A2

Sn-1
V
AM-1

Validation input

II.2. Octal
encoder
This is an eight-channel input circuit which outputs a binary number represented on three (3) bits.

a) Structure b) Truth table

A7 A6 A5 A4 A3 A2 A1 A0 S2 S1 S0
A0
A1
S0 0 0 0 0 0 0 0 1 0 0 0
A2 0 0 0 0 0 0 1 0 0 0 1
A3
CODEUR S1 0 0 0 0 0 1 0 0 0 1 0
A4
octal
A5 0 0 0 0 1 0 0 0 0 1 1
A6
0 0 0 1 0 0 0 0 1 0 0
A7 S2
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
C) Output equations

S0 = A1 + A3 + A5 + A7 ; S1 = A2 + A3 + A6 + A7 ; S2 = A4 + A5 + A6 + A7

II.3. Priority encoder

The encoder studied above has one major drawback: if more than one input is active at the same
time, the encoder will produce erroneous results at the output. To compensate for this shortcoming,
priority encoders were developed to improve these elementary encoders. It therefore has the necessary
circuitry to ensure that output codes exist when 2 are active, i.e. the one corresponding to the largest
number.

Example of a priority encoder: DCB decimal encoder (CI 74 147)

The 74147 integrated circuit is a 9-input priority encoder. It is active in the low state and
produces the complemented B.C.D. code at output. If two pieces of decimal information are
simultaneously applied to the input, the output corresponds to the higher value of the two inputs.

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a) Structure b) Truth table

𝐴 ̅1 𝐴 ̅2 𝐴 ̅3 𝐴 ̅4 𝐴 ̅5 𝐴 ̅6 𝐴 ̅7 𝐴 ̅8 𝐴 ̅9 ̅𝑆3 ̅𝑆2 ̅𝑆1 ̅𝑆0
A9 A8 A7 A6 A5 A4 A3 A2 A1

1 1 1 1 1 1 1 1 1 1 1 1 1
X X X X X X X X 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
CODEUR
X X X X X X 0 1 1 1 0 0 0
74LS147
X X X X X 0 1 1 1 1 0 0 1
X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
S1 S2 S1 S0 X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
Application: keypad encoder

III. Transcoders

A transcoder is a logic circuit capable of translating information written in any code to another
code.

There are several types of transcoders:

✓ Complementary DCB-DCB transcoder ;

✓ pure binary transcoder - DCB ;
✓ pure binary transcoder - Increased by 3 ;
✓ natural binary transcoder - Gray ;
✓ BCD transcoder - 7-segment code

III.1. DCB -7 segment transcoder study

Commonly referred to as "7-segment BCD decoders", 7-segment DCB transcoders are designed
to control the 7-segment displays widely used in electronic display systems (calculators; digital
multimeters; watches (digital clocks); ...).
They have four inputs and seven outputs. Their operating logic is different from that of the
decoders studied above, since this is not a 1-of-7 decoder, as several outputs can be active for the same
input combination. 7-segment displays show digits (from 0 to 9) by switching on or off 7segments (7
light-emitting diodes) labelled A to G, as shown in the following figures.
a) General arrangement of figures

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b) Decoding principle + display

Example: Digit 1 = Segments to be lit b and c Digit 5 = Segments to be lit a, c, d, f, g

b.1) 7-segment display

There are two types of 7-segment display: common-anode and common-cathode. In the first
case, all the anodes are connected to the same point, set at 5V, so as to illuminate the segment with a low
level on its cathode. In the case of the common-cathode display, all cathodes are connected to a common
point, which must be grounded, so that to light a segment, a high level must be applied to its anode.

b.2) Truth table for a DCB decoder with high-level outputs

Inputs Outputs
Display
D C B A a B C d e f g
0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1

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b.3) Simplified output equations

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c) B.C.D - 7-segment integrated circuit transcoder

The B.C.D-7 segment transcoder is available as an integrated circuit. The 7447 is a transcoder that can
often be used with 7-segment displays.

The outputs of the 7447 are active in the low state, which requires the use of 7-segment displays with
common anodes (all segment anodes are connected to 5V), since grounding the cathode of an LED
causes the corresponding segment to light up.

If the display is common-cathode, use an active high-state transcoder such as the C.I 7448.

Wiring the 7-segment display to the 7447 transcoder

N.B.: The cathodes are connected to the 7447 outputs via
resistors (R) which limit the current flowing through the
LEDs to approx. 20 mA.

The three most common BCD / 7-segment transcoders are the 7447, the 7448 and the 4511 (CMOS
decoder that can be powered from 3V to 18V).

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Lesson 3: MULTIPLEXES - DEMULTIPLEXES

I. Multiplexer (MUX)

I.1. General presentation

Also known as a data selector, the multiplexer is a data connector logic circuit with 2𝑛 data or
information inputs, n address inputs and a single output that communicates this data. It acts as a multi-
position switch that routes information from any input to the output. Data selection is controlled by n
address inputs, also known as "SELECT" inputs.

I Other representation
N = 2
0 I1 I2 IN-1 information or I0 I1 I2
IN-1
data input
n address
entries or A0 MUX
A0 A1
SELECT A1
MUX
An-1
An-1

S S
Output

Note: The MUX functions as a multi-position switch whose position is given by the numerical code
applied to the address inputs.

For n address bits, there can be a maximum of 2n data entries.

Like other logic circuits, the MUX can also have an enable input to control its operation (to eliminate
noise in the MUX).

I.2) MUX with two data inputs (MUX 2 to 1)

a) Structure c) Truth table and d) Flow chart

I0 I1 output equation A I0 I1

A 𝐼0 𝐼1 S
MUX 0 𝐼0
A
2 to 1
1 𝐼1 S

S = A̅I 0 + 𝐴I1
S

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I.3) MUX with four (4) data inputs (MUX 4 to 1)

a) Structure b) Truth table c) output equation
I0 I1 I2 I3

S = A̅1 A̅0 I0 + A̅1A0I1 +

d) Flow chart
A0 MUX + A1A̅0I2 + A1A0I3
A1
4 vers 1

𝐴1 𝐴0 S

0 0 𝐼0
0 1 𝐼1
1 0 𝐼2
1 1 𝐼3

I0

I1

S
I2

I3

A1 A0

I.4) MUX with eight (8) data inputs (MUX 8 to 1)

e) Structure f)Truth table

I0 I1 I2 I3 I4

S𝐴2 𝐴1 𝐴0
V S

1 X X X 0
0 0 0 𝐼0
A
0 0 0 1 𝐼1
A1 MUX 0 1 0 𝐼2

0
A2
8 vers 1 0 1 1 𝐼3
V E 1 0 0 𝐼4
1 0 1 𝐼5
1 1 0 𝐼6
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I5 I6 I7

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a) output equation

S = A̅2 A̅1 A̅0 I0 + A̅2A̅1A0I1 + A̅2A1A̅0I2 + A̅2A1A0I3 + A2A̅1A̅0I4

+ A2A̅1A0I5 + A2A1A̅0I6 + A2A1A0I7

I.5) Application of MUX

✓ Parallel-serial conversion
✓ Logic function generator
✓ Communication

Application exercises
Exercise 1: Consider the following circuit

I0 I1 I2 I3 I4 I5 I6 I7

Show how this circuit can be used to generate

the following logic function Z and then draw
A up its truth table.
B
A is the MSB and C the LSB
C 74 151
E
𝐙 = 𝑨̅𝑩̅𝑪 + 𝑨̅𝑩 𝑪 + 𝑨𝑩̅𝑪̅ + 𝑨 𝑩 𝑪 ̅ + 𝑨𝑩𝑪

Z
SOLUTION :

𝐒 = 𝑨̅𝑩̅𝑪 + 𝑨̅𝑩 𝑪 + 𝑨𝑩̅𝑪̅ + 𝑨 𝑩 𝑪 ̅ + 𝑨𝑩𝑪 𝑬̅ A B C Z

001 011 100 110 111
1 X X X 0
I1 I3 I4 I6 I7 0 0 0 0 𝑰𝟎

𝐙= 𝑨̅𝑩 𝑪
̅ 𝑰 𝟏 + 𝑨̅𝑩𝑪𝑰𝟑 + 𝑨𝑩̅𝑪 𝑰̅ 𝟒 + 𝑨𝑩𝑪̅𝑰𝟔 + 𝑨𝑩𝑪𝑰
𝟕
0 0 1 1 𝑰𝟏
0 1 0 0 𝑰𝟐

0 0
1
1
1
0
0
1
0
1
1
1
0
𝑰𝟑
𝑰𝟒
𝑰𝟓
1 1 0 1 𝑰𝟔
1 1 1 1 𝑰𝟕

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II. Demultiplexer (DEMUX)

Also known as a data distributor, the DEMUX is a logic circuit that performs the inverse operation
of a MUX. It typically has a single data input and 2n data outputs, with n address inputs. It acts as a
multi-position switch, directing input information to each selected output.

II.1) Structure

Other representation
Data input
E
E
n address
entries or A0
SELECT A1 DEMUX A0
A1

An-1
An-1 DEMUX

SN-1 S2 S1 S0 N = 2 n
SN-1 S2 S1 S0
Data output information or
data outputs

II.2) DEMUX with 3 SELECT inputs (DEMUX 1 to 8)

g) Structure h) Truth table

𝐴2 𝐴1 𝐴0 𝑆7 𝑆6 𝑆5 𝑆4 𝑆3 𝑆2 𝑆1 𝑆0
E
0 0 0 0 0 0 0 0 0 0 E
0 0 1 0 0 0 0 0 0 E 0
0 1 0 0 0 0 0 0 E 0 0
A0
A1 0 1 1 0 0 0 0 E 0 0 0
A2 DEMUX 8 vers 1
1 0 0 0 0 0 E 0 0 0 0
1 0 1 0 0 E 0 0 0 0 0
1 1 0 0 E 0 0 0 0 0 0
S7 S6 S5 S4 S3 S2 S1 S0
1 1 1 E 0 0 0 0 0 0 0

II.3) Application of DEMUX

✓ Serial-to-parallel conversion
✓ Communication

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TD3: COMBINATORIAL LOGIC CIRCUITS AND DIGITAL

INTEGRATED CIRCUIT TECHNOLOGIES
EXERCISE 1: COMPARATOR
1) Give the logic diagram of a 1-bit comparator with a validation input V enabling comparison. If
V=0, all outputs are "O", otherwise operation is as follows:
• Si=1 if Ai > Bi,
• Ei=1 if Ai = Bi,
• Ii=1 if Ai < Bi.
V
2) Design of a comparator for two 3-bit numbers A = (A A A2102 )and B = (B B B )2102
a) Deduce the schematic of this circuit using 3 cascaded 1-bit comparators and << OR >> logic
gates.
b) What's the downside of this solution?
c) Knowing that A2 = B2 and A1 = B1 and that each elementary comparator has a propagation
time tp1 = 6µs and each logic gate has a propagation time tp2 = 4.5µs; Calculate the time
taken to produce the result of this comparison.
3) We want to display this result on a 7-segment display. Study the circuit that makes the segments
luminous so as to display :

If A > B; If A = B and If A < B

EXERCISE 2: ADDER
A- 1-bit adder
We wish to add two binary numbers A and B, each with a single bit and possibly taking into account the
previous carryover Cn-1 (the outputs are: sum "S" and carryover "C").
1) What's the difference between a half adder and a full adder?
a) Give the structure o f a half-adder and establish its truth table, then construct the logigram of this
circuit.
2) Design of a complete adder
b) Give the structure, then using two half-adders
c) Setting up your truth table
d) Construct chronograms of outputs S and Cn as a function of inputs A, B and Cn-1
e) Establish the equations of S and R, then simplify them
f) Create your own logic diagram using the logic gates of your choice
B- 4-bit adder
We would now like to add two binary numbers A and B, each with 4 bits, possibly taking into
account the previous carryover Cn-1 (the outputs are: sum "Si " and carryover.
"Ci "). The numbers are : A= A A A3210 Aand B= B B B B3210
Wiring this circuit using full adders

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EXERCISE 3: Subtractor
1) Give the structure of a half-subtracter that performs the difference of two bits A and B as input
and provides as output the difference bit D=A-B and the carry R. Establish its truth table and
then construct the output logic diagrams using the appropriate logic gates.
2) Complete subtractor
a) Give the structure of a complete subtractor, then starting with two half-adders
b) Setting up your truth table
c) Construct chronograms of outputs S and Cn as a function of inputs A, B and Cn-1
d) Establish the equations of S and R, then simplify them
e) Create your own logic diagram using the logic gates of your choice

EXERCISE 4: Transcoder
A transcoder is a logic circuit capable of translating information from one circuit to another. In
this exercise, we'll be working on a logic circuit capable of encoding a four-bit pure binary number a, b,
c, d to its four-bit reflected binary equivalent (A, B, C, D) (NB: a is the least significant bit and d the
most significant bit).
1) Establish the truth table of this transcoder
2) Establish equations A, B, C and D, then simplify them using the method of your choice.
3) Produce the logic diagram for A using two-input NOR gates only.

EXERCISE 5: We give the truth table and the 74151 circuit below:

A B C X

0 0 0 1
0 0 1 0 A
E0 E1 E2 E3 E4 E5 E6 E7
A0
0 1 0 1 B A1

0 1 1 1 C
A2
MUX 74151
V
1 0 0 0 S
1 0 1 0
1 1 0 0
X
1 1 1 1

1) Give the logical expression of X as a function of A, B, C

2) Derive the simplified logical expression of X using Karnaugh's table
3) Give the designation and role of the V, Ai and Ei inputs of the 74151 multiplexer IC above.
4) Draw up the truth table for this MUX 74151.
5) Wire the MUX 74151 IC to generate function X. NB: Variable A is the LSB and
variable C is the LSB.

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EXERCISE 6: Study of a multiplexer

1) Consider the following diagram of a multiplexer wired as a function generator
1.1) Which family does the 74151 logic circuit belong to? Justify your answer and give the value of
the +Vcc voltage.
1.2) Identify the different pins of this multiplexer and give their role
1.3) Give the output equation of function F and simplify it using Karnaugh's method
1.4) Implement the simplified function using 2-input 2-input NAND gates only

A B C D
+Vcc

A1 E0 E E E1 2 E4 E5 E E6 7
3
A2
A3 74151
V

F
2) Let be the function 𝑍 = 𝐴𝐵𝐶 + 𝐴̅𝐵 + 𝐶̅
2.1) Give the truth table of the multiplexer used to achieve this, considering ABC as the address
inputs and Z as the output; A being the least significant bit.
2.2) Give the wiring diagram of this MUX, showing how to establish the interconnections of its
information inputs.

EXERCISE 7:
Design a circuit to implement the logic function
3.
specified in the following table using an 8-input multiplexer,
4.

EXERCISE 8:
5.
Consider the diagram opposite:

1) Give the equation of S as a function

of A, B, C, D and E.
2) Create your own logic diagram
u s i n g the logic gates of your
choice
3) Draw up the truth table for this
circuit

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EXERCISE 9: Study of the SN74LS138N decoder

The SN74LS138A circuit is a decoder with three address inputs (A, Y0

B and C) and three enable inputs (E1 , E2 and E3 ) and eight outputs, A
Y1

as shown in the adjacent figure. B Y2

1) Justify that this is a digital integrated circuit C Y3

74LS138 Y4
2) Give the designation of each code characterizing this circuit Y5

3) Define decoder and describe its areas of application Y6

E1
4) Give the operating table for this circuit E2
E1
E2
Y7
E3
5) Write the equations for the outputs ̅ Y 0 , ̅Y5 and ̅Y7 then E3

perform their logigrams using two-input NAND gates.

EXERCISE 10: Creating a 1of-8 decoder from two 1of-4 decoders:

ST: active validation input on high level

1. Establish the truth table of the circuit.

2. Determine the output functions Yi = f(B, A).
3. Give an implementation with NAND gates.
4. Show how a 1-of-8 decoder can be made using two 1-
of-4 decoders, then draw up its truth table and give its
logigram.

EXERCISE 11: Study of a BCD 7 Segment decoder

We want to display on a 7-segment display the counting order of a process through a BCD / 7-
segment decoder with active outputs at high level. Each segment of the display is symbolized by a light-
emitting diode whose cathodes are common and connected to 0V.

U1
7 13
A QA
1 12
B QB
2 11
C QC
6 10
D QD
4 9
BI/RBO QE
5 15
RBI QF
3 14
LT QG
74LS48

1) Show how to wire this circuit,

2) Give the truth table of this decoder
3) Simplify the output equations. Remember that A is the LSB and D is the MSB.
4) Name the different types of display found in digital signage systems. Which one consumes less
energy?

By searching for so long without finding, you end up finding without searching.
"He who finds without seeking is he who has long sought without finding". Gaston Bachelard
"Thinking signifie to go beyond." Ernst BLOCH (1885-1977)

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SOLUTION EXERCISE 9: Study of the SN74LS138N decoder

The SN74LS138A circuit is a decoder with three address inputs (A, B and C) and three enable inputs
(E1 , E2 and E3 ) and eight outputs, as shown in the adjacent figure.

1) Justify that this is a digital integrated circuit

2) Give the designation of each code characterizing this circuit
3) Define decoder and its fields of application
4) Give the operating table for this circuit
5) Write the equations for the outputs ̅ Y 0 , ̅Y5 and ̅Y7 then perform their logigrams using two-input
NAND gates.

SOLUTION: Study of the SN74LS138N decoder

1) Justify that this is a digital integrated circuit

This is a digital integrated circuit, since the "S" series represents digital
integrated circuits ("T" for analog circuits and "U" for analog-digital circuits).
2) Give the designation of each code characterizing this circuit
SN: manufacturer's code
74: TTL series
LS: TTL subfamily (Low power Schottky type) 138:
Serial number
N: Housing type

3) Define decoder and describe its fields of application

A decoder: this is a combinational logic circuit that maps an N-bit input code to M
outputs such that 𝑀 ≤ 2𝑁 .

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4) Give the operating table for this circuit

Inputs to Inputs
Outputs
validation addresses Observation
E1 𝐸 ̅2 𝐸 ̅3 C B A 𝑌 ̅7 𝑌 ̅6 𝑌 ̅5 𝑌 ̅4 𝑌 ̅3 𝑌 ̅2 𝑌 ̅1 𝑌 ̅0

0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1 Blocking
X X 1 X X X 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1

100 0
1
1
0
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
Normal operation

1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1

5) Write the equations for the outputs Y̅0 , Y̅5 and Y̅7 and then produce their logigrams
using two-input NAND gates.

𝑌̅0 = ̅𝐶̅𝐵̅𝐴̅ = 𝐶 + 𝐵 + 𝐴

𝑌̅5 = ̅𝐶̅𝐵̅𝐴̅ = 𝐶̅ + 𝐵 + 𝐴̅
𝑌̅5 = ̅𝐶̅𝐵̅𝐴̅ = 𝐶̅ + 𝐵̅ + 𝐴̅

C B A

Y0

Y5

Y7

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CHAPTER 5: DIGITAL INTEGRATED

CIRCUIT TECHNOLOGY
Target skills :
By the end of this lesson, learners should be able to :
- Characterize digital integrated circuits;
- Carry out a comparative study of the different technological families (TTL and CMOS) with a
view to making choices applicable to digital circuits.

INTRODUCTION
A logic circuit takes the form of an integrated circuit, in which a maximum number of electronic
components (resistors, diodes and transistors) are grouped together in a single package. Integrated
circuits make digital systems more reliable, since they reduce the number of interconnections between
their various components. The widespread use of integrated circuits makes it essential to know and
understand the technological, physical and electrical characteristics of most families of integrated logic
circuits.

Logic integrated circuits are designated by the complexity of the circuits they carry. This
complexity defines the number of gates on the chip. This is referred to as an integration class.

V- Integration classes
There are five classes of integration:
• SSI (Small Scale Integration): 12 doors maximum.
• MSI (Medium Scale Integration): 12 to 99 doors
• LSI (Large Scale Integration): 100 to 999 doors
• VLSI (Very Large Scale Integration): 10000 to 99999 gates
• ULSI (Ultra Large Scale Integration): over 100,000 doors
Depending on their manufacturing technology, logic ICs are classified into several logic
families.

VI- Integrated circuit logic families II.1-

Definition
A logic family is a homogeneous set of components capable of performing basic logic
operations. There are a multitude of logic families. The oldest are :

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•The RTL (Resistor Transistor Logic) family: These are integrated circuits consisting o f
input resistors and output transistors.
• The DTL (Diode Transistor Logic) family: It uses diodes as inputs and transistors as
outputs.
These first two families appeared in 1964 and have now completely disappeared. In this chapter,
we'll look at the two most recent and currently popular families, namely :
• The TTL (Transistor Transistor Logic) family: uses bipolar transistor technology;
• The CMOS (Complementary Metal Oxide Semiconductor) family: uses MOS transistor
technology.

Each logic family is characterized by electrical parameters such as power supply and
consumption, and dynamic performances such as propagation delay.

VII- Characteristic parameters of logic integrated circuits

These are: case, power consumption, temperature range, logic levels, supply voltage, current
consumption, edge propagation time, load factor.

1- Supply voltage :
- TTL logic family: The power supply must be fixed and equal to 5V with a tolerance of ± 5%.
- CMOS logic family: wider choice of supply voltage, from 3V to 18V.

2- Logic levels :
For a given family, the logic levels "0" or "L" (Low) and "1" or "H" (High) do not correspond to a
precise voltage (or current), but to a certain voltage (or current) "range".
Definition of common terminology
ICC : supply current
IIH : High Input current IIL : Low Input current IOH :
High Output current IOL : Low Output current IOS :
Short-circuit current (output to ground)

VCC : supply voltage for TTL circuit

VDD : supply voltage for CMOS circuit
VIH : High Input Voltage VIL : Low Input Voltage VOH :
High Output Voltage VOL : Low Output Voltage
Manufacturers generally specify mimima and maxima voltages and currents to represent these
quantities in their catalogs.

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• VIHmin : Minimum input voltage to ensure high logic level.

• VILmax : Maximum input voltage to ensure low logic level.

• VOHmin : Minimum output voltage in high logic state.

• V0Lmax : Maximum output voltage in low logic state.

3- Power consumption
This is the power required by its housing from the supply circuit.
All ICs, when in operation, consume a certain amount of electrical energy. This energy is
supplied by one or more supply voltages connected to the supply pins on the package. This voltage is
called VCC for TTL or VDD for CMOS.

PC = VCC x ICCmoy where ICCmoy

= ICCH+ICCL
2

4- Propagation time
In an integrated logic circuit, quantities are transmitted with a delay characteristic of the gate:
this is the propagation time of the information in the gate. A distinction is then made between a high-low
transition (falling edge) and a low-high transition (rising edge):

Fig: Illustration of propagation time

TpHL : Propagation time High to Low of the
logic signal when the output goes from high to low.
TpLH : Propagation time Low to High of the
logic signal when the output goes from low to high.
To ensure these times are measured, a
voltage reference is set by the manufacturers (1.3 V
in TTL) for the start and end of propagation, as
shown opposite:

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The propagation time tpd is the time it takes for the circuit to modify its output following a change in input
level. Tpd = TpHL+ TpLH
2

5- Quality factor :
This is the product of propagation time and power consumption.

𝐅∶ in pico joule (pj)

F = Tpd x PC with {Pc in watts (𝑊)
Tpd in nanoseconds (ns)

6- Load factor :
A logic gate cannot accept an unlimited number of gates
connected to its output. For each logic IC, it is therefore possible
to interconnect other ICs within the limits specified by the
manufacturer. The load factor is defined by the circuit's input and
output.

a) Fan out
The maximum number of loads (of other integrated circuits) that it is capable of driving from a
single output is called its output.
• Low-level output : • High-level output :
𝐼𝑂𝐿 𝑚𝑎𝑥 𝐼𝑂𝐻 𝑚𝑎𝑥
𝑆𝐿= (in logical units) 𝑆𝐿= (in logical units)
𝐼𝐼𝐿 𝑚𝑎𝑥 𝐼𝐼𝐻 𝑚𝑎𝑥

b) Entrance
It corresponds to the value of the input control current of a logic circuit expressed in number of
loads.

To simplify calculations, the manufacturers have decided to use a unit load corresponding to 40
µA in the high state and 1.6 mA in the low state. These values correspond to the input current for the
standard TTL series. In the high state, IIH (max) = 40 µA represents the maximum current flowing
through a standard TTL input. Similarly, in the low state, IIL (max) = 1.6 mA represents the maximum
current in the input in the low state.

• Input low level (Input low)

𝐸𝐿 = 𝐼𝐼𝐿 (in logic units for a standard TTL IC)
𝑚 𝑎 𝑥
16×10-3

• High-level output :

𝑆𝐿 = 𝐼𝑂𝐻 (in logic units for a standard TTL IC)

𝑚 𝑎 𝑥
40×10-6

7- Noise immunity :
Noise is a parasitic signal induced in the circuit and superimposed on the transmitted signal.
Noise immunity is the amplitude tolerance that the circuit can withstand to identify signals correctly.

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The VNH (Noise High) sensitivity margin is defined as follows:

VNH = VOH (min) - VIH (min)
Similarly, at low level, we define VNL = VIL (max) - VOL (max)

Figure: Representation of noise immunity

8- Temperature range:
Several operating temperature ranges are available:
- Military range: -55°C to +125°C
- Commercial range: -40°C to +85°C
- Industrial or civil range: 0°C to +70°C

9- Type of housing
This is the shell in which the chip is encapsulated, and which also carries the integrated circuit
pins. It can be made of plastic or ceramic.
We distinguish :
• Round cases (which have almost disappeared)
• Flat packages
The flat housings are very thin and a r e soldered on the
component side.

• DIL or DIP boxes (Dual In Line or two rows of lugs)

These
- are the most common, with 8 to 64 pins divided
into 2 lines. DILs are available in plastic or ceramic,
depending on the material used to protect the circuit.

• SIL (Single In Line) enclosures

• SO (Small Outline) enclosures

They resemble the DIL box, but with the space between the legs
reduced by a ratio of 2.)

• Pin Grid Array boxes

They are indicated when the number of connections becomes very large.
Example: the microprocessor

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VIII- Integrated logic circuit technology

Integrated logic circuits are divided into two technologies:

IV.1- TTL (Transistor-Transistor-Logic) technology

These ICs are based on NPN or PNP bipolar transistors. There are 7 logic families in TTL technology:
• TTL Standard: 74xx: Logic family no longer commonly used.
• TTL Low Power : 74Lxx : TTL logic circuits with low current consumption.
• TTL Schottky : 74Sxx : Fast logic circuits based on Schottky diodes.
• TTLFast : 74Fxx: Logic circuit with very low propagation time, thus increasing speed.
• TTL Low Power Schottky: 74LSxx: TTL circuit combining the advantages of 74Lxx and
74Sxx circuits, i.e. high speed and low current consumption.
• TTL Advanced Schottky: 74ASxx: Very fast logic circuits, capable of operating a t high clock
frequencies.
• TTL Advanced Low Power Schottky: 74ALSxx: These circuits combine the advantages of the
74ASxx and 74Lxx: low power consumption and high speed. Most frequently used.

IV.2- CMOS (Complementary Metal Oxide Semiconductor) technology

These circuits are based on MOSFET transistors. There are 6 logic families
are :
• Classic CMOS: 4000 series (power supply from 3 to 18 V)
• Classic CMOS: 74Cxx.
Identical in technology to the 4000 series, this logic family is pin-for-pin and function-for-function
equivalent to the 74xx logic family. These circuits are 50% faster than the 4000 series and accept 50%
more current. This logic family has levels compatible with TTL logic.
• Fast CMOS: 74HCxx , 74HCTxx, 74 ACxx and 74 ACT
74HCxx :Fast CMOS like the TTL LS family, power supply from 2 to 6V)
74HCTxx : 5V power supply, this 74HCT family is fully compatible w i t h TTL circuits. These two
logic families also have the advantage of being fast.
74 ACxx (CMOS even faster than the HC family) and 74 ACTxx (TTL-compatible AC CMOS).

IX- Logic families and their functions

1- DTL (Diode Transistor Logic) family
These are integrated circuits made up of diodes and transistors operating in switching mode (acting
like switches). Diodes let current flow in one direction only.

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The function implemented here is the NAND

function
ATruthBtable : Q
0 0 1
0 1 1
1 0 1
1 1 0

"1" = Vcc and "0" = 0 (ground)

2- TTL family (Transistor Transistor Logic)
Multi-emitter transistor

Transistors operating in switching mode (or

in saturation)
If at least one emitter of T1 is low, then
transistor T2 cannot conduct and output Q will be
high. This output Q is low when inputs A and B
are high. T1 T2
The truth table is identical to the previous
one.
3- CMOS (Complementary Metal Oxide Semiconductor) family
The MOSFET transistor is voltage-controlled at its gate, while the bipolar transistor is controlled by a base
current.
B: Substrate; G: Grate, D: Drain; S: Source

Fig: Characteristics of an enrichment MOS

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3.1) Elementary gate of the CMOS family :

Figure 2 shows the basic structure of a CMOS INVERTER gate based on two complementary MOS
transistors: VDD : Supply voltage

• If a low level is applied to the input, transistor T2 (MOS N) is

blocked because its gate voltage is zero. Transistor T1 (MOS P), on
the other hand, is conductive because its source gate voltage is equal
to -5V:
output S is at logic level 1 ;
• If a high level is applied to the input, transistor T1 is blocked
because its source gate voltage is zero. Transistor T2 is conductive
because its source gate voltage is equal to 5V: output S is at logic
level 0;

• The assembly creates an inverse gate.

CMOS inverter: NO function

3.2) NAND and NOR CMOS gates

The two basic gates NAND and NOR are obtained by connecting the MOS-FET transistors either in
series or in parallel. For the NAND gate, only one input needs to be "L" for the output to be "H", since
Q1 and Q2 in parallel ≡ 'OR'. For the output to be "L", both inputs must be "H", as Q3 and Q4 in series
≡ 'AND'. For the NOR gate, only one input needs to be "H" for the output to be "L" and both inputs need
to be "L" for the output to be "H".

Work to be done:
Draw up the truth table for
each circuit, indicating the
state of each transistor for
each input combination.

NAND CMOS carrierNOR CMOS carrier

X- Advantages and disadvantages of TTL and CMOS circuits

Circuits TTL CMOS

• Good noise immunity. • Variable power supply from 3V to 18V.

• High switching speed (low • Low energy consumption
Benefits propagation time)
• Excellent noise immunity
• Good luck
• High integration density
• High energy consumption • Lower switching speed than TTL
technology (long propagation times)
• Power supply must be accurate to 5V
Disadvantages +/- 5% otherwise the circuit may be • Weak fate
destroyed.

By ZEUMO Stève Marius, PLET F2 - LT BANGANG - School year 2019/2020 Page 67

 DIGITAL CIRCUITS COURSE - PF3

XI- Code and designation

Digital integrated circuits are designated by a code of letters and numbers, as shown in the
example below.
SN 74 LS 18 A
SN: Manufacturer's code: not shown on some circuits
74: Series (there are also 74 or 54 series for the TTL family and 40 or 45 for CMOS
technology, sometimes also 74)
LS: TTL subfamily
18: Circuit number (defines function, up to five digits)
A: Case type

NOTES: In the European PRO-ELECTRON code, the first letter identifies the type of
integrated circuit. Thus :
✓ S: digital circuit
✓ T: analog circuit
✓ U: mixed digital/analog circuits

Application exercises
From the 74LS00 manufacturer's documentation, which you will download from the Internet, determine
the following characteristic values (Temperature: 25°C):
- Supply voltage Vcc ; VILmax ; VIHmin ; VOLmax ; VOHmin ; PCmax ; Sortance (high) ; Sortance (low) and
Maximum propagation time tpd

Same exercise for 4011

IMPORTANT NOTE: Make the handwritten summary on 3 pages of worksheet.

By ZEUMO Stève Marius, PLET F2 - LT BANGANG - School year 2019/2020 Page 68

 DIGITAL CIRCUITS COURSE - PF3

TD4: DIGITAL INTEGRATED CIRCUIT TECHNOLOGIES

EXERCISE 1: DIGITAL INTEGRATED CIRCUIT TECHNOLOGY

1) Define the following terms and expressions: TTL; DTL; CMOS; ECL, Integrated circuit; Load
factor; Sortance; Input; Delay; Noise immunity; Combinatorial system
2) Give 3 advantages and 3 disadvantages for each of the TTL and CMOS technologies.
3) Classify TTL circuits (SN74xx; SN74Lxx; SN74Sxx; SN74Fxx; SN74LSxx; SN74ASxx and
SN74ALSxx) by power consumption and speed
4) Name the different types of integrated circuits you know.
5) There are two types of LED displays: which are they?

EXERCISE 2: DTL TECHNOLOGY

Consider the figures below, where the diodes are perfect and the transistors operate in saturation
mode. M is a stepper motor (DC motor). e1 = e2 = vcc = 5V

RC2
RC1
R2
R1
D1 T2 D3
5V
R2 VCC R3
T1 5V T
D2 D4 M
e1 e1
R1
M
e2 e2

Figure 2
Figure 1
1) Describe the operation of an ideal diode
2) Describe the operation of a transistor in saturation mode
3) Analyze the circuits, establishing the truth table for each figure.
4) Deduce the function performed by each circuit.

By ZEUMO Stève Marius, PLET F2 - LT BANGANG - School year 2019/2020 Page 69