Ministry of higher education and

scientific research

Course: Computer Architectre 2

Dr. Tayeb Benzenati, Ph.D
University of Boumerdes, Faculty of Science,
Dep. of Computer Science,
last updated: September 28, 2024

1
 Objectives of the course
At the end of this course, the student should be able to design a
basic computer. Specifically, they should:
✓ Understand the role of each component in the data path of
a calculator.
✓ Understand the basic mechanisms that allow a calculator to
communicate (input/output and interrupt systems).
✓ Master the flow of information in basic circuits and
understand the operation of the control unit (sequencer).

2
Chapter 2:
Memories

3
 Main caracterestics of a memory

Access Operation
Volatility Material Capacity
Mode mode
• Random • Read • Volatile • Optic • Megabyte
• Sequential • Write • Non- • Magnetic • Gigabyte
• Associative volatile • Semi-
conducter

4
 Basic structure of Memory
• A memory can be represented as a
table with a set of rows.
• Each row represents a memory cell
that can contain data or an
instruction.
• Each row has a unique address.
• The stored data can be accessed
only via their addresses.

5
 Caracteristics of a memory
• Capacity: It indicates the total number of bits (words) that can
be stored in memory, expressed in bits.
▪ 1 byte = 1 Bytes = 8 bits
▪ 1 kilobyte = 1024 bytes
▪ 1 megabyte = 220 bytes
• Access Time: It represents the time that elapses between the
moment the information request is made (Read/Write) and the
moment the information is available on the data bus.

6
 Access time (latency)

Read/right request
Access
time

Availability of the
information

7
 Caracteristics of a momory
• Access Mode to Information: This depends on the
organization of information on the medium. There are two
types:
▪ Sequential Access: To access information, it is necessary to go through
all the preceding data. Consequently, the access time varies based on
the position of the information (example: magnetic bands).
▪ Direct Access: Each piece of information has its own address. The
access time is constant and independent of position. Example: RAM and
ROM.

8
 Caracteristics of a momory
• Operation Mode:
There are two types :
▪ Read/Write Memory: It is possible to read and write at will. This
type of memory is also called volatile memory.
▪ Read-Only Memory: These are memories accessible only for
reading. Writing may require a specific and/or complex
device/procedure. They are also referred to as non-volatile
memory.

9
 Caracteristics of a momory
Volatility
▪ Volatile Memories: They lose
information when the power
source is turned off. They need
electric current to maintain
programs and data temporarily
▪ Non-volatile Memories: These
include memories capable of
storing information permanently
(even without power).

10
 Caracteristics of a momory
Storage Technology: There are three technologies based on the
information storage medium :
• Electronic Memories based on Semiconductors: Their basic element is
the transistor. Example: RAM and ROM.
• Magnetic Memories: These use magnetic media and allow for the
storage of large amounts of information at a low cost (Example: hard
disk).
• Optical Memories: These use a laser-based system for information
storage. Example: CD-ROM.

11
 Main Memory
• Also known as primary memory.
• It is the most important unit after the processor.
• The processor and memory have a closely correlated
relationship, so neither unit can function effectively without the
other.
• Data and instructions circulate between the processor and
central memory via buses.

12
 Structure of the Main Memory (1)
To effectively fulfill its role, the CM requires:
• A storage mechanism to retain information.
• An addressing mechanism to locate the position of
information.
• An input/output mechanism for the acquisition or retrieval of
information.

13
 Structure of the Main Memory (2)
To achieve this, central memory is composed of three elements:
• Storage/Memory Circuits: These are the memory cells capable of
storing information (e.g., registers).
• Addressing Logic: This represents the technique used to address a
word in central memory. It comprises :
▪ Memory Address Register (MAR): This registers the address of the word in
question in memory.
▪ Decoder (Decoding Logic): This precise the effective address of the
requested word in memory.
• Input/Output Logic: This includes the set of circuits that enable the
reading or writing of a memory word. It includes:
▪ Memory Information Register (MIR): This temporarily holds the information
read or to be written.
▪ Input/Output Interface: This contains the three-state amplification circuits
for input and output information (Three-state buffers, multiplexers, etc.).
14
 Addressage logic Stockage/Memory Logic

Cell Cell Cell

Address
Bus
Cell Cell Cell
M

Decoder
A
R

Structure of the Main

Read
Write
Memory (3) Cell Cell Cell

𝑅/𝑊
Amplifier circuits
𝐶𝑆

MAR : Memory Addrees Register

MIR : Memory Instruction Register MIR
I/O Logic

Data Bus
15
 Storage/memory Logic
• The elementary information (the bit) is stored in a single
memory cell.
• These cells are grouped into words of n bits.
• The memory cells are grouped into words of fixed word length,
for example, 1, 2, 4, 8, 16, 32, 64 or 128 bits.
• Each word can be accessed by a binary address of 𝑁 bits,
making it possible to store 2𝑁 words in the memory.

16
 Storage/memory Logic (2)

𝑘
𝑎𝑑𝑑𝑟𝑒𝑠𝑠 𝑙𝑖𝑛𝑒𝑠 2𝑘 words n bits

𝑹/𝑾
n input n output
lines line

17
 Storage/memory Logic (3)
• To address each word, k address lines are required. The first
word is placed at address 0, and the last at address 2ᵏ − 1.
• Reading a word requires n output lines for retrieval.
• Writing also requires n output lines for storage.
• The (𝑹/𝑾) control line indicates the access mode to the block,
either read (R: READ : 1) or write (W: WRITE : 0).
• An input/output mechanism is used for the acquisition or
retrieval of information.

18
 Addressing Logic
• The addressing logic depends on the
internal design of memory.
• It refers to how memory locations are Addressage
identified and accessible. modes

• Its objective is to minimize circuit One- Two-

costs while maintaining optimal dimensional dimensional
performance.
• Generally, memory is structured in the
form of a table or a matrix (i.e., rows
and columns).

19
 One-dimensional Addressing
• The most basic organization consists of assigning:
▪ Rows for addresses
▪ Columns for data
• Each row represents a word of n bits.
• Each cell is identified by the intersection of its row and column
index.
• The decoder activates one of the 2ᵏ rows (one word).
• Only the cells corresponding to this address are selected, and
the information is read or written.

20
One-dimensional Addressing (2)
2𝑘 address
𝑘 Address rows
rows
Cell Cell Cell

Cell Cell Cell

M

Decoder
A
R

Cell Cell Cell

𝑛 columns

21
 Selecting a word memory
• When an address is loaded into the MAR, the decoder receives the same
information as that stored in the MAR.
• At the decoder’s output, a single output is activated, allowing to select a single
word from the memory.
2𝑘 address
𝑘 Address rows
rows
Cell Cell Cell
𝑆𝑒𝑙𝑒𝑐𝑡 𝑤𝑜𝑟𝑑
Cell Cell Cell
M Decoder
A
R

Cell Cell Cell

𝑛 columns 22
 Two-dimensional Addressing
• Also known as XY addressing.
• It splits the address into two parts: row address and column
address.
• Two address registers (𝑀𝐴𝑅𝑥 ​ and 𝑀𝐴𝑅𝑦 ​) are required to store
the two parts of the address, along with two decoders.
• Selection principle: A cell is selected by the intersection of the
outputs from the row decoder (𝑀𝐴𝑅𝑥 ​) and the column decoder
(𝑀𝐴𝑅𝑦 ​).

23
Two-dimensional Addressing (2)
Cell Cell Cell

M Cell Cell Cell

Decoderx
A
R
X

Cell Cell Cell

DecoderY
Address Bus
MARY

24
 Example
• Let be a memory of 256 words of 10 bits.
• Design this memory with a one-dimensional structure, then
with a two-dimensional structure.
• Compare the number of the required address circuits for the
two possible organizations.

25
• Memory XY :
▪ Optimise l’accès à la mémoire : On peut lire ou écrire des blocs (mots) complets
(lignes/colonnes), ce qui accélère les opérations.
▪ Réduit le câblage : Moins de lignes d'adresse sont nécessaires qu’en adressage
linéaire sur de grandes mémoires.
▪ Logique d’accès plus complexe : Nécessite un décodage pour sélectionner à la fois la
ligne et la colonne.
▪ Plus coûteux à implémenter que l’adressage à une dimension.
• Memory of one dimension :
▪ Facile à implémenter et rapide à accéder.
▪ Ne nécessite pas de logique complexe pour accéder à une position en mémoire.
▪ Peu adapté aux mémoires de grande taille ou aux structures de mémoire organisées
en matrices, car cela devient inefficace.

26
 Calculating the Capacity of Memory
• Let 𝑘 be the size of the MAR register (address bus size).
• Let 𝑛 be the size of the RIM register (memory word size or
data bus).
• The capacity of the main memory is represented in terms of
the number of memory words or in bits (bytes, kilobytes, etc.):
▪ 2𝑘 memory words of 𝑛 bits
▪ Capacity = 2𝑘 × 𝑛 𝑏𝑖𝑡𝑠

27
 Example
• In a memory, the size of the address bus is 8 and the size of
the data bus is 10 bits.
▪ Calculate the capacity of this memory.

28
 Data retrieval (lecture d’information)

• To get a data in main memory, it is necessary to perform the

following steps:
1. Load the address of the word to be read into the MAR.
2. Initiate the read command (𝑹/𝑾=1).
3. The information will be available in the MIR after a certain time (i.e., the
access time).

29
 Writing Data
• To write information to main memory, it is necessary to
perform the following steps:
1. Load the address of the word to be written into the MAR.
2. Store temporary the information to be written into the MIR.
3. Initiate the write command (𝑹/𝑾 =0) to place the contents of the RIM
into the desired memory address.

30
 Memory Design
• We aim to create a memory 𝑀 with a capacity of 𝑛 × 𝑚.
However, we only have smaller chips 𝑀′ (circuits) with a size
of 𝑛′ × 𝑚′.

Ship Memory Capac𝑖𝑡𝑦

𝑛′ Capacity 𝑛
𝐶′
𝐶

𝑚′

𝑚
31
 Structure of a Chip
• The structure of a chip is similar to that of 𝑅𝑊 𝐶𝑆
standard memory (RAM, RIM, etc.).
However, it also incorporates a specific 𝐶𝑆
command (Chip Select).

Decoder
M
A Chip
• 𝐶𝑆 : is an active-low signal used to select R
(enable) or disable the chip.
▪ 𝐶𝑆 = 0: The chip is selected and ready for use. MIR
▪ 𝐶𝑆 = 1: The chip is not selected (standby or idle).

32
 Calculating the required number of chips
• Let 𝑀 be a memory with a capacity 𝐶, where 𝑛 is the number of
words, and 𝑚 is the size of each word.
• Let 𝑀′ be a smaller chip with a capacity 𝐶′, where 𝑚′ is the
number of words, and 𝑛′ is the size of each word.
• Note that 𝑛 ≥ 𝑛′ and 𝑚 ≥ 𝑚′ (i.e., 𝐶 > 𝐶′).

How many chips 𝑀′ are required to

construct the memory 𝑀?

33
 Calculating the required number of chips (2)
• To determine the required number of chips, the following two factors must
be calculated:
𝑛
▪ P=⌈𝑛′⌉ [.] : ceiling function
𝑚
▪ Q=⌈ 𝑚′⌉
▪ P: This factor determines the number of chips 𝑀′ needed to achieve the total
number of words in memory 𝑀 (row extension).
▪ 𝑄: This factor determines the number of chips 𝑀′ required to achieve the word
size in memory M (word or column extension).
• 𝑷 × 𝑸: Total number of chips needed to model the memory 𝑀.
• To select the desired chip, the most significant address bits are used. If 𝑃
is the row extension factor, then 𝑘 bits are taken such that 𝑃=2𝑘 .
• The remaining address bits are used to select the word within the
corresponding chip.

34
Calculating the required number of chips (3)
MAR
𝐴𝑛 𝐴𝑛−1 𝐴𝑛−2 … 𝐴1 𝐴0

K bits Nbr of @ words of C –k

Desired Chip Address of the word within the
selection corresponding chip.
𝑘 = 𝑙𝑜𝑔2 (𝑃)

35
 Example 1
We want Construct a memory of 1 KB, with each word consisting
of 8 bits, using chips that each contain 256 words of 8 bits.
• How many chips do we need ? Calculate the P and Q
• Illustrate the content of the MAR
• Create a conceptual diagram of this memory.

36
 Example 2
We want to construct a memory consisting of 1024 words,
where each word is 16 bits in size.
To achieve this, utilize chips that have a capacity of 1024, with
each word being 4 bits in size.
• How many chips do we need ? Calculate the P and Q
• Illustrate the content of the MAR
• Create a conceptual diagram of this memory.

37
 Exemple 3
• Same questions :
Build a memory of 1 KB (where the word size is 8 bits) using
chips with a size of 512 words of 4 bits each.

38
 Design of the main memory
• Does the architecture of main memory influence the
performance of the machine, particularly its CPU ?

39
 Single Processor Architecture
• In this type of architecture, the computer includes a single
processor (central processing unit) for processing.
▪ The CPU has exclusive access to the memory. It can access it whenever
it desires.
• The performance of the CPU depends on the access time to
the main memory.
▪ A slow main memory significantly slows down the central processing
unit (the CPU inactive because it must wait for the requested information
from memory)

CPU Memory

40
 Multi-Processor Architecture
• When multiple processors work in parallel (at the same time),
this leads to a high likelihood of simultaneous access requests
to main memory.
• The access time to memory is no longer the only factor
affecting the CPU's wait time.
• If the memory is organized as a single block, only one
processor can access it at a time.
• This results in significant waiting time for the other
processors, leading to an inevitable drop in performance.

41
 Factors of Main Memory Affecting CPU Performance
• Two main factors of main memory that can impact processor
performance are:
1. The time it takes to access data in memory (memory latency).
2. The design and layout of main memory:
♦ Whether memory is organized as a single block or multiple blocks.
♦ How processors access memory.

How could we design a main memory without losing

the performance of the CPU ?

42
 Solution 1: Modular Memory
• Called also Memory banks
• The first solution is to divide memory into multiple modules.
• Multiple buses provide simultaneous access to different modules.
• It allows for as many accesses as there are modules.
• However, simultaneous access to a single module is not feasible.
Notes M1 M2 M3 M4
• Addresses within a module are organized on
a sequential fashion.
• A module can consist of smaller-sized units
(it’s necessary to calculate the line and 𝑃1 𝑃2
column extension factors).
43
Example

44
 Solution 1: Modular Memory (2)
• The address is divided into two parts:
▪ The high-order bits are used to select the desired module. If the number
of modules is n, then k bits are needed such that 2𝑘 ≥n
▪ The low-order bits are used to select the word within the corresponding
module.

Module’s number Word’s address

45
 Exemple
Consider a memory of size 4 KB. This memory is divided into 4
modules.
• Determine the address bus size.
• Provide a diagram of this memory using 1 KB units.

46
 Modular Architecture drawback
• In this type of architecture, a main memory module can be
monopolized by a single processor during the execution of a
program.

Principle of Spatial Locality

• If a processor accesses a specific memory address, it is
very likely that it will also access nearby memory
addresses within the same module.
• In other words, when the processor reads from or writes
to a memory address, it tends to access other memory
addresses located close by in physical memory.

47
 Solution 2 : Interleaved Memory
To prevent this issue:
• The solution is to interleave (fr: entrelacer) the addresses.
• The memory is divided into blocks.
• The difference is that consecutive addresses are not placed
one after the other within a single block but are instead
distributed across consecutive modules (units).
• The number of blocks represents the degree of interleaving.

48
Exemple

49
 Selecting a word in an interleaved memory
• The address is divided into two parts (the reverse of classic
modular memory).
• The high-order bits are used to select the desired block.
• The low-order bits are used to select the word within the
selected block.

Word address Module number

50
 Exemple
• An interleaved memory with a degree of interleaving equal to
2, where each block is of size 4 words.
▪ Interleaving degree = 2 => 1 bits to select the module
▪ 4 words => 2 bits to select the word

𝑨𝟐 𝑨𝟏 𝑨𝟎
Word Module
Module 0 Module 1
000 001

010 011

100 101

110 111
51
 Exemple
• Create a memory with a capacity of 512 words of 8 bits each,
using units of 128 words of 8 bits and a degree of interleaving
of 4.

52
 Interleaved Memory drawbacks
• If a failure (une panne) occurs in one of the blocks, it makes
the entire memory unusable.
• This is because the program is distributed across all memory
blocks (two successive addresses are located in two
successive blocks).

53
 Interleaved Modular Memories
• The central memory is structured into several modules.
• Each module is divided into n blocks (where n denotes the
degree of interleaving).
• To select a word:
▪ The module must be selected (high-order bits).
▪ The block must be specified (low-order bits).
▪ The word address must be provided (remaining bits in the middle).
Module number Word address Block number

54
The end

55