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Mod 2 Question Bank

The document outlines various tasks related to digital circuit design, including the implementation of multiplexers, adders, encoders, and decoders using different logic gates. It also covers the explanation of concepts such as magnitude comparators, priority encoders, and ripple carry adders. The tasks require designing circuits and explaining their operations, emphasizing practical applications of digital logic in circuit design.

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22 views1 page

Mod 2 Question Bank

The document outlines various tasks related to digital circuit design, including the implementation of multiplexers, adders, encoders, and decoders using different logic gates. It also covers the explanation of concepts such as magnitude comparators, priority encoders, and ripple carry adders. The tasks require designing circuits and explaining their operations, emphasizing practical applications of digital logic in circuit design.

Uploaded by

peven85722
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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PAPER NAME: Digital Circuit Design

PAPER CODE: ECE2002

MOD 2

1. Implement a 16:1 multiplexer using 4:1 multiplexers.


2. Implement a full adder circuit using decoder and OR gates.
3. Explain the operation of an octal to binary encoder.
4. Implement the logic function using 8:1 multiplexer

5. Design a four-bit binary parallel adder circuit using full-adder circuit blocks.
6. Explain the operation of the magnitude comparator with a suitable diagram.
7. Design a 4 input priority encoder with inputs D0, (LSB) D1, D2, and D3, (MSB) and outputs
Y0 Y1. Input D3 shall have highest priority and D0 shall have the lowest priority.
8. Explain the advantages of a priority encoder over a standard encoder using illustrative examples
with 4-line to 2-line standard encoder and a priority encoder.
9. A 8 to 1 MUX is used to implement a function F(A,B,C,D). It has inputs A, B, C connected to
selection lines S2, S1, and S0. The data inputs I0 to I7 are as follows. I0=I1=I5=D, I2=D’, I6=I7=1,
I3=I4=0. Determine the function F(A,B,C,D).
10. Design a single stage BCD adder and explain why addition of six is necessary?
11. Design a one bit Full adder using a 3 to 8 decoder and OR gates.
12. Design a four input (D3-D0) priority encoder having priority in increasing order of sequence. Input
D0 having the lowest, and D3 the highest priority.
13. Draw the logic circuit of the 3-bit Odd-cum-Even Parity Generator and Checker circuit.
14. Realize a full adder circuit using a 4:1 multiplexer.
15. Implement 8:1 Multiplexer by 4:1 Multiplexer.
16. Design a full subtractor using only NAND gates.
17. Show how a 16-input MUX is used to generate the function
Y=(ABC)’D +BCD+A(BC)’+ABC’D
18. Implement a 2:4 decoder with 1:2 decoder
19. Implement the following with 2:4 decoder and OR gates :-
(i) Half Adder (ii) Half Subtractor
20. Implement a 8:1 Multiplexer with 2:1 Multiplexer
21. For a 4 variable function, Y = f(I3, I2, I1, I0), implement with 8:1 Multiplexer the following :-
(i) When the equivalent decimal value of the binary signals at the inputs is an odd number
(for example, I3=1, I2=0, I1=1, I0=1, that is, binary value (1011)=decimal value(11)), the
output is low.
(ii) When the equivalent decimal value of the binary signals at the inputs is an even number
(for example, I3=1, I2=0, I1=0, I0=0, that is, binary value (1000)=decimal value(8)), the
output is low.
22. Implement a full subtractor circuit with 3:8 decoder and OR gates
23. Implement a 1 bit comparator circuit
24. A 16:1 multiplexer is connected to 1:16 demultiplexer. In order to transmit the signal at the input
terminal I13 of the multiplexer to the output terminal Y9 of the demultiplexer, what will be the values
of selector terminal signals at the multiplexer and the demultiplexer.
25. Explain the operation of a 4 bit ripple carry adder
26. 2-bit odd-cum-even parity generator-cum-checker circuit
27. Implement the following functions with 4:1 Multiplexer :-
(i) Y = f(A, B, C) = (A + B + C’)’.(A + B’ + C)
(ii) Y = f(A, B) = (A + B).(A’ + B)
28. Derive the logic circuit of full adder and show how it comprises of 2 Half Adders and one OR gate.
29. Design a logic circuit that takes a 2-bit number as input and gives its cube as output.
30. Implement the function F(A, B, C) = π(2,3,6,7) with 3:8 decoder.

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