INDUR

INSTITUTE OF ENGINEERING & TECHNOLOGY

SIDDIPET, TELANGANA state

LABORATORY MANUAL

DIGITAL ELECTRONICS LAB

2nd Year 2nd Sem. EEE
(As per R22 Academic Regulation)
Prepared and verified by
K KIRANMAI

DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING

PREFACE

Almost all Electronic circuits must include means for converting and processing of

electrical signals. This lab course is to gain the practical hands on experience by exposing the

students to applications and design, Adder / Subtractor of priority encoder, comparator, counter,
multiplexe sequence generator and the transform Characteristics of 74H, LS, HS series

Students are made familiar with Digital applications of Integrated circuits. Students are

made to design the application circuitry by utilizing the basic Integrated circuits. This would

enable them to choose the appropriate IC for required application

Course Objectives:
The main objective of this curriculum/course is to make the students well versed with
basic electronic components and circuits. The students can.
• To learn basic techniques for the design of digital circuits and fundamental concepts used in the
design of digital systems.
• To understand common forms of number representation in digital electronics circuits and to be
able to convert between different representations.
• To implement simple logical operations using combinational logic circuits.
• To design combinational logic circuits, sequential logic circuits.
•To impart to students the concept of sequential circuits, enabling them to analyze sequential
systems in terms of state machines.
•To implement synchronous state machines using Flip-flops.
Course Outcomes:
At the end of this course student will demonstrate the ability to
• Understand working of logic families and logic gates.
• Design and implement combinational and sequential logic circuits.
• Understand the process of analog and digital conversion and digital to analog conversion.
• Be able to use PLD’s to implement the given logical problem.

LAB CODE

• Students should report to the concerned labs as per the time table schedule.
• Students who turn up late to the labs will in no case be permitted to perform the
experiment scheduled for the day.
• After completion of the experiment, certification of the concerned staff in-charge
in the observation book is necessary.
• Staff member in-charge shall award marks based on continuous evaluation for each
experiment out of maximum 10 marks and should be entered in the notebook

• Students should bring a note book of about 100 pages and should enter the
readings/observations into the note book while performing the experiment.

• The record of observations along with the detailed experimental procedure of the
experiment performed in the immediate last session should be submitted and certified by
the staff member in-charge.

• Not more than three students in a group are permitted to perform the experiment on a
setup.

• The group-wise division made in the beginning should be adhered to, and no mix
up of student among different groups will be permitted later.

• The components required pertaining to the experiment should be collected from stores
in-charge after duly filling in the requisition form.

• When the experiment is completed, students should disconnect the setup made by
them, and should return all the components/instruments taken for the purpose.

• Any damage of the equipment or burn-out of components will be viewed seriously either
by putting penalty or by dismissing the total group of students from the lab for the
semester/year.

• Students should be present in the labs for the total scheduled duration.

• Students are required to prepare thoroughly to perform the experiment before coming
to Laboratory

INDEX
As per JNTUH For Laboratory Examination – Minimum of 12 experiments

Sl. No. Name of the Experiment Page No.

1 Realization of Boolean Expressions using Gates 14

2 Design and realization logic gates using universal gates 19

3 Generation of clock using NAND / NOR gates 32

 4 Design a 4 – bit Adder / Subtractor 36

Design and realization a 4 – bit gray to Binary and Binary to Gray

5. 42
Converter
Design and realization of a 4-bit pseudo random sequence
6 generator using logic gates. 48

Design and realization of an 8-bit parallel load and serial out shift
7 52
register using flipflops

8. Design and realization a Synchronous and Asynchronous counter 56

using flip-flops

9 Design and realization 8x1 using 2x1 mux 68

74
10. Design and realization 2-bit comparator

11. Verification of truth tables and excitation tables 78

12. Realization of logic gates using DTL, TTL, ECL, etc., 83

Study of - IC 74148, IC 7400, IC 7432, IC 7486,IC 7483, IC 7485, IC 7490, IC 7447, IC

7474, IC 74151, IC 4026, IC 74165, IC 74166, IC 7485 IC 7408 functioning, parameters
and specifications
1. IC 74148 PIN Diagram:

Description: Unlike a multiplexer that selects one individual data input line and then sends that
data to a single output line or switch, Digital Encoder more commonly called a Binary Encoder
takes ALL its data inputs one at a time and then converts them into a single encoded output. So
we can say that a binary encoder, is a multi-input combinational logic circuit that converts the
logic level “1” data at its inputs into an equivalent binary code at its output.

Features:

• For Encoding 8 Data Lines to 3-Line Binary

• Applications Include n-bit Encoding and Code Converters
 • Units Can be Cascaded for Larger Encoding Applications
• Standard TTL Voltages
• Superseded, Not Recommended for New Designs
Applications:
• Encoders are used to translate rotary or linear motion into a digital signal.
• Usually this is for the purpose of monitoring or controlling motion parameters
such as speed, rate, direction, distance or position.

IC 7400 PIN Diagram:

Description: IC 7400, NAND gate. 7400 IC is the most widely used TTL (Transistor-Transistor
Logic) device in the world. It contains four independent two-input NAND gates. Its popularity is
based on the fact that any logic gate function can be created using only NAND gates.

Feature

• The first part number in the series, the 7400, is a 14-pin IC

• IC7400 containing four two-input NAND gates.

• Each gate uses two input pins and one output pin, with the remaining two pins being
power (+5 V) and ground.
 Applications:

• IC 7400, NAND gate. 7400 IC is the most widely used TTL (Transistor-Transistor
Logic) device in the world.

• It contains four independent two-input NAND gates.

• Its popularity is based on the fact that any logic gate function can be created using only
NAND gates3. IC 7432 PIN Diagram:

Description: OR gates are basic logic gates, and are available in TTL and CMOS ICs logic
families. The standard 4000 series CMOS IC is the 4071, which includes four independent two-
input OR gates. The TTL device is the 7432.

Features:
• Four 2-Input Logic OR Gates in a 14-Pin DIP Package.
• Outputs Directly Interface to CMOS, NMOS and TTL.
• Large Operating Voltage Range.
• Wide Operating Conditions.
• Not Recommended for New Designs Use 74LS32 or 74HC32.
Applications:

• IC 7432: It is a quad two input OR gate.

• All four OR gates may be used independently. On any gate if either of the input is 'High'
then the Output is 'High'.
4. IC 7486 PIN Diagram:
Description: IC 7486: It is a quad two input Ex-OR gate. All four Exclusive-OR gates may be
used independently. On any gate when one input(Not Both) is 'High' then the Output is High.

Features:

• 7486 Quad EXCLUSIVE-OR Gate Datasheet.

• Four 2-Input Exclusive OR Gates in a 14 Pin DIP Package.

• Outputs Directly Interface to CMOS, NMOS and TTL.

• Large Operating Voltage Range. Wide Operating Conditions. Not Recommended for
New Designs Use 74LS86 or 74HC86.

Applications:

• An XOR gate (sometimes referred to by its extended name, Exclusive

OR gate) is a digital logic gate with two or more inputs and one output that performs
exclusive disjunction. ... If both of an XOR gate's inputs are false, or if both of its inputs
are true, then the output of the XOR gate is false.

5. IC 7483 PIN Diagram:

Description: IC 7483 is a 4 bit parallel adder which consists of four interconnected full adders
along with the look ahead carry circuit. The pin diagram of IC 7483 is shown above. It is a 16pin
IC.

Features:

• IC 7483 is a 4 bit parallel adder which consists of four interconnected full adders along
with the look ahead carry circuit.

• The pin diagram of IC 7483 is shown above.

• It is a 16pin IC. The inputs to the IC are A, B and C i n 0 while outputs are S and C o u t
3.

6. IC 7485 PIN Diagram:

Description: IIC 4585 (4-bit comparator in CMOS family) and IC 74AS885 (8-bit comparator).
Data comparison is needed in digital systems while performing arithmetic or logical operations.
This comparison determines whether one number is greater than, equal, or less than the other
number. A digital comparator is widely used in combinational system and is specially designed to
compare the relative magnitudes of binary numbers.

Features:

• 7485 4-bit Magnitude Comparator Datasheet. Compares 4-bit Binary or BCD Codes and
Outputs Greater, Less Than or Equal.

• Outputs Directly Interface to CMOS, NMOS and TTL.

• Large Operating Voltage Range. Wide Operating Conditions. Not Recommended for New
Designs Use 74LS85 or 74HC85.

Applications:

• a 4-bit magnitude comparator using 7485 IC. ... Like the digital
comparators are used in applications like process controllers and servo motor ...

7. IC 7490 PIN Diagram:

Description: The 74LS90 is a simple counter, i.e. it can count from 0 to 9 cyclically in its
natural mode. It counts the input pulses and the output is received as a 4-bit binary number
through pins QA, QB, QC and QD. The binary output is reset to 0000 at every tenth pulse and count
starts from 0 again. A pulse is also generated (probably at pin 9) as it resets its output to 0000.
The chip can count up to other maximum numbers and return to zero by changing the modes of
7490.

8. IC 7447 PIN Diagram:

 Description: The 74xx47 chip is used to drive 7 segment display. You must use the
74xx47 with a common anode 7-segment display (e.g. Kingbright part number SA03). The input
to the 74xx47 is a binary number DCBA where D is 8s, C is 4s, B is 2s and A is 1s. The inputs
DCBA often come from a binary counter.

9. IC 7474 PIN Diagram:

Description: IC 7474 is a dual D Flip Flop IC. It is a TTL logic device, hence operating
voltage is 5V. It has two D flip flops, with separate clocks for each Flip Flop, and preset, clear
and complementary outputs.

10. IC 74151 PIN Diagram:

Description: A typical IC 74151 is an 8-to-1 multiplexer with eight inputs and two
outputs. The two outputs are active low and active high outputs. It has three select lines A, B and
C and one active low enable input. The pinout of this IC is given below.

11. IC 4026 PIN Diagram

Description: It uses a 4026 combined counter and display driver IC which is designed to
drive 7 segment display. When you press the switch S1 counter starts from zero and it advances
one each time whenever pin 1 receives a positive pulse.

12. IC 74165 PIN Diagram

 Description: The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in
the direction of QA toward QH when clocked. Parallel-in access to each stage is made available
by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD)
input. These registers also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying system design.

13. IC 74166 PIN Diagram

Description: The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 54 / 74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.

14. IC 7473 PIN Diagram

Description: In electronics, a flip-flop or latch is a circuit that has two stable states and
can be used to store state information. The circuit can be made to change state by signals applied
to one or more control inputs and will have one or two outputs. It is the basic storage element in
sequential logic. Flip-flops and latches are a fundamental building block of digital electronics
systems used in computers, communications, and many other types of systems.

15. IC 7408 PIN

Diagram
 Description: 7408 IC is a QUAD 2-Input AND GATES and contains four independent gates
each of which performs the logic AND function.

EXPERIMENT NO: 1
REALIZATION OF BOOLEAN EXPRESSIONS USING GATES

AIM: To Realization of Boolean Expressions using Gates .

APPARATUS REQUIRED:

S.NO APPARATUS QUANTITY

REQUIRED

1 Digital IC trainer kit 1 No

2 IC 7408 1No

3 IC 7432 1No

4. IC 7404 1 No

5 Bread board 1No

6 Connecting wires As required

THEORY:
• Logic gates are electronic circuits which perform logical functions on one or more inputs
to produce one output. There are seven logic gates. When all the input combinations of a
logic gate are written in a series and their corresponding outputs written along them, then
this input/ output combination is called Truth Table. OR, AND and NOT are basic gates.
NAND, NOR are known as universal gates. Various gates and their working is explained
here.
• AND GATE: The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.
• OR GATE: The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when both
the inputs are low.
• NOT GATE: The NOT gate is called an inverter. The output is high when the input is
low. The output is low when the input is high
• NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when
both inputs are low and any one of the input is low .The output is low level when both
 inputs are high.
• NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
• X-OR GATE: The output is high when any one of the inputs is high. The output is low
when both the inputs are low and both the inputs are high.

Implement the Boolean function by using basic logic gates. F = (A + B) * (A + B’)

In the given function, we have a complement term, (A + B) and (A + B’). So to represent the
compliment input, we are using the NOT gates at the input side. And to represent the sum term,
we use OR gates. See the below given logic diagram for representation of the Boolean function.
CIRCUIT DIAGRAM:

PROCEDURE:

• Connect the trainer kit to power supply.

• Connect the inputs of any one logic gate to the logic switches and its output to the logic
indicator.
• Apply various input combinations and observe output for each one.
• Verify the truth table for each input/ output combination.
• Repeat the process for all other logic gates.
• Switch off the power supply.

OBSERVATION TABLE:

INP UTS OUTP UTS

A’ A+B (A+B)’ (A *B) (A*B )’ (A B)

A B

NOT OR NOR A ND NAND Ex-OR

0 0 1 0 1 0 1 0
 0 1 1 1 0 0 1 1

1 0 0 1 0 0 1 1

1 1 0 1 0 1 0 0

INFERENCE:

The mental activity that makes a connection between disparate thoughts, linking them in
a set of premises and conclusions. It is by inference that the norms and categories of such
connections, which are inherently present in the social or individual consciousness, are expressed
on the level of “inner speech.”

PRECAUTIONS:

• Make the connection s according to the IC pin diagram.

• The connections should be tight.

• The Vcc and ground should be applied carefully at the specified pin only.

RESULT:
Thus Realized of Boolean Expressions using Gates .

EXTENSION:

All optical multivalued logic processors are of paramount importance in optical

computing and signal processing. In this communication, the author proposes a new method of
developing all-optical quaternary logic gates which are the extension of binary logic gates

APPLICATIONS:

A logic gate implements a Boolean function and thus performs a logical operation on one
or several logic inputs in order to produce a single logic output. A logic gate often uses diodes or
transistors that act like electronic switches. ... The output of one gate can be wired to the inputs
of one or more other gates.
VIVA Questions with answer.
Q.1 Define gates?
Ans. Gates are the digital circuits, which perform a specific type of logical operation.

Q.2 Define IC?

Ans. IC means integrated circuit. It is the integration of no. of components on a

common substrate.

Q.3 Give example of Demorgan’s theorem.

Ans. (AB)’=A’+B’

(A+B)’=A’.B’

Q.4 (A+A) A =?

Ans. A.

Q5 Define Universal gates.

Ans. Universal gates are those gates by using which we can design any type of logical
expression.

Q6.Write the logical equation for AND gate.

Ans. Y=A.B

Q7 How many no. of input variables can a NOT Gate have?

Ans. One.

Q8.Under what conditions the output of a two input AND gate is one?

Ans. Both the inputs are one.

 EXPERIMENT NO: 2
DESIGN AND REALIZATION LOGIC GATES USING UNIVERSAL GATES

AIM: To implement basic logic gates using NAND and NOR gates. and verify its truth tables.

APPARATUS REQUIRED:

S.NO APPARATUS QUANTITY

REQUIRED

1 Digital IC trainer kit 1 No

2 IC 7400 1No

3 IC 7402 1No

4 Bread board 1No

5 Connecting wires As required

THEORY:

Logic gates are electronic circuits which perform logical functions on one or more inputs
to produce one output. There are seven logic gates. When all the input combinations of a logic
gate are written in a series and their corrresponding outputs written along them, then this input/
output combination is called Truth Table. Various gates and their working is explained here.

AND Gate:

AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0.
This gate can have minimum 2 inputs but output is always one. Its output is 0 when any input is
0.

IC 7408

OR Gate:

OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is
0. This gate can have minimum 2 inputs but output is always one. Its output is 0 when all input
are 0.

IC 7432

NOT Gate:

NOT gate produces the complement of its input. This gate is also called an INVERTER.
It always has one input and one output. Its output is 0 when input is 1 and output is 1 when input
is 0.

IC 7404

NAND Gate:

NAND gate is actually a series of AND gate with NOT gate. If we connect the output of
an AND gate to the input of a NOT gate, this combination will work as NOT-AND or NAND
gate. Its output is 1 when any or all inputs are 0, otherwise output is 1.

IC 7400

NOR Gate:

NOR gate is actually a series of OR gate with NOT gate. If we connect the output of an
OR gate to the input of a NOT gate, this combination will work as NOT-OR or NOR gate. Its
output is 0 when any or all inputs are 1, otherwise output is 1.

IC 7402

Exclusive OR (X-OR) Gate:

X-OR gate produces an output as 1, when number of 1’s at its inputs is odd, otherwise
output is 0. It has two inputs and one output.

IC 7486

Exclusive NOR (X-NOR) Gate:

X-NOR gate produces an output as 1, when number of 1’s at its inputs is not odd,
otherwise output is 0. It has two inputs and one output.

I. Implementation of logic gates using NAND gates:

i. NAND gates as NOT gate:

A NOT produces complement of the input. It can have only one input, tie the inputs of a
NAND gate together. Now it will work as a NOT gate. Its output is
Y = (A.A)’ => Y = (A)’

ii. NAND gates as AND gate:

A NAND produces complement of AND gate. So, if the output of a NAND gate is
inverted, overall output will be that of an AND gate.

Y = ((A.B)’)’ =>Y = (A.B)

iii. NAND gates as OR gate:

From DeMorgan’s theorems: (A.B)’ = A’ + B’

(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output. From DeMorgan’s
theorems: (A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.

iv. NAND gates as X-OR gate:

The output of a to input X-OR gate is shown by: Y = A’B + AB’. This can be achieved
with the logic diagram shown in the left side.

Gate No. Inputs Output

1 A, B (AB)’
2 A, (AB)’ (A (AB)’)’
3 (AB)’, B (B (AB)’)’
4 (A (AB)’)’, (B (AB)’)’ A’B + AB’
Now the ouput from gate no. 4 is the overall output of the configuration.
Y = ((A (AB)’)’ (B (AB)’)’)’
= (A(AB)’)’’ + (B(AB)’)’’
= (A(AB)’) + (B(AB)’)
= (A(A’ + B)’) + (B(A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= ( 0 + AB’ + BA’ + 0 )
= AB’ + BA’
=> Y = AB’ + A’B

v. NAND gates as X-NOR gate:

X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-OR
gate to a NOT gate, overall ouput is that of an X-NOR gate.
Y = AB+ A’B’

Vi. NAND gates as NOR gate:

 A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate to a
NOT gate, overall output is that of a NOR gate.
Y = (A + B)’

I. Implementation of logic gates using NOR gates:

i. NOR gates as NOT gate:

A NOT produces complement of the input. It can have only one input, tie the inputs of a
NOR gate together. Now it will work as a NOT gate. Its output is
Y = (A+A)’
Y = (A)’

ii. NOR gates as OR gate:

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted,
overall output will be that of an OR gate.
Y = ((A+B)’)’
Y = (A+B)

iii .NOR gates as AND gate:

From DeMorgan’s theorems: (A+B)’ = A’B’

(A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.

iv. NOR gates as X-NOR gate:

The output of a two input X-NOR gate is shown by: Y = AB + A’B’. This can be achieved
with the logic diagram shown in the left side.

Gate No. Inputs Output

1 A, B (A + B)’
2 A, (A + B)’ (A + (A+B)’)’
3 (A + B)’, B (B + (A+B)’)’
4 (A + (A + B)’)’, (B + (A+B)’)’ AB + A’B’

Now the ouput from gate no. 4is the overall output of the configuration.
Y = ((A + (A+B)’)’ (B +( A+B)’)’)’
= (A+(A+B)’)’’.(B+(A+B)’)’’
= (A+(A+B)’).(B+(A+B)’)
= (A+A’B’).(B+A’B’)
= (A + A’).(A + B’).(B+A’)(B+B’)
= 1.(A+B’).(B+A’).1
= (A+B’).(B+A’)
= A.(B + A’) +B’.(B+A’)
= AB + AA’ +B’B+B’A’
= AB + 0 + 0 + B’A’
= AB + B’A’
Y = AB + A’B’

v. NOR gates as X-OR gate

X-OR gate is actually X-NOR gate followed by NOT gate. So give the output of X-NOR
gate to a NOT gate, overall ouput is that of an X-OR gate.
Y = A’B+ AB’

Vi. NOR gates as NAND gate:

A NAND gate is an AND gate followed by NOT gate. So connect the output of AND gate
to a NOT gate, overall output is that of a NAND gate.
Y = (AB)’
 PROCEDURE:

• Connect the trainer kit to power supply.

• Connect the inputs of any one logic gate to the logic switches and its output to the logic
indicator.
• Apply various input combinations and observe output for each one.
• Verify the truth table for each input/ output combination.
• Repeat the process for all other logic gates.
• Switch off the power supply.

OBSERVATION TABLE:

INP UTS OUTP UTS

A’ A+B (A+B)’ (A *B) (A*B )’ (A B)

A B

NOT OR NOR A ND NAND Ex-OR

0 0 1 0 1 0 1 0

0 1 1 1 0 0 1 1

1 0 0 1 0 0 1 1

1 1 0 1 0 1 0 0

INFERENCE:

The mental activity that makes a connection between disparate thoughts, linking them in
a set of premises and conclusions. It is by inference that the norms and categories of such
connections, which are inherently present in the social or individual consciousness, are expressed
on the level of “inner speech.”

PRECAUTIONS:

• Make the connection s according to the IC pin diagram.

• The connections should be tight.

• The Vcc and ground should be applied carefully at the specified pin only.
RESULT:

Thus implemented the basic logic gates using NAND and NOR gates. and verifyed its
truth tables.

EXTENSION:

All optical multivalued logic processors are of paramount importance in optical

computing and signal processing. In this communication, the author proposes a new method of
developing all-optical quaternary logic gates which are the extension of binary logic gates

APPLICATIONS:

A logic gate implements a Boolean function and thus performs a logical operation on one
or several logic inputs in order to produce a single logic output. A logic gate often uses diodes or
transistors that act like electronic switches. ... The output of one gate can be wired to the inputs
of one or more other gates.

VIVA Questions with answer.

Q.1 Define gates?

Ans. Gates are the digital circuits, which perform a specific type of logical operation.

Q.2 Define IC?

Ans. IC means integrated circuit. It is the integration of no. of components on a

common substrate.

Q.3 Give example of Demorgan’s theorem.

Ans. (AB)’=A’+B’

(A+B)’=A’.B’
Q.4 (A+A) A =?

Ans. A.

Q5 Define Universal gates.

Ans. Universal gates are those gates by using which we can design any type of logical
expression.

Q6.Write the logical equation for AND gate.

Ans. Y=A.B

Q7 How many no. of input variables can a NOT Gate have?

Ans. One.

Q8.Under what conditions the output of a two input AND gate is one?

Ans. Both the inputs are one.

Q9.1+0 =?

Ans.
 EXPERIMENT NO: 3
GENERATION OF CLOCK USING NAND / NOR GATES

AIM: - To Study of 450 kHz clock generator using NAND/NOR gates.

EQUIPMENT REQUIRED:-
• 450khz clock generator Trainer kit
• CRO
• CRO Probes
• 5V/2A Adapter
• 2mm Patch Cards.
THEORY:-

This is a very simple square wave generator circuit built with IC 74LS00 that can
generate square signals with frequencies between 20 Hz and 1 MHz. Its stability is good enough
for most applications. The output freq. is dimensioned through the RC components and time
delay of the 3 inverter gates. The time delay of a logic gate is the elapsed time between a change
of input state and the resulting change of the outputstate.
To prevent the temperature and voltage supply from affecting the frequency of the square
wave generator, the oscillator freq. fo must be smaller than 1/2tpn where:
tp =average delay time of each gate
n = the number of gates
The above described oscillator has a tp of 10ns and n-3. The freq. is therefore:
fo << 1/2tpn = 1/2*10ns*3 = 16.6MHzThe voltage at the gate inputs varies from about -6V to -
4V. The oscillation freq. can be made variable by using a 2.2KΩ potentiometer for R.
CIRCUIT DIAGRAM:-
Layout diagram:-

PROCEDURE:-
1. Connections are made as per the circuit diagram.
2. Switch ON the trainer kit.
3. Apply the power supply of 5V DC
4. Vary the 47k potentiometer to get the exact square wave.
5. Calculate the time period of the wave form.
6. Calculate the frequency by using the formula f= 1/t
EXPECTED WAVE FORM:

CALCULATIONS:-
F=1/T
T=time period
F=frequency
PRECAUTIONS:
1. Note down the number of the IC. Note the important specifications of
the IC from the data sheet.
2. Do not exceed the maximum values specified in data sheet.
3. Do not install or remove IC from a circuit with power ON.
4. Identify the Pin numbers of the IC.
5. Adjust the oscilloscope for proper viewing.
TROUBLE SHOOTING:

1. Check the IC
 2. Check Battery Connections
3. Check whether input signal can be viewed on the CRO.
4. Check the CRO probe
5. Check the Patch cards
APPLICATIONS:

1. Clock generators are used in computers to manage memory cards, peripheral devices,
CPUs, ports, etc.

2. In fact, computer experts often reset clock generators in order to control these devices’
speed and performance.
3. Clock generators are also used in telecommunication systems, digital switching systems,
and many mechanical devices.

RESULT:-

Verified the output of a 450 khz clock generator using NAND/NOR gates.

QUESTIONS:

What is the use of clock in digital circuits?

What is the use of clock pulse?
What is the significance of the clock for the microprocessor?
What is the use of clock in flip flop?
 EXPERIMENT NO: 4
DESIGN A 4 – BIT ADDER / SUBTRACTOR
AIM :To Design a 4 – bit Adder / Subtractor IC’s
EQUIPMENT REQUIRED:
• 4 Bit adder/subtractor using adder /subs tractor Trainer kit
• DC Power supply
• 2mm Patch Cards.
• 5V/2A Adapter

THEORY:-
4- BIT ADDER

• IC 7483 is a 4 bit parallel adder which consists of four interconnected full adders along
with the look ahead carry circuit. The pin diagram of IC 7483 is shown above. It is a
16pin IC. The inputs to the IC are A, B and Cin0 while outputs are S and Cout3.
• A15A2A1A0 is a 4 bit input word 'A' and B15B2B1B0 is the second 4 bit input word 'B'.
Cin0 is the input carry. The IC adds the 4 four bit words along with input carry to produce
a 4 bit sum and a one bit carry-out. Cout3 represents the output carry. S3,S2,S1,S0
represents sum output with S3 as the MSB.
 • In odrder to design an 8 bit adder, we require two IC 7483s cascaded as shown in the
figure above.
• Adder-1 is the LSB adder and it adds the four LSB bits of the two 8-bit input words ie
A15−A0 and 153−B0. The carry input of first adder is supposed to be 0. Hence the carry
in pin of LSB IC is connected to the ground. So the first IC adds the LSB bits of A and B,
and produces S3–S0 that is, LSB of sum, along with a carry out Cout3.
• This Cout3 of adder-1 is connected to Cin0 input of Adder-2. The second adder adds this
carry and the four MSB bits of numbers A15−A0 and B15−B0 to produce MSB sum S7–
S4 along with final carry out bit Cout7.
• Thus adder-1 and adder-2 when cascaded as shown in the figure can add two 8-bit words.
Cout7 of adder-2 acts as the final output carry and the sum output is from S7 through S0.
4- BIT SUBSTRACTOR

As with the binary adder, we can also have n number of 1-bit full binary subtractor
connected or “cascaded” together to subtract two parallel n-bit numbers from each other. For
example two 4-bit binary numbers. We said before that the only difference between a full adder
and a full subtractor was the inversion of one of the inputs.
So by using an n-bit adder and n number of inverters (NOT Gates), the process of
subtraction becomes an addition as we can use two’s complement notation on all the bits in the
subtrahend and setting the carry input of the least significant bit to a logic “1” (HIGH).
Then we can use a 4-bit full-adder ICs such as the 74LS283 and CD4008 to perform
subtraction simply by using two’s complement on the subtrahend, B inputs as X – Y is the same
as saying, X + (-Y) which equals X plus the two’s complement of Y.
If we wanted to use the 4-bit adder for addition once again, all we would need to do is set
the carry-in (CIN) input LOW at logic “0”. Because we can use the 4-bit adder IC such as the
74LS83 or 74LS283 as a full-adder or a full-subtractor they are available as a single
adder/subtractor circuit with a single control input for selecting between the two operations
CIRCUIT DIAGRAM
4 BIT ADDER

4 BIT SUBSTRACTOR
Layout diagram:-
PROCEDURE:
1. Connect the circuit. as shown in the fig.
2. Apply different combination of the binary inputs at the I/P terminals.
3. Note down the O/P for Half adder.
4. Repeat the same procedure for Full adder also.
5. The result should be in accordance with truth table.
6. Verify the outputs for different input values.
OBSERUATION:-
4 bit adder:

INPUT X x3 x2 x1 x0

Binary values 0 1 1 1

INPUT Y y3 y2 y1 y0

Binary values 0 0 0 1

OUTPUT s3 s2 s1 s0
SUM

Binary output 1 0 0 0

4 bit subtractor:

INPUT X x3 x2 x1 x0

Binary values 0 1 1 1

INPUT Y y3 y2 y1 y0

Binary values 0 0 0 1

OUTPUT s3 s2 s1 s0
Difference

Binary output 0 1 1 0
PRECAUTIONS:
1. Note down the number of the IC. Note the important specifications of
the IC from the data sheet
2. Do not exceed the maximum values specified in data sheet
3. Do not install or remove IC from a circuit with power ON.
4. Identify the Pin numbers of the IC
TROUBLE SHOOTING:
• Check the IC before connecting in the circuit.
• Check Battery Connections
• Check the input and output LEDs.
• Check the Patch cards.

APPLICATIONS:
1. An adder is a digital circuit that performs addition
2. Adders & Subtractors are wildly used in in computer's ALU to compute addition as well as
CPU and GPU for graphics applications to reduce the circuit complexity.

RESULT: - Verified the output of a 16 bit adder/substractor using 4 bit adder /subs
tractor

QUESTIONS:

1. In which operation carry is obtained

2. If A and B are the inputs of a half adder, the sum is given by
3. The difference between half adder and full adder is
4. Major limitation of a Half-adders is
5. If A and B are the inputs of a half adder, the carry is given by
6. What are the applications of adder and Subtractor

EXPERIMENT NO: 5
DESIGN AND REALIZATION A 4 – BIT GRAY TO BINARY AND BINARY TO GRAY
CONVERTER

AIM:- To Design a 4 Bit Gray to Binary and Binary to Gray code conversion.
EQUIPMENT REQUIRED:-
• 4 Bit Gray to Binary and Binary to Gray code conversion Trainer kit
• DC Power supply
• 2mm Patch Cards
• 5V/2A Adapter

THEORY:-
binary to gray code converter:-

The logical circuit which converts binary code to equivalent gray code is known as
binary to gray code converter. The gray code is a non weighted code. The successive gray code
differs in one bit position only that means it is a unit distance code. It is also referred as cyclic
code. It is not suitable for arithmetic operations. It is the most popular of the unit distance codes.
It is also a reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code about
an axis after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the axis.
Reflection of Gray codes is shown below.
Gray to Binary Code Converter:-
This conversion method also follows the EX-OR gate operation between grey & binary
bits. The below steps & solved example may useful to know how to perform grey code to binary
conversion.

In gray to binary code converter, input is multiplies gray code and output is its
equivalent.binary code.
Let us consider a 4 bit gray to binary code converter. To design a 4 bit gray to binary code
converter, we first have to draw a conversion table.
CIRCUIT DIAGRAM :

Layout diagram:-
PROCEDURE:-
Binary to Gray Converter:-
1. To convert binary to grey code, bring down the most significant digit of the given binary
number, because, the first digit or most significant digit of the grey code number is same as the
binary number.
2. To obtain the successive grey coded bits to produce the equivalent grey coded number for the
given binary, add the first bit or the most significant digit of binary to the second one and write
down the result next to the first bit of grey code, add the second binary bit to third one and write
down the result next to the second bit of grey code, follow this operation until the last binary bit
and write down the results based on EX-OR logic to produce the equivalent grey coded binary.

Gray to Binary Converter

1. To convert grey code to binary, bring down the most significant digit of the given grey code
number, because, the first digit or the most significant digit of the grey code number is same as
the binary number.
2. To obtain the successive second binary bit, perform the EX-OR operation between
the first bit or most significant digit of binary to the second bit of the given grey code.
3. To obtain the successive third binary bit, perform the EX-OR operation between
the second bit or most significant digit of binary to the third MSD (most significant
digit) of grey code and so on for the next successive binary bits conversion to find the equivalent.
OBSERVATION TABLE:

PRECAUTIONS:
1. Note down the number of the IC. Note the important specifications of
the IC from the data sheet.
2. Do not exceed the maximum values specified in data sheet.
3. Do not install or remove IC from a circuit with power ON.
4. Identify the Pin numbers of the IC.
TROUBLE SHOOTING:
1. Check the IC before connecting in the circuit.
2. Check Battery Connections
3. Check the input and output LEDs.
4. Check the Patch cards
APPLICATIONS:
1. Today, Gray codes are widely used to facilitate error correction in digital communications
such
as digital terrestrial television and some cable TV systems.
2. Gray codes are used in position encoders
3. Due to the Hamming distance properties of Gray codes, they are sometimes used in genetic
algorithms
4. In modern digital communications, Gray codes play an important role in error correction
RESULT:-
Verified the Truth tables of Binary to Gray and Gray to Binary converters.

QUESTIONS:

1. What is gray to binary code conversion?

2. What are weighted and non weighted codes?
3. How do you convert binary to BCD?
4. What are the applications of Gray to Binary code converter?
5. What are the applications of Binary to Gray code converter?

EXPERIMENT NO: 6
 DESIGN AND REALIZATION OF A 4-BIT PSEUDO RANDOM SEQUENCE
GENERATOR USING LOGIC GATES.

AIM:- To Design a 4 bit pseudo random sequence generator using 4 – bit ring counter.
EQUIPMENT REQUIRED:
• Pseudo-random Sequence Trainer kit
• DC Power supply
• 2mm Patch Cards.
• 5V/2A Adapter

THEORY:-
Pseudo-random Sequence Generator
A pseudo-random binary sequence generator as shown in the Fig. This binary sequence
generator will display a random output (repeats every 2 n–1 bits, where n is the number of flip-
flops used in the shift register). The IC 7486 provides the exclusive-OR needed in the circuit. To
start the sequence generator, set the initial state of the shift register to 0001 by setting the switch
SW1 to logic 1. Then change SW1 to logic 0 as this will release the control input. Now apply the
clock and record the output in a table. Does the output show randomness? Does the output repeat
after 15 pulses?
CIRCUIT DIAGRAM :

Layout diagram:-

PROCEDURE:-
1. Connections are made as per the circuit diagram.
2. Switch ON the trainer kit.
3. Apply the power supply of 5V DC
4. First reset all flip-flops of Q3 Q2 Q1 Q0 = 0 0 0 0.
5. Shift right operation mode .
6. Connect EX-OR means o/p of EX-OR is connected to
DSR.

OBSERVATION TABLE:-

Clock
Pulse Ex-OR PRBS
Number Shift Register gate Sequence

Q0 Q1 Q2 Q3 Q2 Q3 Q0
0 0 0 0 1 0 1=1 0
1 1 0 0 0 0 0=0 0
2 0 1 0 0 0 0=0 1
3 0 0 1 0 1 0=1 1
4 1 0 0 1 0 1=1 0
5 1 1 0 0 0 0=0 1
6 0 1 1 0 1 0=1 0
7 1 0 1 1 1 1=0 1
8 0 1 0 1 0 1=1 1
9 1 0 1 0 1 0=1 1
10 1 1 0 1 0 1=1 1
11 1 1 1 0 1 0=1 0
12 1 1 1 1 1 1=0 0
13 0 1 1 1 1 1=0 0
14 0 0 1 1 1 1=0 1
15 0 0 0 1 0 1=1 0
16 1 0 0 0 0 0=0 0
17 1 1 0 1 1 1=0 1

PRECAUTIONS:
1. Note down the number of the IC. Note the important specifications of
 the IC from the data sheet
2. Do not exceed the maximum values specified in data sheet
3. Do not install or remove IC from a circuit with power ON.
4. Identify the Pin numbers of the IC.

TROUBLE SHOOTING:
1. Check the IC before connecting in the circuit.
2. Check Battery Connections
3. Check the input and output LEDs.
4. Check the Patch cards.

APPLICATIONS

1. Pseudorandom generators have numerous applications in cryptography.

2. Pseudorandom generators provide an efficient analog of one-time pads.

3. Key length can be significantly reduced using a pseudorandom generator

4. Common constructions of stream ciphers are based on pseudorandom generators.

5. Pseudorandom generators may also be used to construct same key. symmetric key
cryptosystems, where a large number of messages can be safely encrypted under the

RESULT:-

Verified the output of a 4 bit pseudo random sequence generator using 4 – bit ring
counter.

QUESTIONS:
• What is a Pseudo-random Sequence generator?
• How does pseudo random number generator work?
• How does pseudo random work?
• What is a pseudo random code what is it used for?
 EXPERIMENT NO: 7
DESIGN AND REALIZATION OF AN 8-BIT PARALLEL LOAD AND SERIAL OUT
SHIFT REGISTER USING FLIPFLOPS.

AIM:- Design an 8 bit parallel load and serial out shift register using two 4 bit shift register.
EQUIPMENT REQUIRED:

• 8 bit parallel load and serial out shift register using flip flop Trainer kit
• DC Power supply
• 2mm Patch Cards.
• 5V/2A Adapter
THEORY:-
Parallel-in to Serial-out (PISO) Shift Register
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to
parallel-out one above. The data is loaded into the register in a parallel format in which all the
data bits enter their inputs simultaneously, to the parallel input pins P0 to P7 of the register. The
data is then read out sequentially in the normal shift-right mode from the register
at Q representing the data present at P0 to P7.
This data is outputted one bit at a time on each clock cycle in a serial format. It is
important to note that with this type of data register a clock pulse is not required to parallel load
the register as it is already present, but four clock pulses are required to unload the data.
As this type of shift register converts parallel data, such as an 8-bit data word into serial
format, it can be used to multiplex many different input lines into a single serial DATA stream
which can be sent directly to a computer or transmitted over a
communications line. Commonly available IC’s include the 74HC166 8-bit Parallel-in/Serial-out
Shift Registers.
CIRCUIT DIAGRAM:-
.

Layout diagram:-

PROCEDURE:-
1. When the SHIFT/LOAD =0,Then Load Mode.
2. When the SHIFT/LOAD =1,Then shift Mod.
3. D0, TO D7 are the parallel inputs, where D0 is the most significant bit and D7 is
the least significant bit.

4. To write data in, the mode control line is taken to LOW and the data is clocked in. The data
can be shifted when the mode control line is HIGH as SHIFT is active high.
5. The register performs right shift operation on the application of a clock pulse.

OBSERVATION TABLE:-

CLK CLK SHIFT/LOAD INPUTS OUTPUTS

INHIBIT

I0 I1 I2 I3 I4 I5 I6 I7

1 0 0 1 1 1 1 0 0 0 0 0

1 0 1 1 1 1 1 0 0 0 0

1 0 1 1 1 1 1 0 0 0

1 0 1 1 1 1 1 0 0
 1 0 1 1 1 1 1 1

1 0 1 1 1 1 1

1 0 1 1 1 1

1 0 1 1 1

PRECAUTIONS:
1. Note down the number of the IC. Note the important specifications of the IC from the
data sheet
2. Do not exceed the maximum values specified in data sheet
3. Do not install or remove IC from a circuit with power ON.
4. Identify the Pin numbers of the IC
TROUBLE SHOOTING:
1. Check the IC before connecting in the circuit.
2. Check Battery Connections
3. Check the input and output LEDs.
4. Check the Patch cards.
APPLICATIONS:

Registers are used in digital electronic devices like computers as

1. Temporary data storage
2. Data transfer
3. Data manipulation
4. As a counters and used in computers as memory elements.

RESULT:-
Verified the output of a 8- bit parallel load and serial out shift register
using two 4 bit shift register.
QUESTIONS:

1. What are the applications of shift registers?

2. Why do we need shift registers?
3. What is a parallel load register?
4. What are the types of shift registers?
5. Why are shift registers considered basic memory devices?

EXPERIMENT NO: 8
DESIGN AND REALIZATION A SYNCHRONOUS AND ASYNCHRONOUS COUNTER
USING FLIP-FLOPS
AIM:- To Realiaze a synchronous counter using flipflops..

EQUIPMENT REQUIRED:
 • 4 digit hex counter using synchronous counter Trainer kit
• DC Power supply
• 2mm Patch Cards.
• 5V/2A Adapter

THEORY:-

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly
to each of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied
together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected
HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous
counter follows a predetermined sequence of states in response to the common clock signal,
advancing one state for each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output Q A of flip-flop
FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates
which are also supplied with signals from the input and output of the previous stage. These
additional AND gates generate the required logic for the JK inputs of the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop
outputs (Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous
circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly
the same time.

Then as there is no inherent propagation delay in synchronous counters, because all the
counter stages are triggered in parallel at the same time, the maximum operating frequency of
this type of frequency counter is much higher than that for a similar asynchronous counter
circuit.

CIRCUIT DIAGRAM:-
PROCEDURE:-
a) Make the connections as per the logic diagram.
b) Connect +5v and ground accord ing to pin configuration.
c) Apply diff combinations of inputs to the i/p terminals.
d) Note o/p for summation.
e) Verify the truth table.
QBSERVATION TABLE:-

Clock pulse Clear (clr) Preset(pr) OUTPUTS

1 1 0 0000
1 1 1 0001
1 1 1 0002
1 1 1 0003
. . . .
. . . .
1 1 1 0009
1 1 1 000
1 1 1 000
1 1 1 000
1 1 1 000
1 1 1 000
1 1 1
1 1 1 0010
1 1 1 0011
. . . .
. . . .
1 1 1 0019
1 1 1 001
1 1 1 001
1 . . .
1 . . .
1 1 1
1 1 1 0020
. . . .
. . . .
1 1 1 0099
1 1 1 0100
1 1 1 0101
. . . .
. . . .
1 1 1 0199
1 1 1 019
1 1 1 019
. . .
. . .
1 1 1
1 1 1 0200
1 1 1 0201
. . . .
. . . .
1 1 1 0299
1 1 1 029
1 1 1 029
. . . .
. . . .
1 1 1 0300
. . . .
. . . .
1 1 1 039
1 1 1 0400
. . . .
. . . .
1 1 1 0999
 1 1 1 099
1 1 1 1000
1 1 1 1001
. . . .
. . . .
1 1 1 1999
1 1 1 199
1 1 1 199
. . . .
. . . .
1 1 1 1

PRECAUTIONS:

1. Note down the number of the IC. Note the important specifications of the IC from the data
sheet
2. Do not exceed the maximum values specified in data sheet
3. Do not install or remove IC from a circuit with power ON.
4. Identify the Pin numbers of the IC

TROUBLE SHOOTING:

1. Check the IC before connecting in the circuit.

2. Check Battery Connections
3. Check the input and output LEDs.
4. Check the Patch cards.

APPLICATIONS:
1. The applications of the counters mainly involve in digital clocks and in multiplexing.
2. For Generating staircase voltage
3. These counters find their applications in embedded systems,stop watch,real-time clock and
4. After receiving the clock signal they count the desired sequence in order.
RESULT:-
The 16-bit synchronous counter has studied and verified.
QUESTIONS:
1. What is the application of counter?
2. What is 4 bit counter?
3. What are decade counters?
4. How does a counter work?
5. What is the main HYPERLINK "https://www.google.com/url?
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main-application-of-counters&usg=AOvVaw0EU7rrMXip1sWFFiVGEjHm"application of
counters HYPERLINK "https://www.google.com/url?
sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwiox5TvqdvfAhWDbn0KHeQdBh
AQrAIoADAAegQICxAH&url=https%3A%2F%2Ffanyv88.com%3A443%2Fhttps%2Fwww.quora.com%2FWhat-is-the-main-
application-of-counters&usg=AOvVaw0EU7rrMXip1sWFFiVGEjHm"?
6. What are the main HYPERLINK "https://www.quora.com/What-are-the-main-
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7. What are the application of synchronous counters?
 EXPERIMENT NO: 9
DESIGN AND REALIZATION 8X1 USING 2X1 MUX

Aim:
To Design and realization 8x1 using 2x1 mux

Apparatus:
Trainer kit, Patch cords

Theory:
 This is an 8X1 MUX with inputs d0,d1,d2,d3,d4,d5,d6,d7 , Y as output and
S2, S1, S0 as selection lines. The output will depend upon the combination of S2,S1 &
S0 as shown in the truth table.

Circuit Diagram:

Truth table:

Procedure:
• Connect the circuit as per circuit diagram.
• Connect D0 to D7 to the input switches.
• Connect selection line inputs to the input switches.
• Connect the output terminal Y to the output indicator (LED).
• Verify the truth table given above.
Result:
 Experiment No: 10
Design and realization 4-bit comparator

Aim: To verify the truth table of 4-bitComparator.

Apparatus: MTS-COMPARATOR

PATCH CORDS

Theory:

A magnitude digital Comparator is a combinational circuit that compares two digital or

binary numbers in order to find out whether one binary number is equal, less than or
greater than the other binary number. We logically design a circuit for which we will
have two inputs one for A and other for B and have three output terminals, one for A > B
condition, one for A = B condition and one for A < B condition.
A comparator used to compare two bits is called a single bit comparator. It consists of
two inputs each for two single bit numbers and three outputs to generate less than, equal
to and greater than between two binary numbers.
A comparator used to compare two binary numbers each of two bits is called a 2-bit
Magnitude comparator. It consists of four inputs and three outputs to generate less than,
equal to and greater than between two binary numbers.
A comparator used to compare two binary numbers each of four bits is called a 4-bit
magnitude comparator. It consists of eight inputs each for two four bit numbers and
three outputs to generate less than, equal to and greater than between two binary
numbers.
Pin diagram:

Truth Table. :

COMPARING CASCA OUTPUTS

DING
INPUTS INPUTS
A3,B3 A2,B2 A1,B1 A0,B0 A> A< A= A> A< A=
B B B B B B
A3>B3 X X X X X X H L L
 A3< X X X X X X L H L
B3
A3= A2> X X X X X H L L
B3 B2
A3= A2< X X X X X L H L
B3 B2
A3= A2= A1> X X X X H L L
B3 B2 B1
A3= A2= A1< X X X X L H L
B3 B2 B1
A3= A2= A1= A0> X X X H L L
B3 B2 B1 B0
A3= A2= A1= A0< X X X L H L
B3 B2 B1 B0
A3= A2= A1= A0= H L L H L L
B3 B2 B1 B0
A3= A2= A1= A0= L H L L H L
B3 B2 B1 B0
A3= A2= A1= A0= L L H L L H
B3 B2 B1 B0
A3= A2= A1= A0= X X H L L H
B3 B2 B1 B0
A3= A2= A1= A0= H H L L L L
B3 B2 B1 B0
A3= A2= A1= A0= L L L H H L
B3 B2 B1 B0

Procedure:
• Connect the trainer kit to ac power supply.
• Connect Inputs ( A0,A1,A2,A3,B0,B1,B2,B3) to Input Switches
• Connect Cascade Inputs (A<B,A>B,A=B) to Input Switches
• Connect Outputs (A<B,A>B,A=B) to Output Switches.
 • Connect the inputs of first stage to logic sources and output of the last gate
to logic indicator.
• Apply various input combinations and observe output for each one.
• Verify the truth table for each input/ output combination.
• Repeat the process for all logic functions.
• Switch off the ac power supply.
Result:
 Experiment No: 11
Verification of truth tables and excitation tables

Experiment No: 12
Realization of logic gates using DTL, TTL,
ECL, etc.,

Aim:

Realization of logic gates using DTL, TTL, ECL, etc.,

Apparatus:
Logic trainer kit, Connecting wires

Theory:

Diode- Transistor Logic, or DTL, refers to the technology for designing and fabricating
digital circuits wherein logic gates employ diodes in the input stage and bipolar junction
transistors at the output stage. The output BJT switches between its cut-off and saturation
regions to create logic 1 and 0, respectively.

Circuit Diagram:
Procedure:
• Connect the trainer kit to ac power supply.
• Connect the NOR gates for any of the logic functions to be realised.
• Connect the inputs of first stage to logic sources and output of the last gate
to logic indicator.
• Apply varous input combinations and observe output for each one.
• Verify the tructh table for each input/ output combination.
• Repeat the process for all logic functions.
• Switch off the ac power supply.
Result: