IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO.

12, DECEMBER 2018 5289

Optimization and Scaling of Ge-Pocket TFET

Weicong Li and Jason C. S. Woo, Fellow, IEEE

Abstract — TFETs are promising candidates for future

low-power logic applications because of their potential for
outperforming conventional MOSFETs under reduced sup-
ply voltage (V DD ). Among all material systems currently
being explored, group IV semiconductor SiGe holds the
most potential due to its very large scale integration (VLSI)
compatibility, mature synthesis techniques, and tunable
bandgap, making it more likely to be adopted for future VLSI
technologies. It has been shown experimentally that the
on-state current (I on ) of SiGe TFETs improves significantly
with the increasing Ge content. However, increasing the
Ge content leads to excessive leakage in the off-state and Fig. 1. (a) Schematic cross-sectional of Ge-pocket TFET. (b) SiGe
poses a challenge to the pseudomorphic growth of SiGe. composition along the cutline (1 nm below the gate oxide/channel
In this paper, the concept of Ge-pocket TFET with a counter- interface) for Ge-pocket TFET, Ge-source TFET, and Si0.5 Ge0.5 -source
doped pocket is proposed. By confining Ge to the pocket TFET.
region, the proposed structure circumvents those problems.
Both the steep subthreshold swing and high I on can be
achieved. The proposed TFET also demonstrates excellent compatibility, mature synthesis techniques, and tunable
scalability in terms of physical gate length (Lgate ) and V DD , bandgap. The FinFET/GAA compatibility is essential for a
which makes it a promising replacement of conventional material to be adopted in mainstream VLSI platforms. In addi-
MOSFETs for low-power logic applications. tion, the maturity of synthesis techniques helps to reduce the
Index Terms — Heterojunction, silicon germanium, TFET. defect formation during material growth and suppress defect-
assisted tunneling. The tunable bandgap enables the realization
I. I NTRODUCTION
of the efficient tunneling injection and the suppression of
TFETs have been studied extensively as potential replace-
ambipolar conduction. SiGe TFETs have been demonstrated,
ments for conventional MOSFETs for future low-power logic
and their performance improvement relies on the increasing
very large scale integration (VLSI) applications because
Ge content [7]–[10]. However, increasing the Ge content leads
of their potential to achieve sub-60-mV/dec subthreshold
to high leakage current in SiGe homojunction TFETs [8], [9]
swing (SS). So far, reducing VDD without sacrificing Ion
and degraded SS in SiGe heterojunction TFETs [10]. During
has been the key challenge to TFETs. Because traditional Si
SiGe heteroepitaxy, defects can form in the case of growth
TFETs suffer from low Ion , SiGe and III–V TFETs have been
beyond critical thickness [11], resulting in defect-assisted
suggested as alternatives due to their reduced tunnel barrier
tunneling, which is responsible for the SS degradation in SiGe
heights. Although high Ion was obtained from III–V TFETs,
heterojunction TFETs [10]. In this paper, the Ge-pocket TFET
the SS degradation at low current level (<nA/µm) [1]–[4] ren-
with a counter-doped pocket is presented. By confining Ge to
ders the devices unsuitable for VDD scaling. The high leakage
the pocket region, the device is not limited by the drawbacks
floor (∼100 pA/µm) [2], [5], [6] makes the devices incompati-
of conventional SiGe TFETs, and therefore, high Ion and steep
ble with low-power VLSI technologies. Both shortcomings are
SS can be achieved concurrently. The optimized structure has
likely due to the enhanced generation/recombination, which is
the potential to achieve Ion /Ioff > 7 × 106 and ∼125% Ion
inherent to III–V materials.
improvement compared with 14-nm FinFETs under VDD of
SiGe is one of the promising material systems for TFET
0.5 V. Its advantage in Ion over the FinFETs further increases
applications because of its FinFET/gate-all-around (GAA)
to over ×100 to as VDD is reduced to 0.3 V.
Manuscript received June 24, 2018; revised September 4, 2018;
accepted September 29, 2018. Date of publication October 18, 2018; II. D EVICE C ONCEPT
date of current version November 26, 2018. This work was supported
by Defense Advanced Research Projects Agency under Grant FA8650- A cross-sectional schematic of the Ge-pocket TFET with a
15-1-7574. The review of this paper was arranged by Editor J. Knoch. counter-doped pocket is shown in Fig. 1(a). The key device
(Corresponding author: Weicong Li.)
The authors are with the Department of Electrical Engineering, Univer- parameters are listed in Table I. When a positive bias is applied
sity of California at Los Angeles, Los Angeles, CA 90095 USA (e-mail: to the gate, the conduction band of the channel is lowered.
[email protected]). Once the valence band of the source and the conduction band
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. of the channel overlap, electrons have a finite probability of
Digital Object Identifier 10.1109/TED.2018.2874047 tunneling through the potential barrier from the source to the

0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 5290 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 12, DECEMBER 2018

TABLE I
D EVICE D IMENSIONS AND THE N OMINAL D OPING
C ONCENTRATIONS AT E ACH R EGION

Fig. 2. Tunneling model calibration for (a) Ge-source TFET [10] and
(b) Si/SiGe RITD [22].

channel, which depends on the height and the width of the

tunnel barrier [12]. In the proposed structure, the fully strained low temperature [Fig. 2(a)]. The values of the parameters
Ge (E g ∼ 0.4 eV [13]) at the pocket region reduces the tunnel agree with those in [21]. To generalize the model for SiGe
barrier height, whereas the counter-doping reduces the tunnel TFETs with arbitrary composition, it is further calibrated to the
barrier width by enhancing the lateral electric field across the Si/SiGe resonant interband tunneling diode (RITD) from [22].
tunnel junction [14], [15]. As a result, the device performance Due to the low growth/process temperature, the dopant inter-
is expected to improve significantly. diffusion is suppressed in the RITD. Therefore, the box-shaped
Compared with TFETs with a Ge source [10], [16], doping profile is assumed. The simulation results match the
Ge in the proposed TFET design is only confined to the experimental data for small bias, where the band-to-band
pocket region. As the tunneling process occurs across the tunneling dominates the conduction [Fig. 2(b)]. The doping-
tunnel barrier around the tunnel junction, extending Ge beyond dependent mobility model, the interface mobility degradation
the pocket region does not improve Ion much, and a thick model, and the high-field saturation model are used in the
Ge heteroepitaxy is more challenging to achieve. The pocket simulation. The quantum confinement (QC) can be treated
thickness is set to 4 nm, which is approximately the tunnel rigorously by adopting the Schrodinger–Poisson solver, but the
barrier width. As the pocket thickness reduces below 4 nm, computational burden makes it unsuitable for device optimiza-
the tunneling process starts to occur outside the pocket region, tion. Therefore, the treatment of QC is the following: under the
and the tunneling current decreases significantly due to the low-current regime, the electron density in the channel is small
large tunneling barrier height outside the pocket region. Due to such that the redistribution of electrons due to QC has a neg-
the large bandgap of Si, the ambipolar conduction at the drain ligible impact on the electrostatic potential profile. Therefore,
side can be effectively suppressed for low VDD operation. it is ignored in the study. The size-induced bandgap widening
has been incorporated into the simulation based on [23]. The
III. O PTIMIZATION AND S CALABILITY
field-induced quantization has been ignored due to the small
A. Simulation Setup vertical electric field (i.e., small gate voltage for low power),
The nonlocal dynamic band-to-band tunneling in Synopsis and the difference is partially compensated by the fact that this
Sentaurus TCAD provides a conceptually sound yet computa- effect was not included during the previous tunneling model
tionally efficient tool to investigate the tunneling process. The calibration. The physical dimensions of the devices are chosen
model is derived from the Landauer Buttiker formula, which to enable a fair performance comparison between the proposed
is equivalent to the nonequilibrium Green function (NEGF) device and 14-nm FinFETs (Table I). The DOS of Six Ge1−x
for coherent conduction [17]. The electron–phonon interaction has been linearly interpolated between the values of Si and
in the indirect tunneling is taken into account by incorpo- Ge based on the composition. The bandgap of Si, strained
rating the phonon emission/absorption into the calculation Ge, and strained Si0.5 Ge0.5 are 1.13, 0.43, and 0.81 eV (with
of the tunneling probability. The number of tunneling chan- size-induced bandgap widening included), respectively, with a
nels is calculated by integrating the available density of constant electron affinity of 4.07 eV (Table II). The gate work
states (DOS) perpendicular to the tunneling direction [18]. function is set to 4.3 eV. All doping profiles are assumed to be
SS ∼20 mV/dec has been demonstrated experimentally in abrupt. The doping concentrations are optimized sequentially,
∼pA/µm range [19], [20], which suggests that the impact which allow a clear interpretation of the simulation results.
of band tail on the SS is negligible for SS ≥ 20 mV/dec. The values of Nsource = 1020 cm−3 , Npocket = 4 × 1019 cm−3 ,
Therefore, the Urbach tail is ignored in this paper. The Nchannel = 1016 cm−3 , and Ndrain = 1020 cm−3 are used
tunneling model is calibrated to the vertical TFET with a as the doping concentrations in the initial simulation study.
Ge source in [10]. The simulated doping profile is extracted During SiGe growth, Ge tends to segregate at the surface
from the scanning spreading resistance measurements, and to minimize the surface free energy. By lowering the growth
the device structure is confirmed by cross-sectional TEM. By temperature, the hydrogen passivates the surface and reduces
adjusting the parameters A and B in the tunneling model, the segregation [24]. To account for the Ge segregation during
the simulated transfer characteristics are fit to the experimental the growth, a linear composition gradient of 20% per nm
data measured at 78 K, because the defect-assisted tunneling is assumed in the simulation [Fig. 1(b)]. This allows the
and the Shockley–Read–Hall recombination are suppressed at simulation to yield a more realistic prediction of the device

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 LI AND WOO: OPTIMIZATION AND SCALING OF Ge-POCKET TFET 5291

TABLE II
M ATERIAL PARAMETERS A DOPTED IN THE S IMULATION . DOS
E FFECTIVE M ASSES A RE A SSUMED FOR C ALCULATING
THE M ODIFIED B ANDGAPS [23]

Fig. 4. Band diagram of Ge-pocket, Ge-source, and Si0.5 Ge0.5 -source

TFETs at (a) low gate bias and (b) high gate bias.

Fig. 3. Transfer characteristics of Ge-pocket, Ge-source, and Si0.5 Ge0.5 -

source TFETs (Nsource = 1020 cm−3 , Npocket = 4 × 1019 cm−3 ,
Fig. 5. Transfer characteristics of Ge-pocket TFETs with different source
Nchannel = 1016 cm−3 , and Ndrain = 1020 cm−3 ). doping concentrations.

performance. For Ion comparison, Ioff is fixed at 10 pA/µm

to meet the low operating power standard for International
Technology Roadmap for Semiconductors (ITRS) [25], and
VDD is set to 0.5 V. This enables a fair comparison of the
device performance (i.e., Ion ) with fixed power consumption.

B. Simulations Results
1) Ge-Pocket TFET Versus SiGe-Source TFET: Fig. 3 shows
the transfer characteristics of Ge-pocket, Ge-source, and
Si0.5 Ge0.5 -source TFETs. For the latter two devices, Ge and Fig. 6. Band diagram of Ge-pocket TFETs with different source doping
Si0.5 Ge0.5 have been used for the source and the pocket concentration at (a) low gate bias and (b) high gate bias.
regions, respectively. All three structures have the same doping
profile. The ambipolar conduction is absent for all the three
devices because Si is used for the drain region. The Ge-pocket Si0.5 Ge0.5 ) to 0.43 eV (strained-Ge) in the pocket region.
TFET shows a steep SS comparable to the Si0.5 Ge0.5 -source Note that the discontinuity of the valence band shown in
TFET at the low current regime. It also exhibits IDS compara- Fig. 4 is the result of composition grading, but it does not
ble to the Ge-source TFET at high VGS . For the Ge-pocket negatively affect the performance. Compared with the devices
TFET, the large bandgap in the source region blocks the with abrupt Ge mole fraction change at the pocket/channel
tunneling at a low gate bias [Fig. 4(a)]. Therefore, the device interface, the difference in the current is less than 2%. This
can be switched OFF more efficiently, which leads to steep is because the channel resistance is dominated by the tunnel
switching. At a high gate bias, the Ge-pocket TFET has resistance at the source/pocket junction.
a small tunnel barrier that is comparable to the Ge-source 2) Impact of Doping Concentrations: Fig. 5 shows the trans-
TFET [Fig. 4(b)], which leads to a high tunneling current. fer characteristics of the Ge-pocket TFET with different
After adjusting the gate voltage to match Ioff , the Ge-pocket source doping concentrations. The device with Nsource =
TFET (48 µA/µm) exhibits a higher Ion than the Ge-source 5 × 1020 cm−3 shows a significantly larger leakage current
TFET (34 µA/µm) and Si0.5 Ge0.5 -source TFET (7 µA/µm). and a degraded SS in the low-current regime because of
Comparing the Ge-pocket TFET with the Si0.5 Ge0.5 -source the overlap between the valence band of the source and
TFET, Ion is improved by roughly 6×. This is achieved by the conduction band of the channel even at VGS = 0 V
reducing the tunneling barrier height from 0.81 eV (strained- [Fig. 6(a)]. Fig. 6(b) shows that increasing the source doping

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 5292 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 12, DECEMBER 2018

Fig. 9. Band diagram of Ge-pocket TFETs with different pocket doping

Fig. 7. Ion of Ge-pocket TFET as a function of the source doping concentrations at a low gate bias. The pocket region comes out of full
concentration. depletion for high pocket doping concentration.

Fig. 8. Ion of Ge-pocket TFET as a function of the pocket doping Fig. 10. Ion of the Ge-pocket TFET as a function of the drain doping
concentration. concentration.

concentration increases the lateral electric field at the tunnel

junction, which in turn reduces the tunnel barrier width. This
results in a higher tunneling probability that is close to one.
However, increasing the source doping moves the hole quasi-
Fermi level away from the valence band edge in the source,
which reduces the available electrons for tunneling in the
source [26] (Fig. 6). Note that in the source, only the elec-
trons below the valence band can tunnel to the channel. The
tunneling current is the product of the tunneling probability Fig. 11. Band diagram of Ge-pocket TFET with different drain doping
and the number of available electrons; thus, there exists an concentrations at (a) low gate bias and (b) high gate bias.
optimum source doping concentration for high Ion as shown
in [27]. The optimum source doping concentration is found to
be 1020 cm−3 (Fig. 7). to 1018 cm−3 . This is due to the fact that the dose of the total
The concept of counter-doped pocket has been previously depletion charge in the body is small in this doping range
discussed in [14] and [15]. Increasing the pocket doping con- because of the thin body of the device. As a result, the doping
centration significantly improves the performance of TFETs by in the channel has a negligible impact on the electrostatic
enhancing the electric field at the tunnel junction and reducing profile. In addition, since the channel resistance is dominated
the tunnel barrier width (Fig. 8). However, for a pocket doping by the tunnel junction, the change in the mobility due to the
higher than 5 × 1019 cm−3 , the pocket comes out of full channel doping concentration has a negligible effect on Ion .
depletion (Fig. 9). The electrons in the nondepleted n+ pocket Ion of the proposed structure is independent of the channel
region serves as an intrinsic source, and the device becomes an doping for a concentration up to 1018 cm−3 .
n+/p+ tunnel junction in series with a conventional MOSFET. Fig. 10 shows the impact of the drain doping concentration
Therefore, the device loses its steep switching characteristics. on Ion of the Ge-pocket TFET. For a high drain doping
The pocket doping concentration needs to be optimized to concentration, the electric field from the drain penetrates to
ensure the full depletion of the pocket. the channel region, and the conduction band in the channel
The channel doping has a negligible impact on the per- is lowered, similar to the drain-induced barrier lowering in
formance of the Ge-pocket TFET for a concentration up conventional MOSFETs [Fig. 11(a)]. This leads to a reduction

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 LI AND WOO: OPTIMIZATION AND SCALING OF Ge-POCKET TFET 5293

Fig. 12. Benchmark Ge-pocket TFET against 14-nm FinFETs for

(a) VDD scaling and (b) Lgate scaling with VDD = 0.5 V.

TABLE III Fig. 13. SS as a function of IDS for Ge-pocket TFET and 14-nm Intel
P HYSICAL D IMENSIONS OF THE G E -P OCKET TFET FOR FinFET.
F UTURE N ODES S UGGESTED BY ITRS

optimized doping profile for the 14-nm node is used for all
L gate [Fig. 12(b)]. The proposed structure has demonstrated
potential in both L gate and VDD scaling. Note that the scaling
of channel thickness is less straightforward due to the strong
QC. For a more rigorous treatment, NEGF is required.
4) Feasibility and Additional Comments: The performance
in the tunnel barrier height and the width in the channel, of the Ge-pocket TFET relies on the growth of defect-
which increases the tunneling current at a low gate bias. free vertical SiGe heterostructure with high active doping
This phenomenon is expected to become more severe for concentrations. By adopting selective area growth, SiGe het-
shorter L gate . As the drain doping concentration is reduced, erostructure (i.e., Ge pocket/Si0.5 Ge0.5 source) thicker than the
the electric field from the drain to the channel decreases. critical thickness could be achieved on Si [30]. To suppress
Therefore, the leakage current due to the conduction band the relaxation of the Ge-pocket layer, the subsequent growth
lowering is reduced. However, the parasitic resistance of the of SiGe source needs to be carried out at low temperature.
drain becomes significant as indicated by the electron quasi- This could lead to the low activation rate of dopants. Laser
Fermi level in the drain [Fig. 11(b)]. The parasitic voltage annealing offers one potential solution to increase the active
drop leads to a reduction in IDS . The optimum drain doping doping concentration without causing the strain relaxation in
concentration is found to be 1019 cm−3 . Note that the impact the Ge-pocket layer [31].
of the drain doping on the contact resistivity is not considered, Due to the small lateral area of the vertical device
as the simulation is intended to emphasize the impact of the (i.e., ∝tbody ), strain partitioning occurs between Si channel/Ge
drain doping on the leakage current. The contact resistance pocket/Si0.5 Ge0.5 layers [30]. A detailed study on the strain
can be reduced by adding a highly doped drain between the distribution in the heterostructure is necessary for investigating
lightly doped drain and the metal contact, which resembles its impact on the device performance via DOS and electron
the concept of the subcollector in bipolar junction transistor. affinity alignment. Therefore, it has not been included in this
3) Benchmarks and Scalability: The Ge-pocket TFET with paper. However, this is not expected to change the analysis:
an optimized doping concentration (Nsource = 1020 cm−3 , simulation suggests that a ∼50% reduction in Ge hole effective
Npocket = 5 × 1019 cm−3 , Nchannel = 1016 cm−3 , and mass (i.e., correspond to >3% compressive strain) [32] leads
Ndrain = 1019 cm−3 ) has been benchmarked against 14-nm to less than 5% reduction in Ion ; additionally, at the ON-state,
node FinFETs (L gate = 20 nm) in terms of Ion [28], [29]. the tunneling predominantly occurs within the pocket region.
Ion of the FinFETs is extracted from the experimental results Therefore, the electron affinity alignment is expected to have
and verified by calibrated simulations. Under VDD of 0.5 V, an insignificant impact on the performance of the device.
the Ge-pocket TFET exhibits an Ion that is ∼125% higher
than the FinFETs [Fig. 12(a)]. Due to the steep SS in the IV. C ONCLUSION
low-current regime, the advantage of the proposed structure In this paper, the concept of the Ge-pocket TFET is pre-
over the FinFET technology becomes more significant as VDD sented. SiGe is chosen over III–V materials because of its
is further reduced. As VDD is scaled down to 0.3 V, the VLSI compatibility, mature material synthesis, and tunable
enhancement in Ion increases to over 100×. Fig. 13 shows bandgap. Thanks to the reduced bandgap of the fully strained
that the SS of the Ge-pocket TFET degrades significantly as Ge and the enhanced lateral electric field at the tunnel junc-
IDS increases. The proposed device renders its performance tion, the device performance is improved significantly. The
advantage to the FinFET for VDD higher than 0.5 V. ambipolar conduction at the drain side is suppressed by the
The performance of the Ge-pocket TFET for future tech- large bandgap of Si. The proposed device structure shows
nology nodes has been examined. The physical dimensions performance superior to both Si0.5 Ge0.5 -source and Ge-source
of the devices are adopted from ITRS (Table III) and the TFETs. The impact of doping concentrations at different

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 5294 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 12, DECEMBER 2018

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VLSI Technol., Honolulu, HI, USA, Jun. 2009, pp. 178–179. he is currently a Professor.

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