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1.2-V CMOS op-amp with a dynamically biased output stage

Article in IEEE Journal of Solid-State Circuits · May 2000

DOI: 10.1109/4.839923 · Source: IEEE Xplore

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632 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000

Brief Papers_______________________________________________________________________________
1.2-V CMOS Op-Amp with a Dynamically Biased Output Stage
G. Giustolisi, G. Palmisano, G. Palumbo, and T. Segreto

Abstract—A very low-voltage operational amplifier in a stan-

dard CMOS process with a 0.75-V threshold voltage is presented.
It uses a novel dynamically biased output stage based on the
switched-capacitor approach. Thanks to this, drive performance
is greatly improved and accurate current control is also achieved.
The amplifier is capable of working with a power supply as low
as 1.2 V while providing a 74-dB total harmonic distortion with
a 700-mV peak-to-peak output voltage into a 500- and 20-pF
output load. The open-loop gain and the gain-bandwidth product
are higher than 90 dB and 2.2 MHz, respectively.
Index Terms—CMOS analog integrated circuits, MOSFET am-
plifiers, operational amplifiers.

I. INTRODUCTION

D URING recent years, the literature has paid more and

more attention to integrated circuits working at very
low-voltage power supplies (i.e., 1.5 V or less). This is mainly
due to the wide use of portable equipment, requiring low-con- Fig. 1. Schematic of the input stage.
sumption IC's to increase battery life.
Cutting down power consumption usually means reducing on whether the source-coupled pair uses NMOS or PMOS
both the power-supply voltage and current. However, given the transistors. This drawback can be overcome by adopting the
dependence of transistor noise on the quiescent current, the switched-capacitor (SC) approach, which is very suitable for
latter cannot be achieved in some high-performance analog low-voltage analog signal processing.
building blocks. Therefore, the only way to reduce power In this paper, a new operational amplifier that works with
consumption in many cases is to reduce the supply voltage. a 1.2-V power supply is presented. It adopts a folded mirror
Today, typical supply voltages for analog circuits are around load in the input stage, which saves input swing, and includes
2.5–3 V, but future trends suggest supply voltages of 1.5 V or a dynamically biased class-AB output stage providing both a
even less. With such low values, traditional CMOS circuit solu- rail-to-rail output swing and a high output current.
tions can be adopted only if a low threshold process is available. The operational amplifier has been implemented in a stan-
Otherwise, new circuit solutions capable of working with a re- dard 1.2- m CMOS process with threshold voltages of around
duced power supply have to be designed [1]–[6]. 0.75 V. It dissipates less than 150 W.
A fundamental building block in analog processing is the
power operational amplifier (op-amp). Unlike the transconduc- II. CIRCUIT DESCRIPTION
tance amplifier, it includes an output stage capable of driving
off-chip, low load resistances. Obviously, the output stage must A. The Input Stage
respect the specifications required of drive capability, linearity, The input stage is shown in Fig. 1. It is made up of the source-
and output swing. coupled pair M1–M2 and the folded mirror M6–M7. Transistors
Another critical aspect in low-voltage design is the M3–M5 bias current sources [6].
common-mode input swing, which depends on the input stage. The common-mode input voltage must satisfy the fol-
Indeed, while the output bias voltage is preferably set lowing conditions:
to half the power supply to provide maximum output swing, the
input terminals must be set to a common-mode input voltage (1)
, which may be higher or lower than , depending and

(2)
Manuscript recieved February 18, 1999; revised October 11, 1999.
The authors are with the Dipartimento Elettrico Elettronico e Sistemistico,
Università di Catania, Catania I-95125, Italy. In effect, for a 1.2-V power supply, the upper bound of
Publisher Item Identifier S 0018-9200(00)02864-X. is the power supply itself. Therefore, we can achieve an upper
0018–9200/00$10.00 © 2000 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000 633

Fig. 3. Schematic of the clock booster.

switches S3 and S4, at least, need a gate voltage that is higher

than the available power supply because their drain and source
terminals are at half the supply voltage. Therefore, the clock
Fig. 2. Schematic of the output stage. booster in shown Fig. 3 was adopted [8]. Moreover, to simplify
the clock phase generator, all the switches were implemented as
bound that is higher than with respect to the traditional NMOS pass-transistors.
differential stage loaded with a p-type current mirror. By setting The clock booster is made up of capacitor and transistors
to 1 V and assuming values of lower than 0.1 V, a MB1-MB5, which have the bulk terminal short-circuited with
common-mode range (CMR) of around 400 mV is achieved. the source terminal. Capacitor was set much larger than
the load capacitor .
B. The Output Stage The clock booster works as follows. Transistors MB1 and
1) Circuit Behavior: The novel class-AB output stage MB2 perform an inverter stage. When the clock is high,
capacitor is precharged to through transistor MB3,
is shown in Fig. 2. Common source transistors MO1 and
which will be in the linear region. Moreover, transistor MB4 is
MO2 provide a rail-to-rail output swing, diode-connected
open and load capacitor is discharged through transistor
transistors MO3 and MO4 set the bias voltages for the control
MB5. Next, when the clock goes down, the output of the in-
of the quiescent current in the output branch, and the SC
verter MB1–MB2 goes to , transistors MB3 and MB5 open,
network, composed of capacitors - ( and
and transistor MB4 closes. Since capacitor is much larger
) and switches S1–S6, performs a dynamic biasing
than , the output voltage is boosted above the power supply.
and feeds the input signal [7]. Switches S1–S6 are controlled
by complementary clock phases and . More exactly, the output voltage tries to reach about twice ,
but during the last part of the transient, the bulk junctions of
Assuming standby conditions, capacitors with
MB3 clamp the output voltage to around . This over-
switches S1–S4 and capacitors with switches
drive is sufficiently high to drive the switches of the output stage.
S3–S6 perform as two SC damped integrators. In steady-state
conditions, the voltages across capacitors and are
equal to the gate voltages of MO3 and MO4, and , C. Complete Amplifier
respectively. Since the closed-loop amplifier sets the current in The whole operational amplifier is shown in Fig. 4. It is made
MO1 and MO2 as equal, the gate voltages of MO1 and MO2, up of three main stages, which are the input and the output
and the input bias voltage, are forced to , , and , stage in Figs. 1 and 2, respectively, and the intermediate stage
respectively. Therefore, current is set by currents and M8–M12. This last stage is composed of the folded-mirror in-
and the aspect ratios of MO1, MO3 and MO2, MO4. verter M8–M10 and the common source M11–M12. The in-
The input bias voltage, i.e., , was set to half the supply verter was included for frequency compensation purposes.
voltage to achieve maximum input overdrive while capacitors The circuit shows three low-frequency poles at the output
and were set larger than the gate-source capacitances of each gain stage. Then the nested Miller compensation was
of MO1 and MO2 to avoid signal attenuation at the gate nodes used to provide frequency stability [9]–[12]. The two capaci-
of MO1 and MO2. tors and were connected between the output of the
Note that the gate voltages of MO1 and MO2 are pulled be- amplifier and the output of the inner stages in order to achieve
yond and , respectively, due to the large input over- a single low-frequency pole at the output of the input stage
drive. The maximum swing on the gates of MO1 and MO2 is and to move the other two poles to frequencies higher than the
limited by the forward biasing of the switch bulk junctions. gain-bandwidth product. Resistors and were included
2) The Clock Booster: Since the process threshold voltages to transform the right half-plane zeros into high-frequency left
are around 0.75 V and the power supply is as low as 1.2 V, half-plane zeros.
634 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000

Fig. 4. Schematic of the operational amplifier.

TABLE I TABLE II
PARAMETERS OF THE FREQUENCY COMPONENT VALUES AND BIAS CURRENTS
RESPONSE

The expressions of the gain, the gain-bandwidth product, and

the main poles and zeros of the frequency response are summa-
rized in Table I. Resistances , , and are the output re-
sistances of the input stage, the intermediate stage, and the load
resistance, respectively.

III. EXPERIMENTAL RESULTS

The circuit was fabricated in a standard 1.2- m CMOS Step response measurements were carried out with the am-
process with threshold voltages around 0.75 V for both PMOS plifier in a noninverting configuration and with a closed-loop
and NMOS transistors. The power supply was set to 1.2 V. gain of six (around 15 dB) by loading the output with 20 pF in
Component values and bias currents are shown in Table II. With parallel to 1 k . Figs. 5 and 6 show the rising and the falling
the clock frequency is set to 100 kHz, the power dissipation is edge of the step response, respectively, for an input voltage of
equal to 150 W and the power-supply current has a ripple less 100 mV. The settling time at 1% is 1.6 s, and the slew rate is
than 10%. 0.54 V/ s.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000 635

Fig. 8. HD2, HD3, and THD versus output voltage (R =1k ).

Fig. 5. Positive step response.

Fig. 9. HD2, HD3, and THD versus output voltage (R = 500 ).

TABLE III
MEASURED MAIN PERFORMANCE

Fig. 6. Negative step response.

resulting in 2.2 MHz and 56 , respectively. The output voltage

ripple due to the switching activity is less than 1 mV.
The maximum efficiency of the output stage is close to 45%
for a 1-V peak-to-peak output signal. It decreases linearly
with the decreasing of the output voltage with a slope of
115 10 %/mV.
Fig. 7. Closed-loop frequency response.
Total harmonic distorition (THD) measurements were carried
out for two different resistive loads and with a 1-kHz input signal
For the same configuration, the closed-loop frequency re- frequency. Then measures for the unity-gain configuration were
sponse is shown in Fig. 7. Measurements with unity feedback of extrapolated and plotted in Figs. 8 and 9 for a resistive load of
gain-bandwidth product and phase margin were also carried out, 1 k and 500 , respectively. Despite the low aspect ratios of the
636 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000

with a simple oscillator since no accuracy or frequency stability

is required.
The very good linearity performance achieved validates the
proposed solution.

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