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Table of Contents
15ECL77 : VLSI LAB.............................................................................2
A. LABORATORY INFORMATION.................................................................................... 2
1. Lab Overview................................................................................................................... 2
2. Lab Content..................................................................................................................... 3
3. Lab Material..................................................................................................................... 5
4. Lab Prerequisites:............................................................................................................ 5
5. General Instructions......................................................................................................... 6
6. Lab Specific Instructions.................................................................................................. 6
B. OBE PARAMETERS..................................................................................................... 7
1. Lab / Course Outcomes................................................................................................... 7
2. Lab Applications.............................................................................................................. 7
3. Articulation Matrix........................................................................................................... 8
4. Mapping Justification....................................................................................................... 9
5. Curricular Gap and Content............................................................................................ 10
6. Content Beyond Syllabus................................................................................................ 11
C. COURSE ASSESSMENT............................................................................................ 11
1. Course Coverage............................................................................................................ 11
2. Continuous Internal Assessment (CIA)............................................................................12
D. EXPERIMENTS........................................................................................................ 12
Experiment 01 :................................................................................................................. 12
Experiment 02 : Buffer....................................................................................................... 14
Experiment 03 : Transmission Gate....................................................................................15
Experiment 04 : Logic Gates............................................................................................... 16
......................................................................................................................................... 16
Experiment 05 : S-R Flip Flop............................................................................................. 18
Experiment 06 : D Flip Flop................................................................................................ 19
Experiment 07 : T Flip Flop................................................................................................ 21
Experiment 08 : JK Flip Flop............................................................................................... 22
Experiment 09 : Parallel Adder........................................................................................... 23
Experiment 10 : Serial Adder.............................................................................................. 25
Experiment 11 :4-bit Asynchronous Counter......................................................................26
......................................................................................................................................... 26
Experiment 12 :4-bit synchronous Counter........................................................................28
......................................................................................................................................... 28
Experiment 13 :CMOS INVERTER......................................................................................... 29
......................................................................................................................................... 29
Experiment 14 :Single Stage Differential amplifier..............................................................31
......................................................................................................................................... 31
Experiment 15 :Comon Source Differential amplifier...........................................................33

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......................................................................................................................................... 33
Experiment 16 :Comon Drain Differential amplifier.............................................................35
......................................................................................................................................... 35
Experiment 17 :R-2R DAC.................................................................................................. 37
......................................................................................................................................... 37

Note : Remove “Table of Content” before including in CP Book

15ECL77 : VLSI LAB

A. LABORATORY INFORMATION
1. Lab Overview
Degree: B.E Program: EC
Year / Semester : 4/7 Academic Year: 2018-19
Course Title: VLSI Lab Course Code: 15ECL77
Credit / L-T-P: 2 / 0-1-2 SEE Duration: 180 Minutes
Total Contact Hours: 40 Hrs SEE Marks: 80 Marks
CIA Marks: 20 Assignment 1 / Module
Course Plan Author: Mrs. Shilpa Rani P Sign Dt :
Checked By: Mr. Sign Dt :

2. Lab Content
Unit Title of the Experiments Lab Concep Blooms
Hours t Level
1 Write Verilog Code for the following circuits and their Test 3 Basic L4
Bench for verification, observe the waveform and synthesize VLSI Analyze
the code circuits
i. An inverter synthesi
ii. A Buffer s
iii. Transmission Gate
2 Write Verilog Code for the following circuits and their Test 3 Logic L4
Bench for verification, observe the waveform and synthesize Gates
the code synthesi
iv. Basic/universal gates s
3 Write Verilog Code for the following circuits and their Test 3 Flip-flop L4
Bench for verification, observe the waveform and synthesize synthesi
the code s
v. Flip flop -RS, D, JK, MS, T

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4 Write Verilog Code for the following circuits and their Test 3 Adders L4
Bench for verification, observe the waveform and synthesize and
the code counters
vi. Serial & Parallel adder synthesi
vii. 4-bit counter [Synchronous and Asynchronous counter] s
5 Write Verilog Code for the following circuits and their Test 3 SAR L4
Bench for verification, observe the waveform and synthesize synthesi
the code s
viii. Successive approximation register [SAR]
6 Design an Inverter with given specifications**, completing the 6 CMOS L4
design flow Inverter
mentioned below: design
a. Draw the schematic and verify the following
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design
e. Verify & Optimize for Time, Power and Area to the given
constraint*
7 Design the (i) Common source and Common Drain amplifier 9 CMOS L4
and (ii) A Single Aplifiers
Stage differential amplifier, with given specifications**, Design
completing the
design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design.
8 Design an op-amp with given specification** using given 3 CMOS L4
differential amplifier OPAMP
Common source and Common Drain amplifier in library*** Design
and completing the
design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii). AC Analysis
iii) Transient Analysis
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b. Draw the Layout and verify the DRC, ERC

c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design.
9 Design a 4 bit R-2R based DAC for the given specification and 3 R-2R L4
completing the based
design flow mentioned using given op-amp in the library***. DAC
a. Draw the schematic and verify the following Design
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
10 For the SAR based ADC mentioned in the figure below draw 3 SAR L4
the mixed signal based
schematic and verify the functionality by completing ASIC ADC
Design FLOW. Design
[Specifications to GDS-II]

3. Lab Material
Unit Details Available
1 Text books
Dept Lab Manual In Dept Library

2 Reference books
1. Digital Logic Applications and Design, John M Yarbrough, Thomson In College Library
Learning, 2001. ISBN 981-240-062-1.
2. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and In College Library
Synthesis”,
Pearson Education, Second Edition.

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3. “Basic VLSI Design”- Douglas A. Pucknell& Kamran Eshraghian, PHI In College Library
3rd Edition (original Edition – 1994)

3 Others (Web, Video, Simulation, Notes etc.)

4. Lab Prerequisites:
- - Base Course: - -
SNo Course Course Name Topic / Description Sem Remarks
Code
1 15EC33 Digital Elecronics Logic Gates, Flip-flops, Adders 3
2 15EC53 Verilog HDL Gate-Level Modeling,Dataflow 5
Modeling, Behavioral Modeling
3 15EC63 VLSI Design CMOS circuit Design, Stick diagrams 6
and Layout
Note: If prerequisites are not taught earlier, GAP in curriculum needs to be addressed. Include in
Remarks and implement in B.5.

5. General Instructions
SNo Instructions Remarks
1 Observation book and Lab record are compulsory.
2 Students should report to the concerned lab as per the time table.
3 After completion of the program, certification of the concerned staff in-
charge in the observation book is necessary.
4 Student should bring a notebook of 100 pages and should enter the
readings /observations into the notebook while performing the
experiment.
5 The record of observations along with the detailed experimental
procedure of the experiment in the Immediate last session should be
submitted and certified staff member in-charge.
6 Should attempt all experiments given in the list session wise.
7 It is responsibility to create a separate directory to store all the
programs, so that nobody else can read or copy.
8 When the experiment is completed, should shut down the system
properly.
9 Any damage of the equipment or burn-out components will be viewed
seriously either by putting penalty or by dismissing the total group of
students from the lab for the semester/year
10 Completed lab assignments should be submitted in the form of a Lab
Record in which you have to write the algorithm, program code along

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with comments and output for various inputs given

6. Lab Specific Instructions

SNo Specific Instructions Remarks
1 Start computer
2 Open the text editor
3 Select new file.
4 Write the program
5 Save the program with .v extension.
6 Compile the program
7 Execute the program

B. OBE PARAMETERS
1. Lab / Course Outcomes
# COs Teach. Concept Instr Assessment Blooms’
Hours Method Method Level
1 Simulate and synthesize basic VLSI 3 Basic VLSI Demons Slip Test L4
circuits circuits tration/
using Verilog coding synthesis Practica
l
2 Simulate and synthesize logic Gates 3 Logic Gates Practica Slip Test L4
using Verilog coding synthesis l
3 Simulate and synthesize flip-flops 3 Flip-flop Practica Slip Test L4
using Verilog coding synthesis l
4 Simulate and synthesize adders and 3 Adders and Practica Slip Test L4
counters using Verilog coding counters l
synthesis
5 Simulate and synthesize SAR using 3 SAR Practica Slip Test L4
Verilog coding synthesis l
6 Design CMOS Inverter schematic , 6 CMOS Demons Slip Test L4
Layout and verify LVS. Inverter tration/
design Practica
l
7 Design CMOS Amplifier schematic , 9 CMOS Practica Slip Test L4
Layout and verify LVS. Aplifiers l
Design
8 Design Op-amp using differential 3 CMOS Practica Slip Test L4
amplifier and CDA schematic , Layout OPAMP l
and verify LVS. Design
9 Design R-2R DAC schematic, Layout 3 R-2R based Practica Slip Test L4

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and verify DRC, ERC DAC Design l

10 Draw mixed signal schematic and verify 3 SAR based Practica Slip Test L4
its functionality of SAR based ADC ADC Design l
- Total 39 - - - -
Note: Identify a max of 2 Concepts per unit. Write 1 CO per concept.

2. Lab Applications
SNo Application Area CO Level
1 Static RAM, Image sensors CO1 L4
2 Alarm switch, Temperature detector, Door bell switch CO2 L4
3 Data storage, data trasfer, registers, counters, frequency division CO3 L4
4 Designing ALU, Fast multipilers, Digital clocks, Multiplexing, Parallel to serial CO4 L4
data conversion
5 Analog to digital conversion, PLC application CO5 L4
6 Data converters, Transceivers CO6 L4
7 FET, Oscilloscopes, Electronic voltmeters, operational aplifiers CO7 L4
8 Voltage summer, Integrators, digital to analog connversion CO8 L4
9 Motor control, digital potentiometers, Software Radio, Data distribution CO9 L4
system
10 Temperature sensors, bus architecture in microcontroller, distance locator CO10 L4

Note: Write 1 or 2 applications per CO.

3. Articulation Matrix
(CO – PO MAPPING)
- Course Outcomes Program Outcomes
# COs PO PO PO PO PO PO PO PO PO PO PO PO Level
1 2 3 4 5 6 7 8 9 10 11 12
15ECL77.1 Simulate and synthesize basic 3 1 3 3 L4
VLSI circuits
using Verilog coding
15ECL77.2 Simulate and synthesize logic 3 1 3 3 L4
Gates
using Verilog coding
15ECL77.3 Simulate and synthesize flip- 3 1 3 3 L4
flops
using Verilog coding
15ECL77.4 Simulate and synthesize adders 3 1 3 3 L4
and counters using Verilog
coding
15ECL77.5 Simulate and synthesize SAR 3 1 3 3 L4

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using Verilog coding

15ECL77.6 Design CMOS Inverter schematic 3 2 1 3 3 L4
, Layout and verify LVS.
15ECL77.7 Design CMOS Amplifier 3 2 1 3 3 L4
schematic , Layout and verify
LVS.
15ECL77.8 Design Op-amp using 3 2 1 3 3 L4
differential amplifier and CDA
schematic , Layout and verify
LVS.
15ECL77.9 Design R-2R DAC schematic, 3 2 1 3 3 L4
Layout and verify DRC, ERC
15ECL77.1 Draw mixed signal schematic 3 2 1 3 3 L4
0 and verify its functionality of
SAR based ADC
Average 3 1.5 0.5 3 3
Note: Mention the mapping strength as 1, 2, or 3

4. Mapping Justification
Mapping Mapping Justification
Level
CO PO - -
CO1 PO1 3 Knowledge of basic VLSI circuits is required for understanding
complex VLSI problems
CO1 PO2 1 Knowledge of basic VLSI circuits is required for problem analysis in
VLSI designs.
CO1 PO5 3 Simulation of basic VLSI circuits requires tools like “xilinx”
CO1 PO9 1 Individual and team work is required for simulation of basic VLSI
circuits.
CO2 PO1 3 Knowledge of logic gates is required for understanding complex VLSI
problems
CO2 PO2 1 Knowledge of logic gates is required for problem analysis in VLSI
designs.
CO2 PO5 3 Simulation of logic gate circuits requires tools like “xilinx”
CO2 PO9 1 Individual and team work is required for simulation of logic gates.
CO3 PO1 3 Knowledge of flip-flops is required for understanding complex VLSI
problems
CO3 PO2 1 Knowledge of flip-flops is required for problem analysis in VLSI
designs.
CO3 PO5 3 Simulation of flip-flop circuits requires tools like “xilinx”
CO3 PO9 1 Individual and team work is required for simulation of Flip-flops

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CO4 PO1 3 Knowledge of adders is required for understanding complex VLSI

problems
CO4 PO2 1 Knowledge of adders is required for problem analysis in VLSI designs.
CO4 PO5 3 Simulation of adder circuits requires tools like “xilinx”
CO4 PO9 1 Individual and team work is required for simulation of adders
CO5 PO1 3 Knowledge of SAR is required for understanding analog to digital
convertion
CO5 PO2 1 Knowledge of SAR is required for problem analysis in VLSI designs.
CO5 PO5 3 Simulation of SAR circuit requires tools like “xilinx”
CO5 PO9 1 Individual and team work is required for simulation of SAR
CO6 PO1 3 Knowledge of CMOS Inverter is required for understanding complex
VLSI problems
CO6 PO2 2 Knowledge of CMOS Inverter is required for problem analysis in VLSI
designs.
CO6 PO3 1 Designing of CMOS Inverter is required for development of complex
VLSI circuits
CO6 PO5 3 Design of CMOS Inverter requires “cadence” or “tanner tools” usage.
CO6 PO9 2 Individual and team work is required for design of CMOS Inverter
CO7 PO1 3 Knowledge of CMOS Amplifiers is required for solution of
amplification related problems
CO7 PO2 2 Knowledge of CMOS Amplifiers is required for problem analysis in
VLSI designs.
CO7 PO3 1 Designing of CMOS Amplifiers is required for development of
complex VLSI circuits
CO7 PO5 3 Design of CMOS Amplifiers requires “cadence” or “tanner tools” usage.
CO7 PO9 2 Individual and team work is required for design of CMOS Amplifiers
CO8 PO1 3 Knowledge of Op-amp is required for solution of amplification related
problems
CO8 PO2 2 Knowledge of Op-amp is required for problem analysis in VLSI
designs.
CO8 PO3 1 Designing of Op-amp is required for development of complex VLSI
circuits
CO8 PO5 3 Design of Op-amp requires “cadence” or “tanner tools” usage.
CO8 PO9 2 Individual and team work is required for design of Op-amp
CO9 PO1 3 Knowledge of DAC is required for solving signal conversion related
problems
CO9 PO2 2 Knowledge of DAC is required for problem analysis in VLSI designs.
CO9 PO3 1 Designing of DAC is required for development of complex VLSI
circuits
CO9 PO5 3 Design of DAC requires “cadence” or “tanner tools” usage.
CO9 PO9 2 Individual and team work is required for design of DAC

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CO10 PO1 3 Knowledge of SAR is required for solving signal conversion related
problems
CO10 PO2 2 Knowledge of SAR is required for problem analysis in VLSI designs.
CO10 PO3 1 Designing of SAR is required for development of complex VLSI circuits
CO10 PO5 3 Design of SAR requires “cadence” or “tanner tools” usage.
CO10 PO9 2 Individual and team work is required for design of SAR
Note: Write justification for each CO-PO mapping.

5. Curricular Gap and Content

SNo Gap Topic Actions Planned Schedule Planned Resources Person PO Mapping
1
2
3
4
5

Note: Write Gap topics from A.4 and add others also.

6. Content Beyond Syllabus

SNo Gap Topic Actions Planned Schedule Planned Resources Person PO Mapping
1
2
3
4
5

Note: Anything not covered above is included here.

C. COURSE ASSESSMENT
1. Course Coverage
Unit Title Teachi No. of question in Exam CO Levels
ng CIA- CIA- CIA- Asg- Asg- Asg- SEE
Hours 1 2 3 1 2 3
1 Inverter, Buffer, TG 03 1 - - 1 - - 1 CO1 L4
2 Logic gates 03 1 - - 1 - - 1 CO2 L4
3 Flip-flops 03 1 - - 1 - - 1 CO3 L4
4 Adders, Counters 03 1 - - 1 - - 1 CO4 L4
5 SAR 03 1 - - 1 - - 1 CO5 L4

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6 CMOS Inverter Schematic 03 - 1 - - 1 - 1 CO6 L4

7 CMOS Inverter Layout 03 - 1 - - 1 - 1 CO6 L4
8 Common Source Amplifier 03 - 1 - - 1 - 1 CO7 L4
9 Common Drain Amplifier 03 - 1 - - 1 - 1 CO7 L4
10 Differential Amplifier 03 - - 1 - - 1 1 CO7 L4
11 Op-amp 03 - - 1 - - 1 1 CO8 L4
12 R-2R DAC 03 - - 1 - - 1 1 CO9 L4
13 SAR based ADC 03 - - - - - - 1 CO10 L4
- Total 39 5 4 3 5 4 3 13 - -
Note: Write CO based on the theory course.

2. Continuous Internal Assessment (CIA)

Evaluation Weightage in Marks CO Levels
CIA Exam – 1 15 CO1, CO2, CO3, L4, L4,L4,L4,L4
CO4,CO5
CIA Exam – 2 15 CO6, CO7, L4,L4
CIA Exam – 3 15 CO8, CO9, CO10 L4, L4, L4

Assignment - 1 05 CO1, CO2, CO3, L4, L4,L4,L4,L4

CO4,CO5
Assignment - 2 05 CO6, CO7, L4,L4
Assignment - 3 05 CO8, CO9, CO10 L4, L4, L4

Other Activities – define CO1 to CO10 L4

– Slip test
Final CIA Marks 0 - -
-
SNo Description Marks
1 Observation and Weekly Laboratory Activities 04 Marks
2 Record Writing 08 Marks for each Expt
3 Internal Exam Assessment 08 Marks
4 Internal Assessment 20 Marks
5 SEE 80 Marks
- Total 100 Marks

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D. EXPERIMENTS
Experiment 01 :
- Experiment No.: 1 Marks Date Date
Planned Conducte
d
1 Title Inverter
2 Course Outcomes Simulate and synthesize basic VLSI circuits using Verilog coding
3 Aim To write the verilog code for CMOS Inverter and write the test bench for
the same to verify and observe the waveform.
4 Material / Lab Manual
Equipment Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

• Symbol

8 Observation Table, Truth Table

Look-up Table, •
Output •
•

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9 Sample Calculations • -
10 Graphs, Outputs

11 Results & Analysis • The CMOS Inverter has been successfully simulated and verified.
12 Application Areas • Static RAM, Image sensors
13 Remarks
14 Faculty Signature
with Date

Experiment 02 : Buffer

- Experiment No.: 2 Marks Date Date

Planned Conducte
d
1 Title Buffer
2 Course Outcomes Simulate and synthesize basic VLSI circuits using Verilog coding
3 Aim To write the verilog code for CMOS Buffer and write the test bench for the
same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop

7 Block, Circuit, • Circuit Diagram

Model Diagram,
Reaction Equation,
Expected Graph

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• Symbol

8 Observation Table, Truth Table

Look-up Table,
Output

9 Sample • -
Calculations
10 Graphs, Outputs

11 Results & Analysis • The CMOS Buffer has been successfully simulated and verified.
12 Application Areas • Static RAM, Image sensors
13 Remarks
14 Faculty Signature
with Date

Experiment 03 : Transmission Gate

- Experiment No.: 3 Marks Date Date

Planned Conducte
d
1 Title Transmission Gate
2 Course Outcomes Simulate and synthesize basic VLSI circuits using Verilog coding
3 Aim To write the verilog code for CMOS Transmission Gate and write the test
bench for the same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept

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6 Procedure, • step 1: start

Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop

7 Block, Circuit, • Circuit Diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table, Truth Table

Look-up Table,
Output

9 Sample • -
Calculations

10 Graphs, Outputs

11 Results & Analysis • The CMOS TG has been successfully simulated and verified.
12 Application Areas • Static RAM, Image sensors
13 Remarks
14 Faculty Signature
with Date
Experiment 04 : Logic Gates

- Experiment No.: 4 Marks Date Date

Planned Conducte

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d
1 Title Logic Gates
2 Course Outcomes Simulate and synthesize Logic gate circuits using Verilog coding
3 Aim To write the verilog code for CMOS Logic Gates and write the test bench
for the same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop

7 Block, Circuit, • Circuit Diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table, Truth Table

Look-up Table,
Output

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9 Sample • -
Calculations
10 Graphs, Outputs

11 Results & Analysis • The CMOS Logic gate circuit has been successfully simulated and
verified.
12 Application Areas • Alarm switch, Temperature detector, Door bell switch
13 Remarks
14 Faculty Signature
with Date

Experiment 05 : S-R Flip Flop

- Experiment No.: 5 Marks Date Date

Planned Conducte
d
1 Title S-R Flip flop
2 Course Outcomes Simulate and synthesize flip-flop using Verilog coding
3 Aim To write the verilog code for S-R Flip flop and write the test bench for the
same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.

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• Step 8: Simulate Behavioral Model

• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table, Truth Table

Look-up Table,
Output

9 Sample • -
Calculations
10 Graphs, Outputs

11 Results & Analysis • SR Flip-flop circuit has been successfully simulated and verified.
12 Application Areas • Data storage, data trasfer, registers, counters, frequency division
13 Remarks
14 Faculty Signature
with Date

Experiment 06 : D Flip Flop

- Experiment No.: 6 Marks Date Date

Planned Conducte
d

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1 Title D Flip flop

2 Course Outcomes Simulate and synthesize flip-flop using Verilog coding
3 Aim To write the verilog code for D Flip flop and write the test bench for the
same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table, Truth Table

Look-up Table,
Output

9 Sample • -
Calculations
10 Graphs, Outputs

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11 Results & Analysis • D Flip-flop circuit has been successfully simulated and verified.
12 Application Areas • Data storage, data trasfer, registers, counters, frequency division
13 Remarks
14 Faculty Signature
with Date

Experiment 07 : T Flip Flop

- Experiment No.: 7 Marks Date Date

Planned Conducte
d
1 Title T Flip flop
2 Course Outcomes Simulate and synthesize flip-flop using Verilog coding
3 Aim To write the verilog code for T Flip flop and write the test bench for the
same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table, Truth Table

Look-up Table,
Output

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9 Sample • -
Calculations
10 Graphs, Outputs

11 Results & Analysis • T Flip-flop circuit has been successfully simulated and verified.
12 Application Areas • Data storage, data trasfer, registers, counters, frequency division
13 Remarks
14 Faculty Signature
with Date

Experiment 08 : JK Flip Flop

- Experiment No.: 8 Marks Date Date

Planned Conducte
d
1 Title JK Flip flop
2 Course Outcomes Simulate and synthesize flip-flop using Verilog coding
3 Aim To write the verilog code for JK Flip flop and write the test bench for the
same to verify and observe the waveform.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop

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7 Block, Circuit, • Circuit Diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table, Truth Table

Look-up Table,
Output

9 Sample • -
Calculations
10 Graphs, Outputs

11 Results & Analysis • JK Flip-flop circuit has been successfully simulated and verified.
12 Application Areas • Data storage, data trasfer, registers, counters, frequency division
13 Remarks
14 Faculty Signature
with Date

Experiment 09 : Parallel Adder

- Experiment No.: 9 Marks Date Date

Planned Conducte
d
1 Title Parallel Adder
2 Course Outcomes Simulate and synthesize adders and counters using Verilog coding
3 Aim To write the verilog code for parallel adder write the test bench for the
same to verify and observe the waveform and synthesize the code.
4 Material /Lab Manual

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Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output
Sample CASE 1: if A=1001 and B =0011 CASE 2: if A=1001 and B
Calculations =0111

1001 1001
+ 0011 + 0111
1100 S3 S2 S1 S0 1 0000
Cout S3 S2 S1 S0

10 Graphs, Outputs

11 Results & Analysis • Parallel Adder circuit has been successfully simulated and verified.
12 Application Areas • Designing ALU, Fast multipilers, Digital clocks, Multiplexing, Parallel

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to serial data conversion

13 Remarks
14 Faculty Signature
with Date

Experiment 10 : Serial Adder

- Experiment No.: 10 Marks Date Date
Planned Conducte
d
1 Title Serial Adder
2 Course Outcomes Simulate and synthesize adders and counters using Verilog coding
3 Aim To write the verilog code for serial adder write the test bench for the same
to verify and observe the waveform and synthesize the code.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,

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Output
Sample
Calculations
10 Graphs, Outputs

11 Results & Analysis • Serial Adder circuit has been successfully simulated and verified.
12 Application Areas • Designing ALU, Fast multipilers, Digital clocks, Multiplexing, Parallel
to serial data conversion
13 Remarks
14 Faculty Signature
with Date
Experiment 11 :4-bit Asynchronous Counter

- Experiment No.: 11 Marks Date Date

Planned Conducte
d
1 Title Asynchronous Counter
2 Course Outcomes Simulate and synthesize adders and counters using Verilog coding
3 Aim To write the verilog code for asynchronous counter write the test bench for
the same to verify and observe the waveform and synthesize the code.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop

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7 Block, Circuit, • Circuit Diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output
9 Sample
Calculations
10 Graphs, Outputs

11 Results & Analysis • Asynchronous counter circuit has been successfully simulated and
verified.
12 Application Areas • Designing ALU, Fast multipilers, Digital clocks, Multiplexing, Parallel
to serial data conversion
13 Remarks
14 Faculty Signature
with Date

Experiment 12 :4-bit synchronous Counter

- Experiment No.: 12 Marks Date Date

Planned Conducte
d
1 Title Synchronous Counter
2 Course Outcomes Simulate and synthesize adders and counters using Verilog coding
3 Aim To write the verilog code for synchronous counter write the test bench for
the same to verify and observe the waveform and synthesize the code.
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of verilog programming to writing the verilog program
Principle, Concept

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6 Procedure, • step 1: start

Program, Activity, • step 2: Double click on Xilinx ISE 9.2i
Algorithm, Pseudo • step 3: File->New Project.
Code • step 4: Write the verilog code
• step 5:check Syntax.
• step 6: if error then correct the errors
• step 7: Write the Test Bench program.
• Step 8: Simulate Behavioral Model
• Step 9: Wave Form will be displayed
• step 10:stop
7 Block, Circuit, • Circuit Diagram
Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output
9 Sample
Calculations
10 Graphs, Outputs

11 Results & Analysis • synchronous counter circuit has been successfully simulated and
verified.
12 Application Areas • Designing ALU, Fast multipilers, Digital clocks, Multiplexing, Parallel
to serial data conversion
13 Remarks
14 Faculty Signature
with Date

Experiment 13 :CMOS INVERTER

- Experiment No.: 13 Marks Date Date

Planned Conducte

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d
1 Title CMOS INVERTER
2 Course Outcomes Design CMOS Inverter schematic , Layout and verify LVS.
3 Aim Design an Inverter with given specification, complete design flow mentioned
below.
a. Draw the schematic and verify the following.
i)DC Analysis.
ii)Transient Analysis.
b) Draw the Layout and verify the DRC, ERC
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of CMOS circuits to design the given circuit
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on S-edit
Algorithm, Pseudo • step 3: File->New
Code • step 4: Draw the circuit
• step 5: Check for DRC and ERC errors.
• step 6: Save and minimize
• step 7: Open T-spice.
• Step 8: File->New
• Step 9: Write the t-spice code and run the code, observe the
waveform
• step 10:stop
7 Block, Circuit, • Circuit Diagram and Layout diagram
Model Diagram,
Reaction Equation,
Expected Graph

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8 Observation Table,
Look-up Table,
Output

9 Sample
Calculations
10 Graphs, Outputs

11 Results & Analysis • The schematic and layout for the Inverter is successfully verified and
tested.
12 Application Areas • Data converters, Transceivers
13 Remarks
14 Faculty Signature
with Date

Experiment 14 :Single Stage Differential amplifier

- Experiment No.: 14 Marks Date Date

Planned Conducte
d
1 Title Single Stage Differential amplifier
2 Course Outcomes Design Single Stage Differential amplifier schematic , Layout and verify LVS.
3 Aim Design an Single Stage Differential amplifier with given specification,
complete design flow mentioned below.
a. Draw the schematic and verify the following.
i)DC Analysis.
ii)AC Analysis.
b) Draw the Layout and verify the DRC, ERC
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula,Basic structure of CMOS circuits to design the given circuit

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Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on S-edit
Algorithm, Pseudo • step 3: File->New
Code • step 4: Draw the circuit
• step 5: Check for DRC and ERC errors.
• step 6: Save and minimize
• step 7: Open T-spice.
• Step 8: File->New
• Step 9: Write the t-spice code and run the code, observe the
waveform
• step 10:stop

7 Block, Circuit, • Circuit Diagram and Layout diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output

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9 Sample
Calculations
10 Graphs, Outputs

11 Results & Analysis • The schematic and layout for the Single stage differential amplifier
is successfully verified and tested.
12 Application Areas • FET, Oscilloscopes, Electronic voltmeters, operational aplifiers
13 Remarks
14 Faculty Signature
with Date

Experiment 15 :Comon Source Differential amplifier

- Experiment No.: 15 Marks Date Date

Planned Conducte
d
1 Title Common source differential amplifier
2 Course Outcomes Design common source differential amplifier schematic , Layout and verify
LVS.
3 Aim Design an Common Source Differential amplifier with given specification,
complete design flow mentioned below.
a. Draw the schematic and verify the following.
i)DC Analysis.
ii)AC Analysis.
b) Draw the Layout and verify the DRC, ERC
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of CMOS circuits to design the given circuit
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on S-edit
Algorithm, Pseudo • step 3: File->New

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Code • step 4: Draw the circuit

• step 5: Check for DRC and ERC errors.
• step 6: Save and minimize
• step 7: Open T-spice.
• Step 8: File->New
• Step 9: Write the t-spice code and run the code, observe the
waveform
• step 10:stop

7 Block, Circuit, • Circuit Diagram and Layout diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output
9 Sample

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Calculations
10 Graphs, Outputs

11 Results & Analysis • The schematic and layout for the common source differential
amplifier is successfully verified and tested.
12 Application Areas • FET, Oscilloscopes, Electronic voltmeters, operational aplifiers
13 Remarks
14 Faculty Signature
with Date

Experiment 16 :Comon Drain Differential amplifier

- Experiment No.: 16 Marks Date Date

Planned Conducte
d
1 Title Common drain differential amplifier
2 Course Outcomes Design common drain differential amplifier schematic , Layout and verify
LVS.
3 Aim Design an Common Drain Differential amplifier with given specification,
complete design flow mentioned below.
a. Draw the schematic and verify the following.
i)DC Analysis.
ii)AC Analysis.
b) Draw the Layout and verify the DRC, ERC
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of CMOS circuits to design the given circuit
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on S-edit
Algorithm, Pseudo • step 3: File->New
Code • step 4: Draw the circuit

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• step 5: Check for DRC and ERC errors.

• step 6: Save and minimize
• step 7: Open T-spice.
• Step 8: File->New
• Step 9: Write the t-spice code and run the code, observe the
waveform
• step 10:stop

7 Block, Circuit, • Circuit Diagram and Layout diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output
9 Sample
Calculations
10 Graphs, Outputs

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11 Results & Analysis • The schematic and layout for the common drain differential amplifier
is successfully verified and tested.
12 Application Areas • FET, Oscilloscopes, Electronic voltmeters, operational aplifiers
13 Remarks
14 Faculty Signature
with Date

Experiment 17 :R-2R DAC

- Experiment No.: 17 Marks Date Date

Planned Conducte
d
1 Title R-2R DAC
2 Course Outcomes Design R-2R DAC schematic , Layout and verify LVS.
3 Aim Design an R-2R DAC with given specification, complete design flow
mentioned below.
a. Draw the schematic and verify the following.
i)DC Analysis.
ii)AC Analysis.
b) Draw the Layout and verify the DRC, ERC
4 Material / Lab Manual
Equipment
Required
5 Theory, Formula, Basic structure of CMOS circuits to design the given circuit
Principle, Concept
6 Procedure, • step 1: start
Program, Activity, • step 2: Double click on S-edit
Algorithm, Pseudo • step 3: File->New
Code • step 4: Draw the circuit
• step 5: Check for DRC and ERC errors.
• step 6: Save and minimize
• step 7: Open T-spice.
• Step 8: File->New

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• Step 9: Write the t-spice code and run the code, observe the
waveform
• step 10:stop

7 Block, Circuit, • Circuit Diagram and Layout diagram

Model Diagram,
Reaction Equation,
Expected Graph

8 Observation Table,
Look-up Table,
Output
9 Sample
Calculations
10 Graphs, Outputs

11 Results & Analysis • The schematic and layout for the R-2R DAC is successfully verified

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and tested.
12 Application Areas • Motor control, digital potentiometers, Software Radio, Data
distribution system
13 Remarks
14 Faculty Signature
with Date

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