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ADLD&CO Lab Questions With Scheme of Evaluation

The document outlines the lab experiments for the Applied Logic Design & Computer Organization course at RV College of Engineering, detailing tasks such as the realization of various digital circuits using specific integrated circuits. It includes a section for demonstration and machine coding of a 4-bit CPU using the LOGISIM simulator, specifying the components and instructions to be implemented. Additionally, it provides a scheme of evaluation for the lab work, including marks distribution for viva, write-up, execution, and demonstration.

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34 views2 pages

ADLD&CO Lab Questions With Scheme of Evaluation

The document outlines the lab experiments for the Applied Logic Design & Computer Organization course at RV College of Engineering, detailing tasks such as the realization of various digital circuits using specific integrated circuits. It includes a section for demonstration and machine coding of a 4-bit CPU using the LOGISIM simulator, specifying the components and instructions to be implemented. Additionally, it provides a scheme of evaluation for the lab work, including marks distribution for viva, write-up, execution, and demonstration.

Uploaded by

meharkulkarni0056
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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RV College of Engineering

Department of Computer Science & Engineering

Applied Logic Design & Computer Organization (CS234AI)

Part A : Lab Experiments [30 Marks]

Sl.
Lab Questions
No.
Realization of Excess-3 Code converter with Parallel Adder and
1.
Subtractor using IC – 7483.
2. Realization of Full Adder and Full Subtractor using IC 74153.
Design and Realization of One Bit Magnitude Comparator using Basic
3 A.
Gates
B. Realization of decade counter 0 to 9 using IC 7490.

4 A. Realization of Binary to Gray Code Converter using IC 74139

Realization of Decoder using IC-7447 and Realization of Encoder


B.
using IC-74147
5 Realization of Master-Slave J K Flip-Flop using NAND gates.
6 Realization of Up and Down Programmable Counter using IC74192

Part B (Demonstration and machine coding) [20 Marks]

Demonstration of a 4 bit CPU using the LOGISIM simulator, for the following
specifications and Machine code the given program and run the program on simulator.
1. Program Counter (Assume 256 program/code memory)
2. Instruction Register (Assume instruction size as 16 bit)
3. General Purpose Registers (RISC type-R0-R7):
4. ALU (to support 4-bit integer arithmetic operations & 4-bit logical operations)
5. Memory – 1024 ROM (to store instructions of size 16 bit)
6. Implement the following instructions namely: MOV, ADD, AND, OR, XOR
7. Result to be displayed on 7‐segment displays / reg tab of LOGISIM

1 MOV #5, R0 2 MOV #3, R1 3 MOV #4, R1 4 MOV #a, RØ


. MOV #4, R1 MOV #2, R2 MOV #8, R2 MOV #b, R1
MOV #A, R2 ADD R1,R2,R4 ADD R1,R2,R3 ADD RØ,R1,R7
ADD R0,R1,R3 ADD R1,R2,R5 XOR R1,R2,R4 AND RØ,R1,R3
AND R3,R2,R4 OR R1,R2,R6 AND R1,R2,R6 XOR R0,R1,R2
RV College of Engineering
Department of Computer Science & Engineering

Scheme of Evaluation
Description Marks
Viva 10 Marks
Part A for 20 Marks
Split-up as follows
Write -up 5 Marks
Execution 15 Marks
Part B for 20 Marks
Split-up as follows
Write -up 5 Marks
Demo 15 Marks

Signature of Lab Incharge Signature of HOD

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