International Journal of Recent Technology and Engineering (IJRTE)

ISSN: 2277-3878, Volume-3, Issue-1, March 2014

The Comparative Study of FPGA based FIR Filter

Design Using Optimized Convolution Method and
Overlap Save Method
Gargi Roy, Madhumita Mukherjee

Abstract— This paper describes a comparative study of We have designed low pass FIR filter using MATLAB FDA
designing digital filter of long duration sequences. Here we have tool. Here we have developed overlap save method structure
adopted the approach of block filtering scheme “overlap save and optimized linear convolution method of designing
method” and compare with the optimized linear convolution digital filter and synthesized this structure using Xilinx ISE
scheme for designing digital filter. We have implemented both
13.4 synthesis tool and implemented in Spartan 3A. In our
methods in FPGA Spartan 3A starter kit, XC3S700A device.
Implementing both algorithms in FPGA hardware platform paper we have proposed that the long input sequences can
reveals that there is a 67% area reduction and 70.6% increase in be processed using optimized overlap save method
operating frequency in overlap save method compare to optimize technique of designing digital filter. This technique leads to
convolution method. In addition the power utilization summary reduction in the critical path, power consumption and at the
reveals that there is a 24.24% increased in the power utilization same time it increases the clock frequency in comparison to
of overlap save method. Thus the experimental results shows that optimized linear convolution method of designing digital
to design an area optimized , high speed digital filter we should filter. The rest of the paper is MATLAB FDA tool is shown
used overlap save method where as for a power efficient digital in section 2.The FPGA implementation of overlap save
filter we should used optimized linear convolution method.
method structure is given in section 3. The FPGA
Index Terms— FIR,MATLAB, Linear convolution. implementation of linear convolution structure is shown in
section 4.section 5 contains the comparative study and
I. INTRODUCTION calculation of noise variance. Section 6 contains the
conclusion.
Digital signal processing has a broad application in the field
of real time signal processing operation such as speech II. DESIGN OF FIR FILTER USING MATLAB FDA
processing, Audio Compression, Digital Image Processing,
For signal processing operation finite impulse response
radar signal processing and different media applications[1].
(FIR) filter plays an important role, these are the digital
These computation intensive real time applications requires
filter that computes the output response as the weighted,
digital filter to perform the signal processing operation. A
finite term-sum of past, present and future values of the
digital filter is an important class of linear time invariant
filter input as given in equation (2)[3].
system (LTI) that performs on a sample discrete time signal
to reduce or enhanced certain aspect of that signal[2]. In this
paper we focus on designing low pass FIR filter using the
overlap save method technique. The general form of digital
filter difference equation is given below in equation (1)[2]. Where M1, M2 are finite. In this paper we will design a
causal FIR (finite impulse response) filter; the difference
equation is given as below in equation (3) .

Where Y(n) is the current filter outputs, the Y(n-k)’s are

current or previous filter inputs, the aK’s are the filter’s feed
forward co-efficient corresponding to the zeros of the filter, Where M is finite. To design this low pass digital filter, we
the bK’s are the filter’s feedback co-efficient corresponding will use MATLAB FDA as the synthesis tool; the
to the pole of the filter, and N is the filter’s order. specification of the filter is shown in the table I. Depending
Depending upon the filter co-efficient there are two type of upon the specification, we will have the transfer function co-
digital filter, frequency selective and adaptive digital filter. efficient as shown in the table II. The difference equation of
the FIR filter is given in equation (4)

The magnitude and phase plot of this filter is shown in the

Manuscript received March 2014 figure (1). We have adapted the rectangular window method
Gargi Roy, Received B.Tech degree from IERCEM Institute Of
Information Technology (West Bengal University of technology) in 2012 to design the filter in MATLAB FDA tool[4]. The truncated
and pursuing M.Tech from Heritage Institute of technology West Bengal, impulse response of the filter after passing through the
India. rectangular window is given in equation (5)
Madhumita Mukherjee, Received B.Tech degree form West Bengal
University of Technology in 2007 and M.Tech form Jadavpur University in
2011 respectively. she is currently Assistant Professor in department of Where
Electronics and Telecommunication on Heritage Institute of Technology
under West Bengal, India.

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 The Comparative Study of FPGA based FIR Filter Design Using Optimized Convolution Method and Overlap Save
Method

Fig.1. Magnitude and Phase plot of the FIR filter

In frequency domain, we can represent this truncated Thus in this paper we will design over FIR digital filter
impulse response is shown in the equation (6). using an optimized, computation effective algorithm of
overlap-save method.
In this method we consider the input data having the length
L & the impulse response having the length M. the block
Table I length of the input data should have the size N=L+M-1[6,7]
Properties Specification . Thus the block of data sequences is given by,
response low pass
order 2nd
table Yes
window rectangular window
cut-off frequency (wc ) 0.198
attenuation at cut-off 6 db
frequency

Table II
Transfer function Co-efficient
h(0) 0.325996
h(1) 0.3480081 The response of the FIR filter is now computed by the
h(2) 0.325996 circular convolution method [8]:

III. IMPLEMENTATION OF FIR FILTER USING Yi(n)= Xi(n) h(n) (10)

OVELAP SAVE METHOD
In order to generate the output response y (n) of a digital By putting the value of i we obtain the equation given
filter, we have to perform the linear convolution between the bellow:
input sequence & the impulse response. If a long duration
input sequence is to be processed then the convolution Y1(n)=
results more hardware utilization as well as higher
computation time delay ,therefore an effective way of
processing the long duration data is to break into blocks and Y2(n)=
process by circular convolution[4] . In the last stage these The final output response,
blocks of circular convoluted data are to be processed and
is the impulse response of the causal FIR filter. by
two methods- overlap save method and overlap add method
.In this two method while computing the data the circuit
diagram of overlap add method requires more hardware
components in comparison to overlap save method .

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 International Journal of Recent Technology and Engineering (IJRTE)
ISSN: 2277-3878, Volume-3, Issue-1, March 2014

Fig. 2. Circuit diagram of the overlap save structure

A. Simulation results
A. FPGA based design of the overlap save method
We have design our structure using VHDL language and
algorithm
implemented in spartan 3A, starter kit,device
In order to design the architechere of overlap save method XC3S700A.The simulation results of the overlap save
we will divide over structure into two parts – controller and method with different blocks of the input is shown in the
data path.we have used the approach of finite state machine figure(4a) and figure(4b).The table III shows the simulated
for the design of controller part, the input of the controller output results exact valuer,its approaxmiate values and error
part is the input data sequence and the output is the blocks generated due to approaximation.The figure (3) shows the
of data sequences. Thus the FSM controller will divide the plot of the input samples vs error in order to calculate the
long duration input sequence into a fixed block size given variance of output noise.From the error vs sample plot we
by the equation (7), eqation (8) and eqation (10). The output find that as the number of sample increases with each
of the controller is attached with data path as shown in the iteration, error also increases linearly.
diagram figure(2). The data path is again divided into two
sub blocks. The first subblocks is nothing but a ring counter Variance output noise [2] (15)
that produce a impulse response as required during the
B. Device utilization
computation of the circular convolution as shown in the
diagram figure(2).The second subblock consists of We have implemented the structure in spartam-3A starter kit
multipliers and adders that requires during computation of in the device XC3S700A.The device utilization summary ,
the circular convolution.we have used 8 bit array multiplier the maximum computation path delay & the power
and 8 bit ripple carry adder to perform the fast computation utilization of this structure is given in the table below (IV )
of the input sequence .The output of these second subblocks
is connected to a shift register as shown in the diagram ERROR PLOT
figure(2).These serial shift register is used to implement the
0.15
overlap save method.From the five output response of each
0.1
error

serial shifted data we will discard the left most output

response as given in the equation(14). 0.05
0
Y1(n)= X1(n) h(n) 1 2 3 4 5 6 7 8 9

= sample

Fig.3. Sample versus Error plot

Thus the final output block will starts from the output 3

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The Comparative Study of FPGA based FIR Filter Design Using Optimized Convolution Method and Overlap Save
Method

Table III

Input Actual value of Approximate value Deviation(y-x) Binary equivalent

sequence output sequence(y) of value of output
output sequence (x)
1.0 0.325996 0.3203125 0.0056835 000000000.0101001
2.0 1.0000001 0.984375 0.0156251 000000000.1111110
3.0 2.0000002 1.96875 0.03125 000000001.1111100
4.0 3.0000003 2.953125 0.0468753 000000010.1111010
5.0 4.0000004 3.9375 0.0625004 000000011.1111000
6.0 5.0000005 4.921875 0.0781255 000000100.1110110
7.0 6.0000006 5.90625 0.0937506 000000101.1110100
8.0 7.0000007 6.890625 0.1093757 000000110.1110010
9.0 8.0000008 7.875 0.1250008 000000111.1110000
0 5.7400409 5.65625 0.0837909 000000010.1010100
0 2.933964 2.8828125 0.0511515 000000010.1110001

Table IV

Logic device utilization Path delay and frequency required to Power utilization (w)
summary implement the circuit
Total Number of 180 Minimum period 27.100ns Total 0.041
slices register power
Number of slice 140 Maximum Frequency 36.900MHz Dynamic 0.009
flip flops power

Number of 4 input 1167 Minimum input arrival 5.815ns Quiescent 0.032

LUTs time before clock power

Number of used 40 Maximum output required 5.668ns

latches time after clock - -

Fig. 4a. Simulation waveform of overlap save structure when select line (s =’00’)

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 International Journal of Recent Technology and Engineering (IJRTE)
ISSN: 2277-3878, Volume-3, Issue-1, March 2014

Fig. 4b. Simulation waveform of overlap save structure when select lines (s=’01’)

IV OPTIMIZED LINEAR CONVOLUTION METHOD The simulation results of the linear convolution with
To perform the signal processing operation, we have to different inputs are shown in the figure(6a) and the output
study the impulse response of a system. In DSP system response is shown in the figure(6b).
convolution is a mathematical tool for the study of the B. Device utilization
output response of a system. Thus we can find the output We have implemented the structure in Spartan 3A starter kit
response of a linear time invariant system by using the in the device XC3S700A.The device utilization summary
technique of convolution[9]. the maximum computation path delay & the power
utilization of this structure is given in the table below (VI)

This equation (16) is denoted by, Table V

p0 p1 s0 s1 s2 s3 t0 t1 t2 t3 t4 u0 u1 u2 u3 Fina
l
outp
Here x(n) is the input sequences, h(n) is the impulse ut
response & y(n) is the output sequences. In this paper we 0 0 0 0 0 0 0 0 0 0 0 - Y0
have designed a low pass FIR filter using overlap-save 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 Y1
method, now we will verify the output response of the 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 Y2
system using the optimized convolution circuit. 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 Y3
In this circuit we have used an only one array multiplier and 1 0 0 0 1 0 0 1 0 1 1 0 1 1 0 Y4
a ripple carry adder with array of multiplexer as a switching 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 Y5
element to generate the output respons of the FIR low pass 1 0 0 1 0 0 0 0 1 0 0 1 0 1 0 Y6
filter. 1 0 0 1 0 1 1 0 1 1 1 1 1 0 0 Y7
The proposed architecture is divided into two blocks: one 1 0 0 1 1 0 1 1 0 1 0 1 1 1 0 Y8
for input sequences analysis and another for the generation 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 Y9
1 0 1 0 0 0 1 1 1 0 1 - Y10
for the output sequences. In this paper input circuit
depending upon the control signal the input sequences
multiplied with the impluse response in order to generate the
intermidiate sequences. In the output circuit,the intermidiate
signals are added as shown in the figure(5b) to produced the
final output results. According to the table V generarion of
output response for the various combination of control lines
are shown below.
A. Simulation result
We have design our structure using VHDL language and
implemented in spartan 3A starter kit,device.

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The Comparative Study of FPGA based FIR Filter Design Using Optimized Convolution Method and Overlap Save
Method

Fig.5a. input circuit diagram of linear the convolution structure

Fig.5b. output circuit diagram of linear the convolution structure

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 International Journal of Recent Technology and Engineering (IJRTE)
ISSN: 2277-3878, Volume-3, Issue-1, March 2014

Fig.6b. Output waveform of the linear convolution structure

Fig.6a. Input waveform of the linear convolution structure

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 The Comparative Study of FPGA based FIR Filter Design Using Optimized Convolution Method and Overlap Save
Method

V COMPARATIVE STUDY Madhumita Mukherjee

Received B.Tech degree form West Bengal
The comparative study between the optimized convolution University of Technology in 2007 and
method and overlap save method shows that there is a 67% M.Tech form Jadavpur University in 2011
respectively. she is currently Assistant
area reduction, 70.6% increase in operating frequency of Professor in department of Electronics and
overlap save method in comparison to linear convolution Telecommunication on Heritage Institute of
method .Thus for a area efficient high speed application we Technology under West Bengal University of
Technology. Her research interest include
can prefer overlap save method but as the overlap save embedded system , Digital signal processing
method structure used sequential logic for the operation thus and VLSI architecture.
the dynamic power consumption for this circuit is higher
than optimized linear convolution method, thus to design a
low power structure of a filter we will prefer optimized
linear convolution structure.

VI CONCLUSION
This paper has presented a comparative study of a designing
FIR filter of long duration sequences using both optimized
convolution method and overlap save method. The FPGA
implementation results shows that for a area optimized, high
speed FIR filter design application we can preferred overlap
save method. But for a low power FIR filter design
application we can preferred optimized linear convolution
method

REFERENCES

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Gargi Roy

Received B.Tech degree from IERCEM

Institute Of Information Technology (West
Bengal
University of technology) in 2012 and
pursuing M.Tech from Heritage Institute of
technology(West Bengal University Of
Technology). Her research interest include
embedded system , Digital signal processing
and VLSI architecture.

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