Op-am-P Applications

6.1 :· Realistic Stmpllfylng Assumptions

. .
Q.1 Explain virtual ground and virtual sh!)rt concept.
-~ (SPPU 1. May-08,11, Dec.•09,11,13,15, Marks I)
Ans. : • : The virtual ground means
the differential input voltage Vd .
between the noninverting and inverting input terminals is essentially zero.
• Even if outp~t voltage is few .voltl, due ~ Jarae open loop pm of
op-amp, the difference voltage ~ at 1btl
. : ~ . ,
~=\'cs AoL J.~. \a - ....:a... -
. - AoL
•·• - V2 )' = 0
vd = (Vi i.e. ,
• Thus we c~ say . that under ttDe11lf0

shon circuit between .~ e two

voltages are same. ~
• The Fig.·Q.1.1 shows the
concept of the virtual
gro~d. The thick line
'r. . indicates the virtual short
circuit betwe·en the input
terminals.
-
~ ~

·_i !
• Now if . the ~on-~verting Fig. Q.1.1 Concept of vi~ ·
· terminal is grounded, by · . . • 8f"Ound
1
the concept of virtual short, the _inverting t ~ is also at -.
potential, though th~e is n~ p~ys1cal connection between the i n ~
terminal and the groun~ This ts th.e prindple of vi~uaJ crouad. ertifta
lmporta~t Points to Remember
• The two realistic simplifyin~ assump~~ns are,
1. The op-amp input current is al~ays zero.
. .
1.
 I
,r/C C/rcu/11 . 6• 2 ,v

~ i·~p~·t. ,~;;1~·~·i·~. . ~F~;:;~;. . ~~;•. ·;,·... . . . . . . . . . . . . ..~~.~.~.~.'.~. ~~~~~~:~~:.: El•ctro,elc Clrculu· 6-J Op-•'"P Appllu&l,u

' }-Jenee if one input tenninal i ways at the same potential.

• Now from the output side, · considerina the direction of curtent I we can
/ tc be virtually it"O~ ~ ground~d then other can be .
958 umcd
virt1.1al groun d. . n ed. This is called concept of write,
1
8 tepa to Analyae . ... (Q.2.2)
O
. 51,p 1 : Input .;urrent of the ideal P•amp Circuit.
/ ihc current distribution in the circuit ~P-amp i1 alway1 zero. Using this
T I · • 1 to be obtaincp ' •. E~tire current I pa11c1 throu~ Rr as op-amp input current is zero.
1
, St•P 2 : he nput tcnnlnali of th
· I. Thus 1·f one Is grounded
poten1111
virtually grounded. This is called '
th
.
·
e 0 P·arnp
· •.
arc a1way1 at the same
c ~t~cr can be treated to be
• Equatina, equatiom (Q.~.1) and. (Q.2.2) we get, i:.•.- ~f

1~-
. fi concept of v'rtual
1 .
the expres51ons or varic;ms bran~h ground. From this, V. Rr .
current, can be obt . d ....:2... • - - (Gain with feedback) •.. (Q~.3)
I St•P 3 : Analy7.i ng .the Varlou .
I
. . a1ne . Vin . R1 .
1
unwanted vann · bl es, the output exp expressions i O b. ,
tained, eliminating •
/ parameters can be obtained.
, , ; r~s~ on in t~nn• inp\d\and circuit
- ' ................ .
..................... ... .............. ~ .. ...............................................................: ......·................:... .............. . _._
• The ~. is.· the
l.
pin of the. amplifier while neptive ·,ign indi~ that
the polarity of output ii oppoaite to ·that of. input. Hence it ii called
. : Ideal Inverting Amplifier inverting amplifier. : · • ·
Q.2 DrHW the lnvertlna Rll\pllflcr u1ln1
esprmlon for its voltaae aatn. · . op-amp and derl,:e the 6.3 : Ideal No
Ana. 1 The inverting amplifier using ·op am
. p. i h. •· · Q.3 D~aw the · .nonln~ertlaj
. ·· • .s own m the Fig. Q.2.1.
expre11lon for lta .voltaae p1a.
+ R,
Ana. : · The · non-invertina
Fig. Q.3.1. .
• The· input is
applied · to the
noninverting input
terminal of the -::-
op-~p . .
• The node B is at
Fig. Q.2.1 Inverting amplifier potential °½n ,
hence the
As node B is grounded, node A is·,,·~lso .at gr<>Wld potential, . from · the potential of point
concept or'virtual ground, so VA • O. A is same as • B
V: . i . which · lS . ,·~ Fig. Q.3.1 Non-lnvertt- . . . . . .
.-!!!. ... ... (Q.i.1) ''\ . ' . Yjn, '"W

R1 .. from the conc~pt tif virtual short. .

VA • Va• '\'in
... (Q.3.1)
r Electronic Circ"its

. .
• From the output side we can wnte, I
6-4

- VA
=~
Vo
•
. Op-amp A.ppllclllions

Vo -
~
"\'in
Electronic Circuits . · 6-5

6.4 : Voltage Follower or Unity Gain Amplifier

-
Op-11111p AppllcMlo,,s

Q.4 Draw and explain the circuit o( unity gain amplifier usin1
. .. (Q.3.2)
.g;r (SPPU : M1y-11.u. Dec.-13. Marks_4)
op-amp.
• At the inverting terminal, I = VA - O;.. ""in ... (Q.3 .3)
R1 R1 Ans. : A circuit in which
the output voltage follows
• Entire current passes through R 1 .as input current of op-amp is zero.
the input voltage is called
• Equating equations (Q.3.2) amt (Q.3 .3), Vo - "\'in _ \'in voltage follower circuit.
- - - ·- -
Rr R1
• The voltage follower
Vo ""in + ""in i.e: . Vo ·= "'in [(R1 + Rr)] · circuit using .op-amp is
~ Rr R1 Rr R1 Rr shown in the Fig. Q.4.1.
(R 1 + Rr ) R r _ R{ Rr
· R 1 Rr - __R_1_
:+ • The node B is at
potential "'in .
• The · node A is abo at· FIIJ. QA.1 Voltage followw
Av,·,. ~- I + Rr . 1·
.•. (Q.3.4)
the same potential a B · ·
I_ ""in R1 _ i.e. Vin a c e ~ to the GC11;1Nft
• The positive sign indicates that ·there is n~ phase shift between input VA• \Za.;.v_ :
and output. • Now node A is clireedy oca111m1••111t,1
Important Points to Remembe·r . Vo = VA . .
lmp.o rtant Point Regarding Non-inverting Amplifie•r : Equating the equati~ (Q.4.1) _ .
• ·In non-inverting amplifier the input may not be applied directly to
the non-inverting terminal as ~onsidered while deriving the o~tput
I ~DI .
Vo•
· expression but it may be applied through some circuit. ·
• For this circuit, the voltap
• Let '1in is the input voltage applied to the non-inverting amplifier
• Thus the output voltage~ is
through some resistive network such that the voltage available at the
·i- i.
non-inverting input terminal is Va which is different than '½n . Then • It is also called IOIUW .
the non-inverting !lmplifier always amplifies voltage available to ampllfie_r or lsoladoa ~
its non-inverting terminal by the factor (1 + &.j. ~ence :_. '.' • Very large input resis1aDce, . of la
R1
impedance, almost zero are impadant
• Hence it can be used to. c:oanect
impedance load. u •· buffer. 1bis eJinrinlla
.· ·. . .

· A Guide f~r Engineering Studenti .

i. ~§v
r
 £/ectronlc Circuits 6-,6 , ,,
-- ,------.::=:::==
6.5 : Summing A I . .
Op-ampA l'
PP icatlons Electronic Clrculu 6-7 0/Nlfflp Alppllc,uJo~
'--_ _ _ _ _ _ _m..,:P::_::1:._ft.er or Ad . .
. . . · der Ctrc.uit
Q '5 Draw an rnvertmg summin·0• 8 Dlplifi
expression for its output
· .
. .
voltage V • •er Wi!h three i nput1.
.
.
· . Denve
-----J Q,8 Design an adder using op-amp to get output expression u : .
Vo• ._ (lV1 + 3V2 +. SV,) .
1111 . 0
•
where V., V 1 and VJ · are inputs. q- [SPPU : May-15, Mirles I)
· q-
. [SPPU : Dec.-12 M . Ani. : The -circuit of inverting adder ~
Ans, : The circuit . , . ?·14, June-22, Marks 6)
is shown in the Fig; Q.6.1.
with three inputs is
__ .,.,R,1 A R,
shown in the
fig . Q.5.1.
, As point B is
grounded, due to
virtual growid Fig. Q.8.1
concept, node A is Compare with,
also grounded h~nce
Fig'. Q.5.1 lnvartl~g summer V~ =- [2 V 1 + 3 V 2 '+:' S V 3] ... Given
v~ = V 8 = o.
From input side,
.\ RR£ = 2, ·RRf · = 3, RRf - 5 .
. . 1 2 3
l1 Ya -VA Va Choose Rr = 100 kQ, R1 - 50 IQ, Ila ~ 33.33 kO. Ra • 21 IQ
R1 =R.
1.
Vb V. .
I2 = ~· I3
.
= RC3 :
-'- 2
Q.7 _
• Applying KCL at node ·A , I == ·Ii + Ii. + 13 •.
• As op-amp input CUITcnt is ze~o •.~~ e~~-current .r passes thr~ugh Re. Ans. : ..The . circuit
diagram of subtractor is
• From output side I - VA - Vo ·• _ Vo
• · Rf . R.f shown in the Fig. Q.7.1.
. V. • To find the relation. · .
.. · I, + h + I, - Yo i.e. ·.· -~ .between thi inputs · V 1 ·+ ·
Re Rr
and. output let us use · .J:.
.Superpruition -
... (Q.5.1) principle. 'f 2 +.1.o--_- ~
• Let v',, 1 be · the
• Thus the circuit a.--nplifics the surn·: ~f the .inputs in an inverting mode. output. -wi~ input · "1
• If R, - Ri = R3 .. R then V,; • _li (Va + _V b+~] . . acting . alone,
· assuming v2· to be
• If R1 - ~• R, - Rt• R th~ ~o ~• - - ['V. +Vb +i·] zero.

A Guldefior •
E ngI.neermg
: Students
 Ekctronic Circuiu 6-8
Op-t1mp Appl/catlo,u Electronic C/rcula

• And "ai be the output, with input Vi acting. assuming Vz to be zero. [ 6. 7 , Practical Integrator I
• With V2 zero, the circuit acts as an inverting amplifier, hence we can Important Polnta to Remember
• V:: Rr u
wnte, ol = - Rj ~1 ·••• (Q.7.1)
• The ideal integrator circuit
using op-amp is ahown in
• . While with Vz as zero with Vi acting, the circuit acts as a noninvcning
the Fig. 6.1. v,,,
amplifier which amplifies the voltage at node B by the factor

(1+:; ]- • Its output ·equatio~ is,

V0 • - - -J Vin dt -;- .~(0)

1
R1Cr
• Let potential of node B be Va.
input ½ loop,
Applying voltage divjder rule to the
• where V0 (0) i9 m. comta11t
1'19. •· t ~deft• ,,,..rator circuit
of integration indicating the mitiaJ output voltage.
Rr
Va - R2 + R r "2 ... (Q.7.2) , • This circuit converts 9fCP mpuc to ramp ouq,ut_ 9q1l8re inpul to
\ triangular output and AllmOidal iapar_to CCMiDe CJUlpUt.

\1a2 = [1 + ~: ] Va ... (Q.7.3)

Q.8 What are the limff:edeN ~ ~ f a.,.. •
practical intep-ator wldl . . -
_.
• Sobstitm:ing V8 from (Q . 7.2) in (Q . 7.3) we get,
Ans. : • The inpul oflict ~

'1a1 = [1+Rf ]f.

R 1 LR2
~f
-r Rr
] V2 . :. (Q.7.4)
as an error voltage. The bias
current and adds its effect in ~
• The two componems. clue to
• HCJ.cc using Supcq:,osirion principle; '1c, = V0 1 + ¼2 ramp up
or down, dcpm:fbw
and/or bias current.
• Hence there is a poaibiJily ~
.. . (Q .7.5) voltage and it is VfflY difllalll
• Thus the output of• Mllal
likely to be offset 1DWllldl . .
• In the presence of the ' -
offset ·voltage and \'ria _ .
... (Q.7.6) output. Thus -it ii not pOllillle •
signal at the output. 0utpal was 5
error voltage. . ·
is proporti~ to the difference between the • Another limitatjon of in ideal . . . . . if Ill
• a .subtractor or difference amplifier; · small. Hence an ideal intelnt« call N . . . tr • WIJ'
range of the. ~ only.

<:ii§y
 i( Circuits 6 - 10 .
pcffd 11
dc•I Integrato r :
prlC • 1 . Electronic Clrcu/11
f!te pracnca integrato r 6-11
' circuit is shown m the Q.9 Draw the circuit of practical Integrato r alon1 with Its frequency
·
fig, Q.B. I. response and eJtplaln. · a- (SPPU : Dec.-os,10, 11,14, May-06,10, Maries I)
fhe resistance Rco~p is V1'"! Ans. : • Refer Fig.Q.8, 1 for the practical integrator circuit.
aJso used to overcom e the The expressi~n for the gain of th~ practical integrator in terms of the
errors due to the bias frequency · is· given by, · · ·
current. A _ R_ r /R1 · 1 · · · is break frequency
. 1· . f . where ' f s . • 2 1t C R (Q•9 •1)
nie resistance Rr reduces . . + Jr; f f •••

1e Jow frequency gain of . Fig. Q;i 1 p - .. . :. .. . . • . In the frequency reapome, d.c. pin remaim COftlUlllt f~ all frequenc
1e op-amp. • ia
ract1ca_l lntegrat_o r circuit less than f'a and from the frequency fa onw.-da. u frequcDcy
, == Va = 0 due to virtual ground and
I = \.'in -
R
VA
·
= '\'in
R . 12
O

~ VA - V.o
- --~
•
p-amp mput current is zero.

= _ _JL .
V.
. .

. .
Gain In d~·-.... r
increases, gain .reduces at a rate of 20 dB/decad e.

......_.
Ideal fr»egndor
3 dB down at f • fa
l l ' Rr Rr -. R 60
20 log Rf - - : - 1 - - - - - - - ~ ! - - L.
.I1 = C d (VA - Vo) , . 'dV. . · 1 40
f dt =-Cr~
20
r=r 1 +r 2 .. .' KCL ~t node .A . OdB-+ ----.--- -+-"'!" ""'!'9'9
V;n = - Vo - Cr dVo .
R1 Rr dt
g Laplace of above equan:on and negiectin g initial conditions, 10f 100f

- ~o (s) _ ~ Cr V0 (s) i.e. V0 (s) - .[ · • . . '. R JV;. (s)

,.
Rr . . sR1 c,
. .
+i!- ·f .
1
~RA
. Fig. Q.9.1 Frequenc y ·reapona e. !If the
. ery l~ge. ~ : ~ •O and can be ·neglected . ·
Rr 1s v Rr . • · At .f • 0 i.e. d.c. condition -IAI - Rr / R1 ~ .-id
. drops by 3 dB at the frequency f • .fa which is break 11:-
• - ~ " ' i n (s) i.e. Ye, (t) _;' ~ R . ~ / '1n (t) J 1 Jdt . • · For· the integratio n. the frc.q uency response must be straipt ·1M
sR1Cr .- 1 f . •... - . •
s slope -20. dB/decad e, .which is possible for the frequenci es greater t1lllllii
_ _ _ _ _ _._· J ·l. .· · fa ·and les$ than f b-~-- Thl,lS in between f'a and· fb practical integrator ICfl
as an integrator. Below .fa , integration dc;,cs not take place.
• The frequen~ ·~~~~s·c·i~ ihb~ -in .~e Fig. Q~9..1 ~-..·
• ~ Guid•forE,,gin•erlngStude11ts ·
 Op-11,np A.ppUcatlo,..
Electronic Circuirs 6 - 12 Electronic Circuits 6-JJ .
Op-amp Application~

Q.10 Design a practical integrator using - op-amp IC741C to . satisfy Q.11 Design I practical lntesrator with input signal of 2 V PP and
' 'l
the following specifications : Assume V cc • +15 V. cut off frequency of 2.5 kHz for DC volta1e 1ain of 10.
1) 3-dB cut-off frequency = 1.S kHz 2) D.c.· gain • 10 ..r [SPPU a June•Z2, May-15, Marks 6)
Sketch the frequency response of the circuit. · : · · Ans. : f - 2.S kHz
q> [SPPU : Dec.-05,12, May-09, · Marks 8)
F .
or proper integration,_f 2: 10 f 1 i.e. f 1 ··: •
f
Ans. : D.C. gain = 10, cut-off frequency fa = 1.5 kHz · · · 10
D .C. gain = ~= 10
f 2.Sx 103 • 250 Hz
R1 1 • 10
i.e. R r = 10 R 1
But r. - __1_
1 21tRrCr
f = = 1.S x 10 3
a 2n R f C f . 1 • . 4
R f Cf • 21tx 2~0 - · 6.866,c ur •.• (Q.11.1)
i.e. R f Cf = l.06lx 10---4
The d.c, gain• 10 • R.r
Choose Cf = 0.01 µ F ' R.1
R t = 10.61 kQ and R 1= i.061 kQ Rr
The designed circuit is shown in the Fig. · Q .10.1 . Choose .R.1 -
Using (Q.11.1), C,
0,0_1 µF Rc:ami, • ll1
The designed circuit is shown in
cf
10.61 kQ

■
Flo~ Q.11,1
 ,ilc Circuits 6 -14
~ . --!!!:.." '"P A.ppllcfltlon1 Electronic Clrc_ult•
_ Explain op-am p integra tor with Set
0 12
: . ~ [SPPU • . •
R. · 6-JS Op-fllnp Appllcotlo,u
un an~ Bold mode.
• Dec,.-:06, 11, Mi,y-os 12 3 • Such a three mode integrat or is very m:uch essentia
Th e circuit for three mode int .1s 1 l in the analog
•ps : ✓
" · R, ·
• egrator sh • ' • · , Marks
· · 6)
computers where the integrators arc used_ to solve
the differential
.
· own in the :Fig. Q .12.1. equatio ns 'involving initial conditions. ,
V,ef o-------"1/\/11\,---~---.J\,/_W~-- ' ~

. S2
I 6.8 : Practi cal Differ entiat or \
Run Q.13 -W hat are the limitati ons . of Ideal differ.e ntlator
Hold ? Draw and
explain the circuit of practlc al .dlffere atlator.
·
R
· . . ai- (SPPU I May 07, 01, 11, Dec,09, Marks 6)
Run
. Ans. : The litnitation1 of ideal differen tiator are,
Vin ~
---- ~.._ _.
Hold set ·
.i) ~e gain of th~ differentiator Iner ~ as
frequency incrcues. Thus· at'.
· some ·h igh freq ~, the differen tiator may become
unsiable and ~
into the !JSCillations . .
Fig. Q.12.1 l~tegr ator with 'Run, Set a~c:i ·Hold
mode
ii) There is possibil ity' that op-amp ~ go into the
1. Set mode : Keepin g the switc~ es S and s lll&Unli on.
integrator is operate d in set mode. 1 2
on the set positions, iii) The inpu~ imp'edance Xc1- . (112ff.f Ci) decnu
ea M frequency
increases. This makes the circuit very mudl ....,,
• The initial v alue of the integra tor output can be . _to tbe aaile.
set to any desired
value, within output capabi lity of the amplifier;. • These problem s can be
. ·c orrected -u sing sQme
· . addition al parame ters.
I.__v._o_l•_=_o_=·_--~_2_1_v._re_r _.,..I ... (Q.12.1 ) in the
differen tiator·
· basic • .
· circuit~ · Rt
Run mode Keepin g the switch es S1 and S2 on ·the Run position Such a . differCO:tiator Vin o--"""l tJM,-.~
s, circuit
: integrator is operat ed in the Run ~ode . .,. · is called - •
practic al differe ntiator _
The circuit integra tes . the input signal ·and the · output
voltage is given circuit. ·
by
• The . circuit .is shown in .
the Fig. Q.13.L The
... (Q.12.2 ) resistan ce Rcomp . is
used for bias compen sation.
lold mode : Keepin g ~e switebe s 5 t and S2
Pn the Hold position s,
.
integra tor 1s operat e in the Hold mode~
d • VA • V8 .= O due to virtual ground and op-amp
. . ..
·
,!le • t gran·on proces s is then stoPPed and•the output V: -vA · - v·
m e . ed . th . ideally remains I =· in_ . - _!!L where Z 1 • R1 + - -
instant, to the value attain m e set _mode. . Z1 · .Z1 ·- : · s.C1 .
. bange in the output for ·the specific time. . sC1 \'in (s)
1cre 1s no c . .
(l+ sR1Ci)

r
A Guide for Eng/11eerlng Stude111s
A Guide ior .EnglHeri,., _....
I
Electron ic Circuits 6 -16 6 - 11 Op-11mp Appllt:atJo,u
Op-amp Applications ~E!!_l e~ctr~ o~n~lc :_C~'/ ~rc~u~ lts~..:. ..a...-~
--,::_~ :__---- -------~ -._...:: .
- VV 1..:1a1n,... rn co
• While 11 =~ =' -
-V-
0
, 12
d (VA - V0 )
= Cr ......:....:..:..-...::.....:. = -
dV
Cr - 0
Rr Rr dt dt Ideal differe ntiator
... 50 ;
• In 1:,aplace domain, l 2 (s) = - s Cr V (s). . ;
0
+40 +20 dB/decade ,,,/
• But I = 11 + 12 .. . KC:i;., at node A
+20
· ft,,,,,, . -2Q,-dB/decade
s C1 Y;n (s) -Vo(s) · CV( )
(1 + s R 1.C1)
----;-S r o S OdB _J,_ _:~: _.1- -,...~ ~--- ---
Rr Practlc al differe ntiator
-20
_V0 (s) - sRr C1 \'in (s)
(1 + sRr Cr) (1 + sR1 C 1 ) Relatlve
5
• If R r Cr = R1 C1 then Vo (s) = - s Rr C1 \'in (s) 10f
10 , freQue ncy(Hz )
· (l+sR ( C1) 2
. . ·1
• But ·Rr C1 is much greater than R C hen~e neglect
1 1 ing denominator· in ,.~ ~ - ~ fat•iiiif.o:
above equation, . Fig. Q.14.1 Freque ncy l'NpCN lae
• It can be observed fiom the ·
V.0 (s) = ~ s Rr C1V·n (s) i.e. . . d V f t)
1 d frequency increases greater than
Vo(t)= -Rr ~I~ .. . s = dt . . high frequency gets eUmfn•
Q.14 Draw the practic al differe ntiator circuit
. ])raw and explain its
freque ncy respon se. l1<ii" [SPPU : May 06~ 07,. Dec; OS, Marks 4)
Ans. _: The practical differentiator circuit is shown
in.the Fii ·Q.13 .1:
• The expression for the gain of the pra~tical
differe ntiator in terms ~f
the frequency is,
·

r
A-=
flfa

1 +( ~
• As RrC 1 is much larger than R C1 ,. we can
1 write ·
... (Q.14.1 )
• Hence as frequency increases, the gain increas
es ti.11 f ·= fb at a rate of
+20 dB/decade. Howev er after f = f b the gain
·decreases . at a rate of
20 dB/decade. This 40 dB/dec ade change at f
= fb .occurs due to the
combination pf R 1 C1 and Rr Cr ; .
So for RrC1 << T. th~ true differentiation results. , ·

is shown in the Fig. Q.14.1.

A Guid• for Engineering Students

rrro11 ic Circuits 6-JB ·
Op.amp Appllcatlo ,u·
. Electronic Clrculta ,-1,.
5 Design a differen tiator to diffi · .
Gain A In dB
es in frequen cy from 10 11z· t 0 erentta t e an input signal - that
· • frequenc y
about S00 H z. . D raw its
,onse. . +60- Ideal differentiator
sine wave of 2 V peak at 500 ~ : . . ··
+40 - +20c:IB/decade
e expressi o~ for its output and d . is apphed- to the <:lifferen
tiator,
+20- . ~ fb
· raw output wavefor m.
. ~ [SPPU : De.;,-05,09, May-09,12,
Oe!B '•
h. h Marks 8]
. Choose f as th Practical differentiator
e tg egt frequenc y to be differentiat~d.
-20
• a
fa 500 Hz= f max _,_-~-- -'....-=---~--+ :ll,,_-...,. .:,Relatlv e

:::hoose C 1 0.1 µF
1
°' 1rl, 4
10 , 105, frequency(Hz)

,·. ·1 ,... _ 1 _
••~ " 2ffR 1C 1
i.e.
21tRiC 1 of the practical- different iator
Fig. Q.16.2 Frequenc y l'NponM

10 r. = s kHz and .R 1C 1 =- R.r Cr The input sine wave ~ peak value ~ 2 V and frequency 500 Hz.
I Vin • 2 1in (211f i)
2nR 1 C 1 =:=. 2 sin (~14
318.309 Q _
V 0 (t)
R1C1 == 10 nF.
Rf . = - 3.183 x 1:03° X 0.1 X
Rcomp == R 1 II Rt-== 289.37 Q · = ...: 2 cos(3141.S92 t)
isigned circuit is as .shown in .the ·F ig• .Q.~6.1. • · The output' is showa· in
- R,• 3.183 kn V0 (t)

_:_c,= 10 nF_··

Rco,np .,.289.37
. n -2

Fig. a:11.1 Fig. Q.18.3

ponse is shown in the Fig. Q.16.2.
.
=guencY res . .
 El#!ctron ic Circuits 6 - 20
Op-amp Applications Electro11k Clrelllt6 ,' ,,

6.9: Instrumentatio n Amplifier I v,

Q.17 State the requirements of a good instrumentation
. . amp lifi1er.
. Q"(SPPU : May--06,07,08, Dec.--06,08,11,12, Marks 5)
Ans. : . The reqwrcmcnts of a good ~cntation amplifier arc,
1) Fini~e, acc~rate and . stable gain As very low level signals arc
rcqwred to be ampli_fied _b y. ·the . instrumentation amplifiers, high,
aacurate, stable and finite gam 1s the basic requirement.
2) Easier gain adjustment : A variable, gain ·over :the prescribed range is
also required. The gain adjustment must be easier and precise.
3) High input impedance To avoid ~c loading of input ·s,ources, inpu~
.. . ' Ra
impedance of the instrumentation .amplifier must be very high (ideally
infinite).
4) Low output impedance : Extremely low output impedance · (ideally
zero) to avoid the loading on the immediate stage. Fig. Q.11.1 ThNe
. .
5) High CMRR : The output of transducer, -when transmitted with l~ng • The op-amps A 1 and ·
transmission lines has presence of large common mode noise voltages. input or first stage of
The instrumentation amplifier must ampHfy only the djfferential input, • 'lbe op-amp A 3· is .
completely rejecting the common mode input component. Thus it ~ust difference amplifier
have ideally in.finite CMRR. · output stage of
6) Low power consumption The power consumption· · of an Thus if the oU1pUt of
instrumentation amplifier should be as low as possible. A I is ½1 and the
op-amp A 2 is v92 ,
·. 7) Low thermal and time drifts ·: The parameters of the instrumentatiq~
·amplifier, should not drift with temperature and time. R2 .
8) High slew rate ·: The slew rate of tl,lc instrumentation .amplifier ~ust
Vo.= R CV02 -Vo1) .. ·
1 .
be as high as possible .to provide ma,tjniwn lmdi~torte~ output voltage • Consider the first -stpge as
swing. in the Fig. Q; fs~.
· ~11 Draw the circuit of three op-amp instrumentation amplifier · • The node· A ·potential of op-amp
alMI derift la output equation. A 1 is . Vj • From the realistio
,ar· (SPPU : Miy-04,10,11, Dec.-05,09,12,13,14, June-22, Marks ~] assumption, the potential of node
Q.18.1 shows the three op-amp ~trnmentaion amplifier. B is ·a1s0 Vj . And .hence potential
V2·
of ~ _is also Vi ..

A Gl(ide for £_ngft,eerlng Students' .

 £/ectronic Circuits 6-22
Op11mp Appllcatlo,u El•ctro,,lc Clrculi. 6-JJ
, The node D potential of op-arn · . : •· . ·
· •
assumption, the potential of node Cp . A2 ·is _· V2. ·
From th 1· ·
. e rca 1st1c
• Let us implement Ro .with ·• .pot_of SO . lcn and a base resistance of
II is also V2 . · is also .V2 •. _A nd hence potential of ~OB in series with it. With pot on z~o resistance_position we get,
. . . . .. , R .
The input current of op-amp A · d . . 2Rr )( 1) 500 i 1 + ~ - 1000 i.e. _r_ • 499.S ... (Q.19.2)
· 1 an A 2 both ar H . .
remains same through Rn R d . c zero. ence current I ( l ~-Roe· 2 - .e. RoB RoB .

7-=~~R=
• . o _an Rr 2 • _ .
d - . . ·_ .
(l~:Jr:j½):
Applying Ohm's law between the
. Vol - Vo2 . V. ~ V. n~ es E -~d F we ·get, .
I == ---=-.:..---==-- =
Rn + RG + Rf2
01
2 Rr + R
.
02
G.
.
with Rn
. .
= Rf2 ;:a Rr ... (Q. 18.2)
i~ :M;
Now from the observation. of nodes O ~d H . Rr • 0.5 ••• (Q,19.3)
I = Vo - vH· Vi ~ V2 . , soxJ0 3 +Ros ·
... (QJ8.3} . 499.5R.
Ra -~ . Substituting from · equation· (Q.19.2).
50
• Equating the two equatio~s (Q.lS.4) and ·(Q ..lS.S)
V. - V, V . . .· , SOX 10 3 .+ Roa • 999 Ros i.e.
ol o2 - 2 - \'i . (2 R + R ) (V-. V, )
2 Rf + R G - R
G
i.e. Vo2 - V. l
P .
f G
Ro
2 - l
· This is the base resistance required
0

• • • Rr • 499.5
... (Q.18.4) .
• Substituting the V02 - V01 , in the eq~ation .(Q.18.1):

Vo :s . -
R2
R1
•
( .
1 + - .-
. Ro
2Rr) · \'t)(V2 -

~-19 Design an instrumentation amplifier using thre~ op-amps, with

a gain that can be varied from 1 to _500. it=r[SPPU I May-11, Marks 6)
Ans. : The gain of the instrumentation am:Plifier is given by,

A = (I+ ~R: )(~: )- A1A2 . . .. (Q.19,1)

• As A1 is gre~ter than 1, ·A2 must be ·less than 1,. to get gain A is

unity.
i.e.
et 2
R1 - 100 l<Q, i.e. R2 • SO kQ .

Fig. Q.19.1
A Guid• r. E ~
. .,or ngln_urh,g Stud~11t1 .
 0p-11mp A.ppllctltlo111
Electronic Circuits 6-24 6-25
Op-amp A.ppllcatlon1 Electronic Clrcultt
6.10 : Compar ator r,
Importa nt Points to ·R~m,e_m
_ b_e_,.;_ _ _ _ __
• A com~arat or is a circuit ~hich compares a signal voltage applied
at one input of an op-amp with . a known reference voltage at the
other input, and produce either a· lugh or a low output' voltage .
depending o~ which input is higher. '
• It produces output voltage which is either positive s~tu::ation voltage
(+ Vsar) or negative saturation voltage (- V t), , . ·
51
• The op-amp is used in a open loop configura tion fo~ a comparato r.
. ,
-··············. ······················ ················· .. ,,., ......... , .......
/

Q.20 Draw the inverting compara tor us.Ing op-amp with

por-itiva
reference and explain its operation with waveform s. .
~[SPPU : May-l:4, Dec.-06,12, Marks 6]
Ans. : The Fig. Q.20.1 +V::c Fig •
. shows inverting comparat or·
vref
in which the reference
:voltage Vrer is applied to
the non-inverting (+) input
r- Q.21 List the importan t e ·

.and signal voltage (Vin) is 1. Accuracy : It .is the smallest

applied to the inverting (-) the inputs of comparator to
input ~f the op-amp. measured in rriV.
.• Let Vrer is some positive - Fig; Q.20.1 Basic inverting comparat or 2. Logic ·threshold : It ia
voltage. comparator at whic~ th~ COIDJ«~
• The po~tive "ref can be set by using a battery and potential · divider 3. Strobe function : Certain .
as control i~put to· eublc/~ ble the- dna
per the requireme nt.
selection in. ~ d or .multiple com~
• ·When '\'in is less than °¼-:f , the output voltage V i~ at + Vsat .. 4. Respons e time : It .i s defined as the .time ~ 1'lle
0
(== +Vee) because the voltz.ge at the inverting inp.ut (-) is les~ ·than that a step voltage of pred~ ed cbara~t ics at die inpuc
at the non-inver ting(+) input. at whic~ the ou~ut cro~es the logic threshold voltage. 11114
tbe
• On the other hand, when ~n is ~ than Vref, V goes to -Vsat
•
5. Positive output level : It is the high output voltage lev .
0

<•-Vu). given load and a input drive equal to or greater than a speci'fied el With
·
6 • Negative output level : . It is the negative d.c. ·output v Voltaae.
. . 1
Otage with
the compartor satuntcd by a differenti~ input e or &reater than
specified voltage.
•
 £JedTOlfiC Circuits 6-26 0,,..C,,.,, Appllc•tlons
Electronic Circuit$ 6-27
1. Strobe current : It is defined as the current flowing out of the strobe
terminal when it is at the zero logic lcvcC
s.
to
Strobe release time : It is the time required for the output to rise
the logic threshold voltage E.fter the strobe terminal has- been driven
from zero to the logic one level.
9. Saturation voltage : The ~turation voitage is the low output voltage
l-~
~
"'; .. I
I
I
I
I
I
. I I
level with the input drive e ~ 1!l or greater th~ specified value.
Vo l l
I
l. ·
Vo ~ i
I I I +Vsat_..1..._ _ _'..,';..- - - -
10. Latching : Some compan¢:>rs have built-in latching facility. Upon +Vaat
receiving a active signal at the latch pin. the current output· state -of these o :..J----4r --+-----
0 ...J--1--+- -tr--
comparator is frozen in a latch flip-flop .and is held indefinit_e ly until
1IT1Val of a new latch command.
the
-_Vaat
--------
l.22 Explain the working of · zero crossing · detector using _op-amp
'.
I

vith waveforms. S-[SPPU : M1y-01;u, Dec.-2:3, .>un·e-22, Marks 4] • -.11·•••r

· (a) Input I• •l~u~dal
uis. : In a non-inverting zero crossing detector, the_op-amp is used · in
ipen loop mode. ·ft~_.Q.22.2 Wavefomla of•
Inverting terminal of the · +Vee
6.11:S~ ·
Reference · .
op-amp is grounded and ·voltage is zero
input is applied to the
noninverting terminal. The • · In a basic comparator. a
circuit is shown in the in the open loop mode.
Fig. Q.22. 1.
• As open loop _gain of
During the positive half can cause triggering of 1le
cycle, the input voltage is • The comparator circuit
positive i.e . above the called regenerative ~m
reference voltage. Hence uses a positive feedback.
Fig. Q.22.1 Non-inverting zero crossing
the output voltage is + Vsat • detector ·Q.23 Explain with a neat
inverting Schmitt trigger usin& op-amp.
During negative half cycle, the input voltage Vin . is n:egaiive, i.e. below trigger points. · · _ · _ Er(~: Dec.-07,11, Martt.It.
:he reference voltage. The o~tput voltage is then - °¼at . . Ans. : • The Fig. -Q.23.1 shows the basic Schmitt trigger circuit.
[bus the output ';Oltage _switches between ~-vsat
-aiid -vsa, . whenever ·• .T he inverting mode produces opposite polarity output. This i_a fed
. t signal crosses the zero level. Hence ·zero crossing of the input
he mpu the ·output . Thi . ·u to · the non-inverting input which is of same polarity as that of
s IS 1 ustrated m. p·1g. Q.22.~. .
11an b e detected from
• This ensures p~sitive.feedback.

A Gulde for E11gineering Studellls

 E lectronic Circuits

• When \'in is slightly

6-28 Op-amp Applications

+Vee
6 19
-"=its========~===~==·=~==~==--
~E~le~c!tr~on~1~·c~C~h'c~~ ~=i
1
i
==/l I
= =.=Op=-o~~...;.._App..::::~
J...::;..i---+-~-1-.;;_""!'~--s:-r~--=1:-·. -~.-.. -1
'
positive than Vref, the
output gets driven into I, I . ' 1/
negative saturation at I
.... .............. !
. - Vsat level. !

• When \'in becomes R, J,..,;~-"'.~--t--i--~-i---;

j I
more negative than
- vref , then output
gets driven . into
Fig. Q.23.1 Inverting Schmitt trlg~er
positive saturation at
+ '¼at level.
• . Thus . output voltage is always at + "sat or - "sat but the voltage at
Fig. Q.23.2 Input and .output wavetorma of Inverting Schmitt tr1911r
· which it changes its state now can be controlled by the resistance Ri
and R2. Thus '½-ef can be obtained as per_the _requirement. Q.24 Explain with a aeat cfrcaJt .......... work.IDs of nonhave
Schmitt trigger .usfn1 op-amp. DarM die ........ fer trlger
• Now R 1 and R2 forms a potential divider and we can write, .
. -{SfPU I ..._..,,11, ~15, ,.....
Ans. ·: TI1e Fig. Q.24~1 sbowt. .-. . . :ti.,.
The input is applied to tho DDCGIDDMIIII. . . ..

. .

• + Vrer is for positive saturation when V0 =;+"sat and is called upper . Rz

threshold voltage denoted as VUT .
• - .'½er is for negative saturation when V0 = ...: "s~-t . and is called-. lower
threshold voltage denoted as VL T .
• The values of these threshold voltage levels .can be detenni~ed and
adjusted by selecting proper values of R 1 and R2 . .
Fig . .Q.24.1
• The difference between Yur and VL T is called wi~th of the hysteresis
denoted as H. • To understand the wo · o
is positively saturated i.e. at +
non-inverting input-through ~1 • This
 £/ectronlc Circulti 6. 30
---~~~= ~~-~~-- ...:..::... ._~~--:- ~-~~O~'P:-a~,n~'P~AP,~.'P~l~lca~tlo~n~•
, Now though \'in is decreased, the· . l
,;
,
El•ctronlc Clrcul,.
; ,
6-·n
saturation level unless and until the . output conti nues its
· 1'
positive
VL r . input •bccom Important Points to Remember .)
ea more negative than
. Dealgn step• for Schmitt trigger circuit I
, Ar lower threshold, the output change . . ·
. s lts state from .. • Let the ~cnt through R 1 and R 2 is I 2 . The op-amp input current \
+¼at to negative saturation - V. It . po31ttve saturation
. sat · remains in n . is assumed zero. ·
V;n increases beyond tts upper threshold egat1ve saturation till !\
1cvel Yyr : . R Trigger voltage
VA = Voltage at point A • I · R • 2 - 12 . '
.
, As op-amp 1.nput current is zero. . ent·1n 2 · - VuT
V
Lin = -2.. - + "sat ·
11 0
. tre 1Y passes. through R
I·
• Select Ii much higher than op-amp bias current i.e.
12 • lOOia(max)• ·The value of IB(max) is 500 nA for IC 741 op-amp.
· · 1·
R1 - ~ . . V0 - (Trigger voltage) · V. v.·
• Whtie, R 1 - ••• o • sat .
12
... . ...................... ................
_.

Vi
UT = I in R 2 -- -R
R2 ( + V · ·I · Q.25 Design an invertin1 Sc~mltt Trill• drclllt wbON VVT ad ·
531 , = V.sa~
1 VLT are ± S V. Draw laput aad 01l1p1lt Wff......,_ A.Dame ~ p
R2 . R saturates at± 13.5 V. lir [5"U s ,.._n, ....... U.. NIIIII IJ
and R (-vsa1) = -vsat -2
1 .. . R1 Ans.: VuT - + s_v~ VLT • - ~.v, ± Y. -~ 13.5 ,r
F~ Op-amp 7~1r _fs(max) • 500 nA
and H VuT -VLT =2 "sat -R 2
i2
R1 . 100 IB(max) ~ 50 JI.A .
ff sinusoidal input is applied _ to the non-invertin g Schinitt trigger, the
nput and output wavefo.n ns. can. be ·shown as in the Fig. Q.24.2. ·

The designed .circuit and waveforms an

-. , Vii.:

I o _U_J__ _µ.-4--t-J-+-t_,__+-+---4
--v•• ,
__ j___ ,, .. --- --·-··
Fig. Q.24.2 Input ■nd ~utp~t 'w."v,•forma
.,__ _.I\A/\A,.----. J
170 kn
if
12

.l Rz
100kQ

l2
 Electronic Circuits 6-32
Op-amp Application, ,.JJ
Electronic Circuits
Q.26 Using IC 741 op-amp with a supply of ± 12
V, design an
invertin g Schmitt trigger circuit . to have Vuy = 3 V, . ·t, R
Ans. : From the given cJJ'CUI ss 33 kil, R2 - 1 k.Q
V LT = - 3 _V. 1 R
Also find the hysteres is voltage and draw the hystere sis
curve for the R2 . 2
given design.
~[SPPU : Dec.-11, Marks 8)
.
Vur • R1 +R2.
(+ YsarJ and V.LT •
R1 + R2 (-
An·s. : VUT = +3 V, VLT =--3 V , Supply ± 12 V ·
± Vsat = 0.9 x Supply = ± 10.8 V = V
0
Let ±.¼a t• 0.9 ·x (± 15 \? .~· ± 13.S V
For op-amp 741 , I B(max) = 500 nA hence 12 == 100 IB(max) .;. 50 µA ·
_!_ x 13.S = + 0.391 V, .VLT = - 0.397 V
. V . 34
V ._.y ·
R 2 = --1IT....
12
= 60 kQ and ·R1 0 =UT ·= 156 kQ .
_:. H' • \luT _ 'i.T _ 0.397 - . (- 0.397) - 0. 7~4 V .
~ 12 The input-ouqnrt wav~forms are similar to those shown _1n the Fig. Q
.-The hysteres is .voltage is given by, H =
VUT - ·vLT ~ 6 _V. The of Q.25. ·
Fig. Q.26.1 (a) shows the designe d circuit while the Fig.
Q.26.1 (b) shows
the hysteres is curve. . . .
Vo
'
f 6.12 : Square Wave Gene rator I
+V981 = ·+10.8 V
Q.28 Draw and npbda-.•-~ -ilr'; 11 ••• ...... ...... .
' Ans. : A . square wave I
VLT \.'UT
(I multivib rator using op.amp.
-3 V +3V
v,n
R 1 = 156 kn • . _T he Fig. Q.28. l
astablc multivib rator'
.R,1 60kn -V~at
-10 .8 V
op-amp .

• When V0 is at +V••
-= (a) Circu it
(b) Hysteres is curve feedbaclc voltage is
Fig. Q.26.1
the upper threshold ·
Q.27 For invertin g Schmit t t~ger shown· ·10
the Fig. Q.27.l, · '\Im
and is given • .
calculate UTP, LTP and hysteres is width. Draw the
input-o utput _ R1 · (+ Vsat) · (Q
waveforms. ~[SPPU : May-13, Marks 6) Yur- R ' R .••·
+ 15 V
· 1+ 2
· . • When V0 is at -v.,
"">- ----....---<>V o feedback voltage is called . .
RL 10~Q · i
. the iower-tbreshold.yc,ltage \lT 1111d 18 .,._
· · R1 :·(-Vw )
·\'u • R1 + R2
• Wheµ power ls •tum ON, V0 automatically •
-Vsat since 1}iese are tho only stable states
trigger. _ ·
 edf"":::,lc_C1
_ rc_11_it_s _ _ _ _ _ _6_-_3_4_ _ _ _ _-..; _ _ _~~~~~~~
!!:--- Op-o,np A.ppllcatlo11s
AssUJllC it swings to + ~<:at. With v. _
0
+V. Electronk.Clrclll# 6 • JS 0,,..-,, Applla,tloru
sat we have VP - Vur and .
.towards· +v.
•
capacitor starts charging thr 16.13: Triangular Wave Generator ·\
. . sat
Provided by the resistor R· r to the inve.....:- ( ough
) . . the fieedb ack path
. ~ ...... ,g - mput.
. Q.29 Draw and e11:plaln the operatl.o n of trlanplar waveform
As tong -as the capacitor voltage v, · • . than
.
1 1 generator. H"[SPPU : O.C.-03,05,ot, May-U,13, Martes I)
' voltage rem ains at +Vsar. · ·c · s ess .Vur , the output
Ans. : . The Fig. Q.29.1 shows ~e triangular wave_fonn generator.
, As soon as Ve charges to · a value slightly gr .. t th Schmitt
.. . ea et an Vur, the (-) trigger QUtJM~
input goes positive with respect to the (+)· • · (Rectangular) r>/
, This swi~chcs the output voltage from +V.
mput.
· V.
· ,
and ,~;e :-.---------:v~~ --- -l- ~
. . sat to -:: sat · .,., hav~
VP = VL T, which 1s negative with respect to ground.

, As V0 switches to - Vsat , capacitor st~ dis_c harging via R.r

• Tb·e current discharging t:urrent. discharges capacitor to o V and

recharges capacitor to V L T . I
I
I•
. . I
• When Ve becomes slightly more negative than the feedback voltage
Schmitt
- - . - - - . . - --- _,
\1.r, output voltage V0 switches back to + "sat and cycle continues. tri~ger

Once th~ initial cycle is completed, the waveforms b~come periodic, as .

shown in the F ig . Q.28.2. ·
• The op-amp

~;;is~ ~ . Output square

/ waveform .
op-amp B circuit is Bli integrator.
• ~e o~tput of Schmitt triger -i s
· . .and is applied to the inverting mpul af.J
Capacitor
voltage
' . While the output· of · the tri.anp1ar
feedback as . _input ·to Schmitt triaa-.
R.3 _. .
Operation :· Let the output of th~ Schmilt.
VL, - - - - • This forces current + v~t IR1 through . Ci•
- Vsat positive to left and negative· to right.
• This produces negative going ramp at its outpJt. b •
:~ . tito t·2 •
• At t2 when ramp voltage attains a value equal to LTP of .._..
•

F_lg. Q.28.2 Waveforma of Utable multlvlbiator trigger, the output of

Schmitt trigger changes its from + V111 to staae
-v.., ..
,4 G•i~ for Enginttttrlng Stuunts
 .
I ,
. .. \
.,. ,,

Electronic Circuirs
6- 36
Op-amp 'Appllcation.
• N ow f
di re ct io n of cu
rr en t Integrator ou tp ut
through Ci re ve rs es . . It
discharges arid t1 1t 1\ .
2 1\ ,
re ch ar ge s in - - - I- - - 3 4
:- - ... - - • UT
op po si te di re ct io n I . I
P
w it h po la ri ty I I
positive to rig.ht arid I
negative to -, - - t
left . I

• T hi s pr od uc es I I LTP
po si tiv e go in g
ra m p at its ou tp ut, r- -1I
fo r th e tim e
in te rv al t 2 to t 3 .
Schmitt trigger ou tp
. • At t3 w he n I
ut
ra m p vo lta ge +V sa t - -· .- -- '
I I
I
at ta in s a va lu e eq I
ua l to U T P of
Sc hm itt tr ig ge r, th
e ou tp ut of 0V - - - - - - - - - - -- t
Sc hm itt tr ig ge r ch an
ge s its st at e
fr om - Vs at to + Vsat -V sa t - - 1- - - -
I - ~I- - •, "- -
cycle continues. an d 'I - - T - - ,I I

• T he w av ef or m s
are sh ow n m Fig. Q.29.2 Waveform& of triangular
the Fi g. Q .29.2. w av ef or m ge ne
ra to r
• T he pe ak to pe ak
ou tp ut vo lta ge an d
output ·frequency is
given by ,
vo(p p)
an d

Ef '!D... .25