Module 2 ECT206 Computer Architecture and microcontrollers

Module 2
Addressing modes, instruction set, instruction classification.
Assembly language programming examples for 8051.

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Types of instructions

Depending on operation they perform, all instructions are divided in several groups:

• Data Transfer Instructions

• Arithmetic Instructions
• Logic Instructions
• Branch Instructions

The first part of each instruction, called MNEMONIC refers to the operation an instruction
performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of
operation being executed. For example: INC R1 - Means: Increment register R1 (increment
register R1).The other part of instruction, called OPERAND is separated from mnemonic by
at least one white space and defines data being processed by instructions. Some of the
instructions have no operand, while some of them have one, two or three. Here is a list of the
operands and their meanings:

o A - accumulator; o Rn - is one of working registers (R0-R7) in the currently active

RAM memory bank; o Direct - is any 8-bit address register of RAM. It can be any
general- purpose register or a
SFR (I/O port, control register etc.); o @Ri - is indirect internal or external RAM
location addressed by register R0 or R1; o #data - is an 8-bit constant included in
instruction (0-255d or oo- FF H);
o #data16 - is a 16-bit constant included as bytes 2 and 3 in instruction (0-65535or
0000-
FFFFH); o Ladd- is a 16-bit address. May be anywhere within 64KB of program
memory; o sadd- is an 11-bit address. May be within the same 2KB page of program
memory as the first byte of the following instruction;
o radd- is the address of a close memory location (from -128 to +127 relative to the first
byte of the following instruction). On the basis of it, assembler computes the value
to add

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Data Transfer Instructions

Instruction which are use to transfer data from one register to another register, memory to
register or register to memory, comes under this groups. Data transfer instruction is divided
into,
• Move destination byte , source byte
• Move destination bit , source bit MOV DPTR, # 16 bit
value

Move destination byte , source byte

This copies a byte from source location to the destination. This is again classified in to

a) Register “A” as the destination

b) Register “A” as the source
c) Rn is the destination
d) Destination is the “direct address
e) Destination is an indirect address held by R0 or R1
f) External data moves ( from RAM)
g) Code memory read only data moves (from ROM)

a)Register “A” as the destination

This can have the following four formats

1. MOV A,#data
Move the 8 bit constant data immediately to the accumulator (A)
Examples:
MOV A, # 25H ; move the 25h data to the A register
MOV A, #39H ; move the 39h data to the A register

2. MOV A,Rn
Move the content of register Rn ( n is 0 to 7) to the A register
Examples:
MOV A, R3 ; move the content of reg R3 to A
MOV A ,R5 ; move the content of reg R5 to A

3. MOV A, direct
Move the content internal RAM location to the accumulator
Example:

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MOV A, 30H ; move the content of internal RAM location 30h to

the
accumulator
MOV A, 43H ; move the content of internal RAM location 30h to
the
accumulator
4. MOV A,@Ri (i=O or 1)
Move the content of internal RAM address stored in the Ri( i=0 or 1) to the A Example:
MOV A, @ R0 ; move the content of internal RAM address stored in the R0 to the A

b)Register “A” as the source

This can have the following format

1. MOV Rn, A
Move the content of accumulator to the register Rn( n is 0 -7)
Example;
MOV R0, A : move the content of A to the register R0
2. MOV direct, A
Move the content of register A to the internal RAM location given in the
instruction Example:
MOV 40H, A : move the content of accumulator to the internal RAM location
40H
3. MOV @Ri, A
Move the content of accumulator to the internal RAM location stored in the
Ri(i=0or1) Example:
MOV @R0,A : move the content of register A to the internal RAM location given in
R0.

c) Rn is the destination
This can have the following format,

1. MOV Rn,# data

Move the 8 bit data to the register Rn( n is 0-7)
Example;
MOV R0, # 40H ; Move the data 40h to the register R0

2. MOV Rn, A
Move the content of accumulator to the register Rn( n is 0 -7)
Example;
MOV R0, A : move the content of A to the register R0

3. MOV Rn, direct

Move the content of internal RAM location given in the instruction to the register

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Rn( n is 0-7).
Example;
MOV RO, 40H :move the content of internal RAM location to RO.

d) Destination is the “direct address

This can have the following format

1. MOV direct, #data

Move the 8 bit data given in the instruction to the internal RAM location
Example;
MOV 50h, # 40h ; move 40 h to the internal RAM location 50h.

2. MOV direct, @Ri

Move the content of internal ram location stored in the Ri( i=0 or 1) to the
internal ram location given in the instruction.

Example:
MOV 40h, @R0 ; Move the content of internal ram location stored in the RO
register to the internal ram location 40h.

3. MOV direct, A
Move the content of register A to the internal RAM location given in the
instruction Example:
MOV 40H, A : move the content of accumulator to the internal RAM location
40H

4. MOV direct, Rn
Move the content of register Rn ( n is 0 -7) to the internal ram address given in the
instruction. Example;
MOV 30H, R5 ; Move the content of reg R5 to the internal RAM location
30h.

e) Destination is an indirect address held by R0 or R1

This can have the following format

1. MOV @Ri, #data

Move the 8 bit data to the internal RAM location stored in Ri( i =0 or 1)
Example;
MOV @R0, #30H : mov the data 30h to the internal RAM location stored in R0.
2. MOV @Ri, A

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Move the content of accumulator to the internal RAM location stored in the
Ri(i=0or1) Example:
MOV @R0,A : move the content of register A to the internal RAM location
given in R0.
3. MOV @Ri, direct
Move the content of internal ram address given in the instruction to the internal
ram address stored in Ri ( i =0 or 1).

Example;
MOV @ R0, 40H ; move the content of 40h to the internal ram location stored in
the R0

f) External data moves ( from RAM)

This can have the following format

1. MOVX A, @ Ri where i = 0 or 1

This moves to the accumulator a byte from external memory whose 8-bitaddress is
pointed to by Ri
Example;
MOVX A,@Rl. ;move the content of external memory stored in the R1 to
accumulator.

2. MOVX A, @ DPTR
This moves into the accumulator a byte from external memory whose address is
pointed to by DPTR.In other words, this brings data into the CPU (register A) from
the off-chip memory of the 8051.

3. MOVX @ Ri , A
This moves a byte from register A to an external memory location whose8-bit address
is held by RO(or Rl in MOVX @ Rl,A)

4. MOVX @ DPTR, A
This moves the contents of the accumulator to the external memory location whose
address is held by DPTR. In other words, this takes data from inside the CPU (register
A) to memory outside of the 8051.
g) Code memory read only data moves (from ROM)

This can have the following format ,

1. MOVC A, @A+DPTR
This instruction moves a byte of data located in program (code) ROM
into register A. This Allows us to put strings of data, such as look-up table elements,
in the code space and read them into the CPU. The address of the desired byte in
the code

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space (on-chip ROM) is formed by adding the original value of the accumulator to the
16-bit DPTR register.

2. MOVC A, @ A+PC

This instruction moves a byte of data located in the program (code)

area to A. The address of the desired byte of data is formed by adding the program
counter (PC) register to the original value of the accumulator. Contrast this instruction
with "MOVC A, @A+DPTR". Here the PC is used to generate the data address
instead of DPTR

Move destination bit , source bit

This MOV instruction copies the source bit to the destination bit. In this instruction one of the
operands must be the CY -flag. Look at the following examples.

MOV Pl.2,C ;copy carry bit to port bit Pl.2

MOV C,P2.5 ;copy port bit P2.5 to carry bit

MOV DPTR, # 16 bit value

This instruction loads the 16-bit DPTR (data pointer) register with a 16-bitimmediate value
.Examples:

MOV DPTR,#456FH : DPTR=456FH

MOV DPTR,# MYDATA; load 16-bit address assigned to MYDATA

POP direct

This copies the byte pointed to by SP (stack 'pointer) to the location whose direct address is
indicated, and decrements SP by 1. Notice that this instruction supports only direct
addressing mode. Therefore, instructions such as "POP A" or "POP R3" are illegal. Instead
we must write "POP OEOH" where EOH is the RAM address belonging to register A and
"POP 03" where 03 is the RAM address ofR3 of bank0.

PUSH direct

This copies the indicated byte onto the stack and increments SP by 1 Notice that this
instruction supports only direct addressing mode. Therefore, instructions such as "PUSH A"
or "PUSH R3" are illegal. Instead we must write "PUSH OEOH" where EOH is the RAM
address belonging to register A and "PUSH 03" where 03 is the RAM address ofR3 of bank0.

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XCH A, Byte

This instruction swaps the contents of register A and the source byte. The source byte can be
any register or RAM location.

Example:

MOV A,#65H ;A=65H

MOV R2,#97H ;R2=97H
XCH A, R2 ;now A=97H and R2=65H

1. XCH A, Rn Example: XCH A,R3

2. XCH A,direct
Example; XCH A,40H ;exchange A with data in RAM location 40H
3. XCH A,@Rn
Example;
XCH A, @RO;XCHA with data pointed to by RO XCH
A, @Rl;XCHA with data pointed to by Rl

XCHD A, @Ri

The XCHD instruction exchanges only the lower nibble of A with the lower nibble of the
RAM location pointed to by Ri while leaving the upper nibbles in both places intact.

Example: Assuming RAM location 40H has the value 97H, find its content after the following
instructions.

;40H= (97H)
MOV A,#l2H;A=12H (0001 0010 binary)
MOV R1,40H;R1=40H, load pointer
XCHD A,@R1;exchange the lower nibble of;A and RAM location 40H

After execution of the XCHD instruction, we have A = 17H and RAM location 40H has 92H.

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Arithmetic Instructions
The instruction of this group performs arithmetic operation such as addition, subtraction,
increment, decrement etc. Arithmetic instruction is divided into

1. Increment and decrement instructions

2. Addition instructions
3. Subtraction instructions
4. Multiplication and division instructions

Increment and decrement instructions

This can have the following format

INC byte
This instruction adds 1 to the register or memory location specified by the operand. Note that
CY is not affected even if value FF is incremented to 00

1. INCA
This instruction adds 1 to the accumulator content.
2. INC Rn
This instruction adds 1 to the content of Rn (n= 0-7) register
Example;
INC R0
INC R3
3. INC direct
This instruction adds 1 to the byte in internal ram location.
Example;
INC 40H ; instruction adds 1 to the byte in internal ram location
4. INC @Ri
This instruction adds 1 to the byte pointed to by Ri.
Example;
INC @R0 ; This instruction adds 1 to the byte pointed to by R0

INC DPTR

This instruction increments the 16-bit register DPTR (data pointer) by 1.Notice that DPTR is
the only 16-bit register that can be incremented. Also notice that there is no decrement
version of this instruction.
Example:

MOV DPTR, #l6FFH ; DPTR=16FFH

INC DPTR;now OPTR=1700H

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DEC byte

This instruction subtracts 1 from the byte operand. Note that CY (carry/borrow)is unchanged
even if a value 00 is decremented and becomes FF.

1. DECA
This instruction subtracts 1 to the accumulator content.
2. DEC Rn
This instruction subtract 1 to the content of Rn (n= 0-7) register
Example;
DEC R5
DEC R4
3. DEC direct
This instruction subs 1 to the byte in internal ram location.
Example;
DEC 40H ; instruction subs 1 to the byte in internal ram location

4. DEC @Ri
This instruction subs 1 to the byte pointed to by Ri.
Example;
DEC @R0 ; This instruction subs 1 to the byte pointed to by R0

Addition instructions

This can have the following four formats

ADD A, source byte

This adds the source byte to the accumulator (A), and places the result in A. Since register A
is one byte in size, the source operands must also be one byte. Flags affected are Flags: OV,
AC, and CY.

1. ADD A, # data
This instruction adds the 8 bit data to the content of A and places the result in A
Example;
ADD A, # 40H ; Adds the content of accumulator to data 40h and result
placed in the A
2. ADD A , Rn
This instruction adds the content register Rn( n= 0-7) to the content of A and places
the Result in A
Example;
ADD A, R0 ; This instruction adds the content register R0 to the content of A and
places the result in A

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3. ADD A, direct
This instruction adds the content of internal RAM location given in the instruction to
the
accumulator. And places the result in A
Example;
ADD A, 40H ; this instruction adds the content of internal RAM location
40H to the accumulator. And places the result in A

4. ADD A, @ Ri

This instruction adds the contents of internal RAM location stored in the Ri(i=0or 1)
to the accumulator. And places the result in A
Example;
ADD A, @ R0 ; This instruction adds the contents of internal RAM
location stored in the R0 to the accumulator. And places the result in A

5. DA A( Decimal-adjust accumulator after addition)

This instruction is used after addition of BCD numbers to convert the result back to
BCD. The data is adjusted in the following 2 possible cases.
1. It adds 6 to the lower 4 bits of A if it is greater than 9 or if AC = 1.
2. It also adds 6 to the upper 4 bits of A if it is greater than 9 or if CY = 1.

Example:
MOV A, #47H ; A=0100 0111
ADD A, #38H ; A=47H+38H=7fH, invalid BCD
DA A ; A=1000 0101=85H, valid BCD

47H
+ 38H
7FH
+ -6H
85H

ADDC A,source byte

This will add the source byte to A, in addition to the CY flag (A = A + byte+ CY). If CY = I
prior to this instruction, CY is also added to A. If CY =0 prior to the instruction, source is
added to destination plus O. This is used in multi byte additions. Flags affected are OV, AC,
CY,

1. ADDC A, # data
This instruction adds the 8 bit data, CY content to the content of A and places the
result in AExample;
ADDC A, # 40H ; Adds the content of accumulator to data 40h,CY flag and result
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placed in the A

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2. ADDC A, Rn
This instruction adds the content register Rn( n= 0-7), CY flag to the content of A and
places the result in A
Example;
ADDC A, R0; This instruction adds the content register R0, cy flag to the
content of A and places the result in A

3. ADDC A, direct
This instruction adds the content of internal RAM location given in the instruction,
CY flag content to the accumulator. And places the result in A
Example;
ADD A, 40H ; this instruction adds the content of internal RAM
location 40H,cy flag content to the accumulator. And places the result in A

4. ADDC A, @Ri
This instruction adds the contents of internal RAM location stored in the
Ri(i=0or 1), cy flag content to the accumulator. And places the result in A
Example;
ADD A, @ R0 ; This instruction adds the contents of internal RAM
Location stored in the R0 , cy flag content to the accumulator. And places the result
in A

Subtraction instructions
This can have the following four formats

SUBB A, source-byte

This subtracts the source-byte and the carry flag from the accumulator and puts the result in
the accumulator. Flags affected are OV, AC, CY The steps for subtraction performed by
the internal hardware of the CPU are as follows:

1. Take the 2's complement of the source byte.

2. Add this to register A .
3. Invert the carry.

1. SUBB A, # data
This instruction subtract the 8 bit data and the carry flag from the
accumulator and put result in the accumulator.
Example;
SUBB A, # 50H ; This instruction subtract the 50H data and the carry
flag from the accumulator and put result in the accumulator.
2. SUBB A, Rn

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This instruction subtract the content of Rn (n=0-7 ) and the carry flag from
the accumulator and put result in the accumulator
Example;
SUBB A, R0 ;This instruction subtract the content of R0 and the
carry flag from the accumulator and put result in the accumulator

3. SUBB A, direct
This instruction subtract the content of internal RAM address and the
carry flag from the accumulator and put result in the accumulator.
Example;
SUBB A, 40H ; This instruction subtract the content of internal RAM
address 40H and the carry flag from the accumulator and put
result in
the
Accumulator.
4. SUBB A, @ Ri
This instruction subtract the content of internal RAM address stored in Ri(i= 0 or 1)
and the carry flag from the accumulator and put result in the accumulator.
Example;
SUBB A, @R0 ; This instruction subtract the content of internal RAM
address Stored in R0 and the carry flag from the accumulator
and put
result in the accumulator.

Multiplication and division instructions

MUL AB

This multiplies an unsigned byte in A by a unsigned byte in register Band the result is placed
in A and B where A has the lower byte and B has the higher byte. Flags affected are OV, CY

Example:
MOV A,#10
MOV B,#15
MUL AB ;A=150=96H, B=OO

DIV AB

This instruction divides a byte accumulator by the byte in register B. It is assumed that both
registers A and B contain an unsigned byte. After the division ,the quotient will be in register
A and the remainder in register B. If you divide by zero(that is setting register B = 0 before
the execution of"DIV AB"), the values in register A and B are undefined and the 0 V flag is
set to high to indicate an invalid result. Notice that CY is always 0 in this instruction.

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Example:
MOV A,#97H

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MOV B, #l2H
DIV AB ;A=8 and B=7

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Logic Instructions

The instruction of this group performs logical operation such as AND, OR, XOR Rotate and
swap instructions etc. Logical instruction is divided into,

1. AND instruction
2. OR instruction
3. XOR instruction
4. Rotate and swap instruction

According to the operation logical instruction is mainly classified in to two that are
byte level logical operation and bit level logical operations.

Byte level logical operations

AND instructions

ANL dest-byte,source-byte

This performs a logical AND on the operands ,bit by bit, storing the result in
the destination. Notice that both the source and destination values are byte-size only.

1. ANL A, # data
This instruction ANDs the 8 bit immediate data to the content of accumulator
and place the result in accumulator.
Example;

ANL A,# 09H ; This instruction ANDs the 8 bit immediate data09H to the
content of accumulator and place the result in accumulator.

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MOV A,#39H ;A=39H

ANL A, #09H ;A=39H ANDed with 09

39 h 0011 1001
09 h 0000 1001
09 h 0000 1001

2. ANL A, direct
This instruction ANDs the content of internal RAM location with
accumulator content and place the result in A.
Example;
ANL A, 40H ; This instruction ANDs the content of internal RAM location
40h with accumulator content and place the result
in A.

3. ANL A, Rn
This instruction ANDs the content of register Rn(n=0-7) with accumulator
content and place the result in A.
Example;
ANL A, R0 ; This instruction ANDs the content of register Rn(n=0-7) with
accumulator content and place the result in
4. ANL A, @Ri
This instruction ANDs the content of internal RAM location stored in Ri( i=0
or1) with accumulator content and place the result in A.
Example;
ANL A, @R0 ;This instruction ANDs the content of internal RAM location
stored in R0with accumulator content and place the result in A.

5. ANL direct, # data

This instruction ANDs the 8 bit data with internal RAM location content
and place the result in RAM location.
Example;
ANL 40h, # 50h ; This instruction ANDs the 8 bit data 50h with internal RAM
location 40h content and place the result in RAM location

6. ANL direct ,A
This instruction ANDs the accumulator with internal RAM location content and
place the result in RAM location.
Example;
ANL 40H, A ; This instruction ANDs the accumulator with internal RAM
location40H content and place the result in RAM location OR instructions

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ORL dest-byte, source-byte

This performs a logical OR on the byte operands, bit by bit, and stores the result in the
destination.
1. ORL A, # data
This instruction ORs the 8 bit immediate data to the content of accumulator and
place the result in accumulator.
Example;

ORL A,# 09H ; This instruction ORs the 8 bit immediate data 09H to the
content of accumulator and place the result in accumulator.

MOV A,# 39H ;A=39H

ORL A, #09H ;A=39H OR 09 (A=39H)

39H0011 1001
09H 0000 1001
39H0011 1001

2. ORL A, direct
This instruction ORs the content of internal RAM location with accumulator
content and place the result in A.

Example;
ORL A, 40H ; This instruction ORs the content of internal RAM location 40h
with accumulator content and place the result in A.

3. ORL A, Rn
This instruction ORs the content of register Rn(n=0-7) with accumulator
content and place the result in A.
Example;
ORL A, R0 ; This instruction ORs the content of register Rn(n=0-7) with
accumulator content and place the result in

4. ORL A, @Ri
This instruction ORs the content of internal RAM location stored in Ri( i=0
or1) with accumulator content and place the result in A.
Example;
ORL A, @R0; This instruction ORs the content of internal RAM location
stored in R0with accumulator content and place the result in A.

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5. ORL direct, # data

This instruction ORs the 8 bit data with internal RAM location content and
place the result in RAM location.
Example;
ORL 40h, # 50h ; This instruction ORs the 8 bit data 50h with internal RAM
location 40h content and place the result in RAM location

6. ORL direct ,A
This instruction ORs the accumulator with internal RAM location content and
place the result in RAM location.
Example;
ORL 40H, A ; This instruction ORs the accumulator with internal RAM
location40H content and place the result in RAM location

XOR instructions

XRL dest-byte,source-byte

This performs a logical exclusive-OR on the operands, bit by bit, storing the result in the
destination

1. XRL A, # data
This instruction XORs the 8 bit immediate data to the content of accumulator
and place the result in accumulator.
Example;

XRL A,# 40H ; This instruction XORs the 8 bit immediate data 40H to the
content of accumulator and place the result in accumulator.

2. XRL A, direct
This instruction XORs the content of internal RAM location with
accumulator content and place the result in A.
Example;
XRL A, 40H ; This instruction XORs the content of internal RAM location
40h with accumulator content and place the result
in A.

3. XRL A, Rn
This instruction XORs the content of register Rn(n=0-7) with accumulator
content and place the result in A.
Example;

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XRL A, R0 ; This instruction XORs the content of register R4 with

accumulator content and place the result in

MOV A,#32H ; A=32H

MOV R4,#50H ; R4=50H
XRL A,R4; (A=62H)

32H0011 0010
50H0101 0000
62H0110 0010
4. XRL A, @Ri
This instruction XORs the content of internal RAM location stored in Ri( i=0
or1) with accumulator content and place the result in A.
Example;
XRL A, @R0 ;This instruction XORs the content of internal RAM location
stored in R0with accumulator content and place the result in A.

5. XRL direct, # data

This instruction XORs the 8 bit data with internal RAM location content
and place the result in RAM location.
Example;
XRL 40h, # 50h ; This instruction XORs the 8 bit data 50h with internal RAM
location 40h content and place the result in RAM location

6. XRL direct ,A
This instruction XORs the accumulator with internal RAM location content
and place the result in RAM location.
Example;
XRL 40H, A ; This instruction XORs the accumulator with internal RAM
location40H content and place the result in RAM location

Rotate and swap instructions

This can have the following four formats

1. RL A

This rotates the bits of A left. The bits rotated out of A are rotated back into A at the opposite
end.

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Example:
MOV A,#69H
RL A;Now A= 11010010
RL A ;Now A=10100101

2. RR A
This rotates the bits of register Aright. The bits rotated out of A are rotated back into
A at the opposite end.

Example;

MOV A,#66H
RRA ;Now A= 00110011
RR A;Now A=10011001

3. RLC A
This rotates the bits of the accumulator left. The bits rotated out of register A are
rotated into CY, and the CY bit is rotated into the opposite end of the accumulator.

Example;

CLR C ; CY =0
MOV A,#99H ; A=10011001
RLC A ; NOW A =00110010 and CY =1
RLC A ; NOW A= 01100101 and CY =0

4. RRC A

This rotates the bits of the accumulator right. The bits rotated out of register A are
rotated into CY and the CY bit is rotated into the opposite end of the accumulator

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Example;
MOV A,# 99H ; A = 10011001
RRC A ; Now A = 11001100 CY=1

5. SWAP A

The SWAP instruction interchanges the lower nibble (DO - D3) with the upper Nibble
(D4 -D7) inside register A.
Example:
MOV A,#59H;A=59H (0101 1001 in binary)
SWAP A;A=95H (1001 0101 in binary)

Compliment and clear instruction

1. CLR A
This instruction clears register A. All bits of the accumulator are set to O.
2. CPL A
This complements the contents of register A, the accumulator. The result is the l's
complement of the accumulator. That is: Os become 1s and 1s become Os.

Bit level logical operations

AND Instructions

ANL C,source-bit

In this instruction the carry flag bit is AND ed with a source bit and the result is placed in
carry. Therefore, if source bit = 0, CY is cleared; otherwise, the CY flag remains unchanged.
Example;

ANL C, P2.2 ; In this instruction the carry flag bit is AND ed with a P2.2and the
result is placed in carry

Another variation of this instruction involves the ANDing of the CY flag bit with the
complement of the source bit. Its format is "ANL C,/bit".

ANL C, / P2.2 ; In this instruction the carry flag bit is ANDed with the compliment
of P2.2and the result is placed in carry

OR instructions

ORL C,source-bit

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In this instruction the carry flag bit is ORed with a source bit and the result is placed in the
carry flag. Therefore, if the source bit is 1, CY is set; otherwise, the CY flag remains
Unchanged.

Example;
ORL C , P2.3 ; In this instruction the carry flag bit ORed with the
bitP2.3 and theresult is placed in carry.

Another variation of this instruction involves ORing CY with the complement of the source
bit. Its format is "ORL C,/bit".

ORL C, /P2.3 ; In this instruction the carry flag bit ORed with the
Compliment ofP2.3 and the result is placed in carry.

Clear and compliment instructions

1. CLR bit

This instruction clears a single bit. The bit can be the carry flag, or any bit-addressable
location in the 8051

Example;
CLR P 2.3 ; Clear the bit P2.3

2. CPL bit
This instruction compliments a single bit. The bit can be the carry flag, or any bitaddressable
location in the 8051
Example;
CPL P2.3 ; Compliment the bit P2.3,
3. SETB bit

This sets high the indicated bit. The bit can be the carry or any directly
addressable bit of a port, register, or RAM location.
Examples:
SETBPl. 3 ; Pl. 3=1
SETB P2.6 ; P2. 6=1
SETB ACC.6 ;ACC.6=1
SETB C ;Set Carry Flag

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Module 2 ECT206 Computer Architecture and microcontrollers

Branch Instructions;

This group includes the instruction for conditional and unconditional jump,
subroutine call and return, restart. Branch instruction is mainly classified in to ,

1. JUMP instructions
2. CALL instructions
3. Return instructions

The jump or call instruction may have on of the three ranges, that are
(a) Relative range of +128, to -127 byte from the instruction following the jump or
call instruction.
(b) Absolute range on the same 2k byte page as he instruction following the jump or
call.
(c) A long absolute range of any address from 0000h to FFFFh.

Jump instructions

Jump instructions are mainly classified in to two that are, conditional jump
instructions and unconditional jump instructions.

Conditional jump instructions

According to the operation the conditional jump instruction is mainly classified in to two,
(a) byte level conditional jump instruction,
(b) bit level conditional jump instruction

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Byte level conditional jump instruction,

DJNZ byte, target (radd)

In this instruction a byte is decremented, and if the result is not zero it will jump to target
address in relative range,
1. DJNZ Rn, target( radd)
In this instruction decremented the content of Rn( n=0-7), and if the result is not
zero it will jump to target address in relative range, Example;
DJNZ R0, target ; In this instruction decremented the content of R0,
and
if the result is not zero it will jump to target address in relative
range
2. DJNZ direct , target (radd)
In this instruction decremented the content of internal RAM location, and if the result is
not zero it will jump to target address in relative range,

Example;
DJNZ 40h, target ; In this instruction decremented the content of
RAM
Location , and if the result is not zero it will jump to target address in relative range

CJNE dest-byte,source-byte,target (radd)

The magnitudes of the source byte and destination byte are compared. If they are not equal, it
jumps to the target address.

1. CJNE A, direct, target (radd)

This instruction compares the content of accumulator with the content of
internal RAM location. If they are not equal, then jump to the target address in the
relative range.
Example;
CJNE A, 40H, target ; This instruction compares the content of accumulator
with the content of internal RAM location. If they are not equal, then jump to the
target address in the relative range.

2. CJNE A,# data, target (radd)

This instruction compares the content of accumulator with the 8bit data. If
they are not equal, then jump to the target address in the relative range.
Example;
CJNE A, #40H, target ;This instruction compares the content of accumulator
with the DATA 40H. If they are not equal, then jump to the target address in the
relative range.

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3. CJNE Rn,# data, target (radd)

This instruction compares the 8bit data with the register Rn. If they are not
equal, then jump to the target address in the relative range.
Example;
CJNE R0, #40H, target ;This instruction compares the 8bit data
with the content Of register R0 If they are not equal, then jump to the target address
in the relative range.
4. CJNE@Ri.#data, target(radd)
This instruction compare the content of internal RAM location stored in the
Ri(i=0or1) with the 8bit data, If they are not equal, then jump to the target address in
the relative range.

Example;
CJNE@ R0, #40H, target ;This instruction compares the 8bit data
with the with the content of internal RAM location stored in register R0 If they are
not equal, then jump to the target address in the relative range.

1. JNZ target( radd)

This instruction jumps if register A has a value other than zero.

2. JZ target( radd)

This instruction examines the contents of the accumulator and jumps if it has value
O.

Bit level jump instruction;

J condition, target (radd)

In this type of jump, control is transferred to a target address if certain conditions are met.
The target address cannot be more than -128 to + 127 bytes away from the current PC.

JC Jump carry jump if CY = 1

JNC Jump no carry jump if CY =0
JZ Jump zero jump if register A = 0
JNZ bitJump no zero jump I f register A is not 0
JNB bitJump no bit jump if bit = 0
JB bitJump bit jump if bit =1
JBC Jump bit clear bit jump if bit = 1 and clear
bit

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Notice that all "J condition" instructions are short jumps, meaning that the target address
cannot be more than -128 bytes backward or +127 bytes forward of the PC of the instruction
following the jump.

Unconditional jump instructions

Unconditional jump do not test any bit or byte to determine whether the jump should
taken. The jump is always taken.

1. JMP @A+DPTR

The JMP instruction is an unconditional jump to a target address. The target address
is provided by the total sum of register A and the DPTR register.

2. AJMP target(Sadd)
AJMP stands for "absolute jump." It transfers program execution to the target address
unconditionally. The target address for this instruction must be within2K bytes of
program memory.

3. LJMP target(Ladd)
This is a 3-byte instruction. The first byte is the opcode and the next two bytes are the
target address. As a result, LJMP is used to jump to any address location within the
64K byte code space of the 8051.

4. SJMP target(radd)
This is a 2-byte instruction. The first byte is the opcode and the second byte is the
signed number displacement, which is added to the PC (program counter) of the
instruction following the SJMP to get the target address. Therefore, in this jump the
target address must be within -128 to + 127bytes of the PC (program counter)

5. NOP
This performs no operation and execution continues with the next instruction. It is
sometimes used for timing delays to waste clock cycles. This instruction only updates
the PC (program counter) to point to the next instruction following NOP.

Call instructions

Another control transfer instruction is CALL instruction, which is used to call subroutine.
There are two type of call instruction in 8051 that are.

1. LCALL(long call)
2. ACALL(absolute call)

There are two types of CALLs: ACALL and LCALL. In ACALL, the target address is
with in 2K bytes of the current PC (program counter). To reach the target address in the
64K bytes maximum ROM space of the 8051, we must use LCALL. If calling a

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subroutine, the

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PC register (which has the address of the instruction after the ACALL) is pushed onto the
stack and the stack pointer (SP)is incremented by 2. Then the program counter is loaded
with the new address and control is transferred to the subroutine. At the end of the
procedure, when RET is executed, PC is popped off the stack, which returns control to
the instruction after the CALL.

Notice that LCALL is a 3-byte instruction, in which one byte is the opcode, and the other
two bytes are the 16-bit address of the target subroutine. ACALL is a 2-byte instruction,
in which 5 bits are used for the opcode and the remaining 11 bits are used for the target
subroutine address. An II-bit address limits the range to 2K bytes.

Return instructions

RET
This instruction is used to return from a subroutine previously entered by instructions LCALL
or ACALL. The top two bytes of the stack are popped into the program counter (PC) and
program execution continues at this new address. After popping the top two bytes of the stack
into the program counter, the stack pointer (SP) is decremented by 2.

RETI
This is used at the end of an interrupt service routine (interrupt handler). The top two bytes of
the stack are popped into the program counter and program execution continues at this new
address. After popping the top two bytes of the stack into the program counter (PC), the stack
pointer (SP) is decremented by 2. Notice that while the RET instruction is used at the end of a
subroutine associated with the ACALL and LCALL instructions, IRET must be used for the
interrupt service subroutines.

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ARITHMETIC PROGRAMS

Example 1;

Write program to add two 8bit number.

MOV DPTR, # 4500H ; DPTR= 4500H

MOV A,# 06H ; 1st data (06h) to the accumulator
MOV R0, #06H ; 2nd data (06h) to the R0 register.
ADD A, R0 ; A+R0 = A , now A= 06H
MOVX @DPTR, A ; store the accumulator content in memory location
4500

Example 2;

Write a program to add two 8 bit numbers. Assume that input data is in the memory
location 4500 and 4501 and store the result in 4503 and 4504 .and also check the carry.

CLR R3 ; clear R3
MOV DPTR, #4500H ; DPTR =4500
MOVX A, @DPTR A ; move the 1st data in memory location 4500 to

MOV R0, A ; move the content of A register to R3

INC DPTR ; increment dptr , now DPTR =4501
MOVXA, @DPTR ; move the 2nd data in memory location 4500 to
A
ADD A, R0 ; A+R0= A
JNC LOOP ; check the carry , if no carry go to loop otherwise
go to next step
INC R3 ; if carry increment R3.
LOOP; INC DPTR ; increment dptr. , now DPTR = 4502
MOVX @DPTR, A ; store the result in 4502
INC DPTR ; now DPTR = 4503
MOV A, R3 ; move carry into accumulator
MONX @DPTR, A ; store the carry in 4503
END; SJMP END

Example 3

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Write a program to add two 8 bit numbers. Assume that input data is in the internal RAM
location 45h and 46H and store the result in 60Hand 61H.and also check the carry.

CLR R3 ; clear R3
MOV A, 45 H ; move the 1st data in memory location 45H to A
MOV R0, 46H ; move the 2nd data in memory location 46H to R0
ADD A, R0 ; A+R0= A
JNC LOOP ; check the carry ,if no carry go to loop otherwise go to next step

INC R3 ; if carry increment

R3. LOOP: MOV 70H, A ;store the result in 70H

MOV 71H, R0 ; store carry in 71h END:
SJMP END

Example 4;

Write a program to add N 8 bit numbers. Assume that input data is in the internal RAM
location starting fro 46H and store the result in 60Hand 61h.and also check the carry.

MOV R2, # count ; enter the count (N) to R2

CLR R1 ; clear R1 for carry storing
MOV R0, # 46H ; move the memory location of the input data into R0
CLR A ; clear accumulator
LOOP1: ADD A, @R0 ; add the content of A register with the content of
memory
Location stored in R0
JNC LOOP ; check the carry, if no carry go to loop otherwise go to
next step
INC R1 ; if carry increment R1
LOOP INC R0 ; increment the RAM location for next data
DJNZ R2, LOOP1 ; decrement the count if zero go to next step otherwise go
loop1
MOV 60H, A ; store the result in 60H
MOV 61H, R1 ; store carry in 61h
END: SJMP END

Example 5;
Write a program to add two 16 bit numbers,
Note:- for addition of two 16bit number , first add the LSB of two 16 bit numbers with ADD
instruction and then add MSB with ADDC instruction.
The numbers are 4045h and 4140h
CLR C ; clear cy
MOV A,# 45H ; move LSB of first number to A
ADD A, # 40H ; add the LSB of first no: with 2nd number.
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MOV R5, A ; save the low byte of sum in R5

MOV A, #40H ; move the MSB of 1st number to A
ADDC A, #41H ; Add the MSB of 2nd number with A and carry
MOV R6, A ;save the high byte of sum in R6
END: SJMP END
Example 6;

Write a program to subtract two 8 bit numbers. Assume that input data is in the internal RAM
location 45h and 46H and store the result in 60Hand 61H.and also check the carry.

CLR C ; clear carry

CLR R3 ; clear R3
MOV A, 45 H ; move the 1st data in memory location 45H to A
MOV R0, 46H ; move the 2nd data in memory location 46H to R0
SUBB A, R0 ; A-R0-CY= A
JNC LOOP ; check the carry , if no carry go to loop otherwise go to next
step
INC R3 ; if carry increment R3.

LOOP: MOV 70H, A ;store the result in 70H

MOV 71H, R0 ; store carry in 71h
END: SJMP END
Example 7;
To write an assembly language program to perform 8-bit multiplication

MOV DPTR, #4500H

MOVX A,@DPTR
MOV B, A
INC DPTR
MOVX A,@DPTR
MUL AB
INC DPTR
MOVX @DPTR, A
MOV A, B
INC DPTR
MOVX @DPTR, A
HERE: SJMP HERE
END.

Example 8;
To write an assembly language program to generate Fibonacci series.
MOV DPTR, #4500H
MOVX A,@DPTR
MOV R1, A
JNZ LOOP3
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SJMP HERE

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LOOP3: MOVE R0, #00H

MOV B, #00H
INC DPTR
MOV A, R0
MOVX DPTR, A
DJNZ R1, LOOP
SJMP HERE
LOOP MOV A, #01H
INC DPTR
MOVX @ DPTR, A
DJNZ R1, LOOP1
SJMP HERE
LOOP1: MOV B, A
ADD A, R0
MOV R0, B
INC DPTR
MOVX @DPTR, A
DJNZ R1, LOOP1
HERE: SJMP HERE END

Example 9: write an assembly language program to find largest among n

number

MOV DPTR, # 4500h

MOVX A, @ DPTR
MOV R0, A
DEC R0
INC DPTR
MOVX A, @ DPTR
TARGET: MOV 30h, A
INC DPTR
MOVX A, @ DPTR
CJNE A, 30h, LOOP1
LOOP1: JNZ LOOP
MOV A, 30h
LOOP: DJNZ R0, TARGET
INC DPTR
MOVX @ DPTR, A
HERE: SJMP HERE
END
INPUT INPUT data OUTPUT OUTPUT
MEMROY MEMORY
LOCATION LOCATION

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4500 h 01 h 4505 h 04 h
4501 h 02 h
4502 h 03 h
4503 h 04 h

Example 10 ;
To write an assembly language program to sort an array in ascending order.

MOV DPTR, # 4500h

MOVX A, @ DPTR
MOV R0, A
LOOP4: MOV DPTR, # 4500h
MOVX A, @ DPTR
MOV R1, A
DEC R1
INC DPTR
LOOP3: MOVX A, @ DPTR
MOV 50h, A
INC DPTR
MOVX A, @ DPTR
CJNE A, 50h, LOOP1
LOOP1: JNC LOOP2
MOV R2,A
MOV A, 50h
MOVX @ DPTR, A
MOV A, R2
DEC DPL
MOVX @ DPTR, A INC
DPTR

LOOP2: DJNZ R1, LOOP3

DJNZ R0, LOOP4
HERE: SJMP HERE
END
INPUT MEMROY INPUT data OUTPUT OUTPUT
LOCATION MEMORY
LOCATION

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4500 h 04 h 4501 h 22 h
4501 h 43 h 4502 h 33 h
4502 h 33 h 4503 h 42 h
4503 h 22 h 4504 h 43 h
4504 h 42 h

Example 11;

To write an assembly language program to generate square wave generation

START: MOV P1, # 0FFh
ACALL DELAY
MOV P1, # 00h
ACALL DELAY
SJMP START
DELAY: MOV R0, # 0FFh
LOOP: DJNZ R0, LOOP
RET
END

Example 12;
To write an assembly language program to generate triangular waveform

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START: MOVA, # 00h

LOOP1: MOV P1, A
INC A
JNZ LOOP1
MOV A, # 0FFh
LOOP2: MOV P1, A
DEC A
JNZ LOOP2
SJMP START
END

TIME DELAY GENERATION AND CALCULATION

For the CPU to execute an instruction takes a certain number of clock cycles. In the 8051
family, these clock cycles are referred to as machine cycles. List of 8Q51 instructions and
their machine cycles are explained in the above section. To calculate a time delay, we use this
list. In the 8051 family, the length of the machine cycle depends on the frequency of the
crystal oscillator connected to the8051 system. The crystal oscillator, along with on-chip
circuitry, provide the clock source for the 8051 CPU. The frequency of the crystal connected
to the 8051 family can vary from 4 MHz to 30 MHz, depending on the chip rating and
manufacturer. Very often the 11.0592 MHz crystal oscillator is used to make the 8051-based
system compatible with the serial port of the IBM PC . In the 8051, one machine cycle lasts
12 oscillator periods. Therefore, to calculate the machine cycle, we take 1/12 of the crystal
frequency, then take its inverse,

Example;

The following shows crystal frequency for three different 8051-based systems. Find the
period of the machine cycle in each case.
(a) 11.0592 MHz (b) t6MHz (c) 20 MHz

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Solution:
(a) 11.0592/12 = 921.6 kHz; machine cycle is 1/921.6 kHz = 1.085µs (microsecond)
(b) 16MHz/12= 1.333 MHz; machine cycle (MC) = 1/.1.333 MHz = 0.75µs (microsecond
(c) 20 MHz/12 = 1.66 MHz; MC = 1/1.66 MHz = 0.60µs

Example;

For an 8051 system of l 1.0592MHz find how long it takes to execute each of the following
instructions.

(a) MOV R5, #55H

(d) LJMP
(g) MUL AB
(b) DEC R3
(e) SJMP
(c) DJNZ R2, target
(f) NOP (no operation)

Solution:

The machine cycle for a system of 11.0592 MHz is 1.085µs Machine cycles for each of the
above instructions. Therefore, we have:

Instruction machine cycle time to execute

(a) MOV R5, #55H 1 1×1.085 µs=1.085 µs

(d) LJMP 2 2×1.085 µs=2.17µs
(g) MUL AB 4 4×1.085 µs=4.34µs
(b) DEC R3 1 1×1.085 µs=1.085µs
(e) SJMP 2 2×1.085 µs=2.17µs
(c) DJNZ R2, target 2 2×1.085 µs=2.17µs
(f) NOP (no operation) 1 1×1.085 µs=1.085 µs

Example;

Find the size of the delay in the following program, if the; crystal frequency is 11.0592MHz
MOV A,#55H
AGAIN: MOV Pl,A
ACALL DELAY
CPL A
SJMP AGAIN
delay
DELAY: MOV R3,#200
HERE: DJNZ R3,HERE RET

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Solution:
We have the following machine cycles for each instruction of the DELAY subroutine.

Machine Cycle

DELAY:MOV R3,#200 1
HERE:DJNZ R3,HERE 2
RET 1
Therefore, we have a time delay of [(200 x 2) + 1 + 1] x 1.085µs=436.17.

Example;

For a machine cycle of 1.085µs, find the time delay in the following subroutine.

DELAY: Machine Cycle

MOV R2, # 200 1
AGAIN: MOV R3, #250 1
HERE: NOP 1
NOP 1
DJNZ R3,HERE 2
DJNZ R2,AGAIN 2

For the HERE loop, we have (4 x 250) 1.085µs = 1085 µs. The AGAIN loop repeats the
HERE loop 200 times; therefore, we have 200×1.085 µs=217000, if we do not include the
overhead. However, the instructions "MOV R3, #250" and DJNZ R2 ,AGAIN “at the
beginning and end of the AGAIN loop add (3 x 200 x1.085 µs) =651µsto the time delay. As a
result we have 217000 + 651 =217651 Milliseconds for total time delay associated with the
above DELAY subroutine.

Addressing modes

The CPU can access data in various ways. The data could be in a register, or in memory, or
be provided as an immediate value. These various ways of accessing data are called
addressing modes. The various addressing modes of a microprocessor are determined when it
is designed- and therefore cannot be changed by the programmer. The 8051 provides a total
of five distinct addressing modes. They are as follows:

(l) Immediate
(2) Register
(3) Direct
(4) register indirect
(5) Indexed

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Immediate addressing mode

In this addressing mode, the source operand is a constant. In immediate addressing mode, as
the name implies, when the instruction is assembled, the operand comes immediately after
the opcode. Notice that the immediate data must be preceded by the pound sign, "#". This
addressing mode can be used to load information into any of the registers, including the
DPTR register. Examples follow.

MOV A,#25H ;load 25H into A

MOV R4,#62 ;load the decimal value 62 into R4
MOV B,#40H :load 40H into B
MOV DPTR,#4521H ;DPTR=4512H

Although the DPTR register is 16-bit, it can also be accessed as two 8-bitregisters, DPH and
DPL, where DPH is the high byte and DPL is the low byte. Look at the following code.
MOV DPTR,#2550H is
the same as:
MOV DPL,#50H MOV
DPH,#25H

Register addressing mode

Register addressing mode involves the use of registers to hold the data to be manipulated.
Examples of register addressing mode follow.

MOV A, RO ;copy the contents of RO into A

MOV R2, A ;copy the contents of A into R2
ADD A, R5 ;add the contents of R5 to contents of A
ADD A,R7 ;add the contents of R7 to contents of A
MOV R6,A ;save accumulator in R6

It should be noted that the source and destination registers must match in size. In other words,
coding "MOV DPTR,A" will give an error, since the source is an 8-bit register and the
destination is a 16-bit register. See the following.
MOV DPTR,#25F5H
MOV R7, DPL
MOV R6,DPH

Notice that we can move data between the accumulator and Rn (for n = 0 to 7) but movement
of data between Rn registers is not allowed .For example, the instruction "MOV R4, R7" is
invalid.

Direct addressing mode

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There are 128 bytes of RAM in the 8051. The RAM has been assigned
addresses 00 to 7FH. The following is summary of the allocation of these 128 bytes.

1. RAM locations 00 - IFH are assigned to the register banks and stack.
2. RAM locations 20 - 2FH are set aside as bit-addressable space .
3. RAM locations 30 - 7FH are available as a place to save byte- sized data.

Although the entire 128 bytes of RAM can be accessed using direct addressing mode, it is most
often used to access RAM locations 30 - 7FH. This is due to the fact that register bank locations
are accessed by the register names of .R0 - R7, but there is no such name for other RAM
location. in direct addressing mode, the data is in a RAM memory location whose address is
know, and this address is given as a part of the instruction. Contrast this with immediate
addressing mode in which the operand itself is provide~ with the instruction. The "#" sign
Distinguishes between the two modes. See the examples below, and note the absence of the "#"
sign.

MOV RO,40H ;save content of RAM location 40H in RO

MOV 56H,A ; save content of A in RAM location 56H MOV R4,7FH
;move contents of RAM location 7FH to R4

Register indirect addressing mode

In the register indirect addressing mode, a register is used as a pointer to the data. If the data
is inside the CPU, only registers RO and Rl are used for this purpose: In other words, R2 -R7
cannot be used to hold the address of an operand located in RAM when using this addressing
mode: when RO and Rl are used as pointers, that is, when they hold the addresses of RAM
locations, they must be preceded by the "@" sign, as shown below.

MOV A,@RO ;move contents of RAM location whose

;address is held by RO into A
MOV @Rl, B ;move contents of B into RAM location
;whose address is held by Rl

Advantage of register indirect addressing mode

One of the advantages of register indirect addressing mode is that it make accessing data
dynamic rather than static as in the case of direct addressing mode. (b) looping of instruction
is possible .
Limitation of register indirect addressing mode in the 8051

As stated earlier, RO and Rl are the only registers that can be used for pointers in register
indirect addressing mode. Since RO and Rl are 8 bits wide,

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Indexed addressing mode and on-chip ROM access

Indexed addressing mode is widely used in accessing data elements of look-up table entries
located in the program ROM space of the 8051. The instruction used for this purpose is
"MOVC A, @A+DPTR". The 16-bit register DPTR and register A are used to form ,the
address of the data element stored in on-chip ROM. Because the data elements are stored in
the program (code) space ROM of the8051, it uses the instruction MOVC instead of MOV.
The "C" means code. In this instruction the contents of A are added to the 16-bit register
DPTR to form the 16- bit address of the needed data.

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