Module 2 ECT206- Computer Architecture and Microcontroller

Microcontroller
Microcontroller is a true computer on a chip. The design incorporates all of
the features found in a microprocessor CPU: ALU, PC, SP, and registers. It also has
added the other features needed to make a complete computer: ROM, RAM, parallel
I/O, serial I/O, counters, and a clock circuit. Like the microprocessor, a micro
controller is a general-purpose device, but one that is meant to read data, performs
limited calculations on that data, and control its environment based on those
calculations. The prime use of a microcontroller is to control the operation of a
machine using a fixed program that is stored in ROM and that does not change over the
lifetime of the system.

Comparing Microprocessors and Microcontrollers

1. A microprocessor is a general-purpose digital computer central processing unit

(CPU). Microcontroller is a true computer on a chip.
2. Microprocessors have many operational codes (opcodes) for moving data from
external memory to the CPU; microcontrollers have one or two
3. Microprocessors may have one or two types of bit-handling instructions
microcontrollers will have many.
4. The microprocessor is concerned with rapid movement of code and data from
external addresses to the chip; the microcontroller is concerned with rapid movement
of bits within the chip.

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5. The micro controller can function as a computer with the addition of no external
digital parts the microprocessor must have many additional parts to be operational.

TYPES OF MICROCONTROLLERS

Figure shows the various types of microcontrollers. The microcontrollers are classified
in terms of internal bus width. Embedded microcontroller, instruction set, memory
architecture, IC chip. Or VLSI (V HDL or Verilog) file and family.

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1. The 8, 16, and 32-Bit Microcontrollers

The 8-bit microcontroller: When the internal bus in an MCU is 8-bit and ALU performs
arithmetic and logic operations on a byte at an instruction, the MCU is an 8-bit
microcontroller. Some 8-bit MCUs are Intel 8031/8051 family and Motorola MC68HCl
1 family.
The 16-bit microcontroller: When the internal bus in an N4CU is 16-bit and the ALU
performs arithmetic and logic operations on a word of 16 bits at an instruction, the
MCU is a 16-bit microcontroller. Important 16-bit MCUs are extended 8051XA, Intel
8096 family and Motorola MC68HC12 and MC68332 families. These provide greater
precision and performance compared to the 8-bit MCUs.
The 32-bit microcontroller: When internal bus for the data transfer operations in an
MCU is 32-bit and the ALU performs arithmetic and logic operations on a word of 32
bits at an instruction, the MCU is a 32-bit microcontroller. Important 32-bit NICUs are
Intel/Atmel 251 family, Intel family, MotM01a M683xx family, and ARM 7 or 9 or 11
processor-based systems These computing systems for applications—mobile phones,
MP3 audio systems, MPEG processing, image processing-based products and
aerospace systems are the examples.

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2. Embedded and External Memory Microcontrollers

Embedded microcontroller: an embedded system has an MC U that has all the

hardware and software units in a single unit. The MCU is called embedded
microcontroller. Very few or no other external unit or system is present for processing
during the control or use of the external devices. For example. A telephone handset
circuit uses an embedded microcontroller.

External memory microcontroller: When an embedded system has an MCU that has all
the hardware and software units present not as a single unit and has all or part of the
in memory unit externally interfaced using an interfacing circuit which is called the
glue circuit, the MCU is called an external memory microcontroller. For example, 803 1
has the program memory which is interfaced externally to it. The 8051 has both
internal as well as external program memory.
3. CISC and RISC Architecture Microcontrollers

Complicated Instruction Set Computer (CISC) architecture microcontroller: When an

MCU has an instruction set that supports many addressing modes for the arithmetic
and logical instructions and when there are the memory accesses during the ALU
operations and the data transfer instructions, the MCU is said to be possessing CISC
architecture. CISC provides flexibility in choosing various ways of performing the data
transfer, arithmetic and other operations.
Reduced Instruction Set Computer (RISC) microcontroller: When an MCU has an
instruction set that supports a few addressing modes for the arithmetic and logical
Instructions and just a few store, push and pop Instructions for the data transfer, the
MCU is said to be of RISC architecture. RISC provides no flexibility in choosing the many
different ways of performing the arithmetic and logic operations.. RISC implements each
instruction In a single cycle using a distinct hardwired control. It uses a lesser amount
of circuitry. It has less power dissipation. There is reduced instruction set. Instructions
are of fixed number of bytes and take a fixed amount of time for execution.

The RISC provides a higher performance in computing than the CISC. This is because
little need of the external fetches, which takes a significant amount of processor time.
High performance is also because of hardwired implementation of instructions
4. Harvard and Princeton Memory Architecture Microcontrollers

Harvard memory architecture microcontroller: When an MCU has a distinct memory

address space for the program and data memory, the MCU has Harvard memory
architecture in the processor. The MCU has separate instructions, and hence separate
control signal(s), for the data transfers from these two memories

Princeton memory architecture microcontroller: When an MCU has a common memory

address space usable for the program memory and data memory, the MCU has Princeton
memory architecture in the processor. It has no separate instructions, and hence no
separate control signal(s) for data transfers from and to these two sets of memories.

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(Program and data can be stored on the same memory chip or unit within same address
block.)
SELECTION OF A MICROCONTROLLER
1. Checklist of the Needed Features and Factors Taken into Consideration

Features Taken into Consideration while Selecting an MCU

• 8-bit or 1 6-bit or 32-bit ALU

• Power dissipation permissible (maximum limit) and the clock Speed need (lowest

• limit)

• RISC or CISC or RISC core with the CISC instruction set

• Program storage architecture Harvard or Princeton memory and the required

total
• External and internal memory up to or more

• DMA controller requirement, if any

• Cache, memory management unit requirement if any

• Intensive computations at a fast rate requirement if any

The following resources are also checked for various requirements:

1. Internal EEPROM Flash/ROM/EPROM.

2. Serial synchronous communication full duplex or half.

3. Serial UART

4. Timer l, 2 or 3.

5. Watchdog timer none or I.

6. Out-compares none or I or 2 or 3 or 4 or 5.

7. Input captures none or 1 or 2 or 3.

8. PWM none or 1 or 2 or 3 or 4.

9. Single or multi-channel ADC and is it required with or without programmable

voltage reference and with single or dual reference.

10. Modem device.

11. Digital signal processing (DSP) with DSP instructions processing CPU.

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12. Non-linear controller instructions processing CPU.

13. Ports with the network interface and network processing related instructions
processing CPU.

14. Ports with wireless interface and related processing instructions capable CPU.

15. USB/PCI/FC/CAN/JTAG/SDIO interface devices.

Additional Factors Taken into Consideration while Selecting an MCU
• Cost when single chip and when MCU interfaces to circuit with some features
externally added
• Major building hardware blocks and their cost and availability

• Major building blocks of software, their cost and availability and required
Hardware/software tradeoff
• Ease of integration
• Availability of design team expertise
• Availability and cost of development software and hardware tools
• Ease and availability of testing and debugging facilities
• Easy and reliable availability of the MCU, development tools and building blocks for
hardware and software
2. Selection of Processor and Processor Family

First' it should be decided whether to use a microprocessor or microcontroller-based

design and also whether to use an 8-bit or 16-bit or 32-bit MCU. If there are intensive
computations and the memory need is large, then a microprocessor-based design cap
be selected. When the computations are not intensive and either chip or single-unit
design is preferred, then an MCU-based design can be selected, Second, the selection of
the processor family is made. For example, whether to use MCU of Intel or ARM or
Motorola family or Texas Instruments family or Hitachi family, and so on. In selecting
the family' the MCU cost, availability and cost of development tools and efforts needed
for the design are taken into consideration. For example, if a design team is well versed
in Intel 8051 family micro Controllers, has access to development tools and the product
can be delivered with perfection and at a reasonable cost and time, then the Intel 8051
family will be selected.
Finally, the selection of a processor family member as a chip or a VLSI core (library
cell) is taken into consideration. For killer applications like a mobile phone, the core
used is such that very high cost of core-based development can be recovered easily by
the manufacturer.

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3. Selection of On-Chip Resources-Base

In an MCU family, the available resources can be variable. The cost of an MCU in the
same family varies and depends on the on-chip resources (internal hardware blocks).
For example, some MCU of 8051 family member may have 4 kB internal program
memory and other 8 kB; the member will be selected according to the program size, if
cost differential is minimal. The MCU is finally selected and the cost is also taken into
consideration.
4. Selection of Software Building Blocks
Some software building blocks, for example, the codes for the queues, merging, and
sorting and string operations are selected. This saves the development efforts and
reduces the implementation time.
5. Selection of Development Tool-Base

Selection of appropriate hardware and software development tools is also important

when deciding MCU. An IDE (Integrated Development Environment) provides the project
management tools. An example of IDE is micro-Vision 2. It is Keil Software Inc. There
are two modes of IDE. MPLAB is Integrated Development Environment (IDE) for PIC and
DSPPIC microcontrollers.
APPLICATIONS OF MICROCONTROLLERS
Microcontrollers have innumerable applications. Some examples of their simple
applications are

1. Biomedical instruments like an ECG LCD display cum recorder, blood cell
recorder cum analyzer, patient monitor system,
2. Communication systems like numeric pagers, cellular phones, cable TV
terminals, FAX and transceivers with or without an accelerator, video game and
so on,
3. Peripheral controllers of a computer such as the keyboard controller, printer
controller, laser printer controller, LAN controller and disk drive controller,
4. Instruments such as an industrial process controller, and electronic smart
weight display system ,
5. target tracker,
6. an automatic signal tracker,
7. Accurate control of the speed and position of a DC motor,
8. Robotics system
9. CNC machine controller
10. Automotive applications like a close loop engine control, a dynamic ride
control, an anti-lock braking system monitor and so on,

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11. Electronic data acquisition and supervisory control system, the industrial
moisture recorder cum controller, CRT display controller, digital storage
system and spectrum analyzer. Etc..

MICROCONTROLLER ON-CHIP RESOURCES

Each microcontroller has a basic processing unit and has a number of resources.
The commonly present resources are as follows:

1. Basic processing unit, internal buses and interrupt handler.

2. On-chip program memory, Internal EEPROM and Flash.
3. On-chip RAM.
4. Interfacing capability to external program memory.
5. Interfacing capability to external data memory.
6. Ports.
7. On-chip registers.
8. Special function registers.
9. UART .
10. Timers/counters.
11. Pulse width modulator (PWM).
12. On-chip ADC.
13. Watchdog timer .
14. Bitwise manipulation capability.
15. Power-down mode.
16. Real-time clock.

1. Basic Processing Unit, Internal Buses and Interrupt Handling

Basic Processing unit: Processing unit processes the instruction. It fetches, decodes,
read operands, executes and writes back the results during processing an instruction.
After each fetch of the instruction' the program counter sets for the next instruction.
When one instruction is completed, the processing of other instruction begins. Each
microcontroller has a basic processing unit, the processing unit has the IR (instruction
register), instruction decoder, ALU (arithmetic and logic unit for arithmetic and logic
operations), oscillator circuit and has an internal reset circuitry.
Internal buses: Most of the subunits inside a microcontroller are interconnected through
a common set of parallel lines called the internal bus. An internal bus carries the signals
(bits) from one internal subunit to another at an instant.

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2. Program memory and data memory

Program memory can be on-chip and/or external in the MCU-based system. Program
functions and routines in an MCU are mostly in a non-volatile read only memory (ROM
The program memory stores the read-only codes, constant input data and parameters
of the programs.
On-chip Internal Flash and EEPROM :Flash Memory: Flash EEPROM (electrically
erasable and electrically programmable ROM) is also referred to simply as flash. Flash
can be erased by electrical signals.

Data Memory: Data variables and stacks in an MCU are mostly in a volatile read and
write memory (RAM) or registers.
3. Ports
A port the bits are latched (placed) and sent to the processor or external device or circuit.
When the bits are sent (placed) from an external circuit, the port is called the input
port. When the bits are (placed) for an external circuit by the processor, the port is
called the output port.

There are two types of ports—parallel and serial. A parallel 8-bit port means all the 8
bits can be placed at all its pins simultaneously. A serial port means all the 8 bits of a
byte or character can be placed at its pin in 8 time slots. The time interval for each slot
is the same and depends on a preset bit-rate.

4. On-chip Registers
An MCU has several on-chip registers. Registers are needed in the register addressing
instructions and for the operands in the arithmetic and logic operations. Advantage of
the registers is that a register can be addressed in an instruction by a few bits
5 .Special Function Registers
An MCU can have several registers, which are used for special functions. These registers
are called SFRs (special function registers).
6. UART

The serial-line device is present in most MCUs, because the serial port is needed to
communicate with many external and remote devices. In serial communication, a
stream of 1's and 0's is sent or received at successive time Intervals on a single line
called the serial line. UART: (Universal Asynchronous Receiver and Transmission) is a
very popular mode of serial communication. The transmission and reception in UART
mode is asynchronous. The successive bytes are sent and received at the serial line
such that there may be variable time gap between the bytes. Also the transmitter and
receiver clocks must be of the same rate but they are independent (need not be in
same phase or in synchronization). Such transmission is also called

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asynchronous serial

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communication. There is a transmit buffer which is present with the byte for serial
transmission. There is a receive buffer, which receives the byte during serial reception.
7. Timers/Counters

The 8051 has two timers/counters. They can be used either as timers. To generate a
time delay or as counters to count events happening outside the microcontroller.
8. PWM
An MCU version may have one or more pulse width modulated outputs (PWMs). PWM
output is one which the width percentage is proportional to the value loaded in a special
function register which loads the modulation parameters.
9. On -Chip A/D Converters (ADC)
Many times, a microcontroller has an on-chip A/D (called ADC also) conversion
feature. This is an important feature in the control applications for converting the
analog signal to digital.
10. Watchdog Timer (WDT)
The watchdog timer is a timing device that resets the system after a pre-defined timeout.
WDT resets and then the further processing is (i ) either from the same address as at
the beginning on the power-up (for example, in 8051) or (ii) as per the bytes at a vector
address in certain MCU timeouts of the WDT (for example, in 68HCl 1). Most
microcontroller variants of an MCU family have on-chip watchdog timer.

8051 MICROCONTROLLER

8051 an 8-bit microcontroller .This microcontroller had 128

bytes of RAM, '4K bytes of on-chip ROM, two timers, one serial port, and four ports (each
8-bits wide) all on a single chip. At the time it was also referred to as a "system on a
chip." The 8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of
data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed
by the CPU. The 8051 has a total of four I/O ports, each 8 bits wide.

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The 8051 architecture consists of these specific features:

1. Eight-bit CPU with registers A (the accumulator) and B
2. Sixteen-bit program counter (PC) and data pointer (DPTR)
3. Eight-bit program status word (PSW)
4. Eight-bit stack pointer (SP)
5. Internal ROM 4K (8051)
6. Internal RAM of 128 bytes:
 Four register banks, each containing eight registers
 Sixteen bytes, which may be addressed at the bit level
 Eighty bytes of general-purpose data memory
7. Thirty-two input /output pins arranged as four 8-bit ports: PO- P3
8. Two 16-bit timer /counters: TO and T1
9. Full duplex serial data receiver /transmitter: SBUF
10. Control registers: TCON, TMOD, SCON, PCON, IP, and IE
11. Two external and three internal interrupt sources
12. Oscillator and clock circuits

ARCHITECTURE OF 8051
A and B CPU registers

The 8051 contains 34 general-purpose or working registers. Two of

these, registers A and B, hold results of many instructions, particularly math and

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logical operations, of the 8051 central processing unit (CPU). The A (accumulator)
register is the most versatile of the two CPU registers and is used for many operations,
including addition, subtraction, integer multiplication and division, and Boolean bit
manipulations. The A register is also used for all data transfers between the 8051 and
any external memory. The B register is used with the A register for multiplication and
division operations and pas no other function other than as a location where data may
be stored.
Program Counter and Data Pointer

The 8051 contains two 16-bit registers; the program counter (PC) and
the data pointer (DPTR). Each is used to hold the address of a byte in memory. PC
points the address of the next instruction to be executed. The PC is automatically
incremented after every instruction byte is fetched and may also be altered by certain
instructions. The PC is the only register that does not have an internal address.
The DPTR register is made up of two 8-bit registers, named DPH and
DPL, which are used to furnish memory addresses" for internal and external code
access and external data access:. The DPTR is under the control of program
instructions and can be specified by its 16-bit name, DPTR, or by each individual byte
name, DPH and DPL. DPTR does not have a single internal address; DPH and DPL are
each assigned an address.
PSW (program status word) register

The program status word (PSW) register is an 8-bit register. It is

also referred to as the Flag register. Although the PSW register is 8 bits wide, only 6
bits of it are used by the 8051. The two unused bits are user-definable flags. Four of
the flags are called' conditional flags, meaning that they indicate some conditions that
resulted after an instruction was executed. These four are CY (carry), AC (auxiliary
carry), P (parity), and OV (Overflow). As seen from Figure 2-4, the bits PSW3 and
PSW4 are designated as RSO and RS I, and are used to change the bank registers. They
are explained in the next section. The PSW.5 and PSW.l bits are general-purpose status
flag bits and can be used by the programmer for any purpose. In other words, they are
user definable. See Figure for the bits of the PSW register.
D7 D0
CY AC FO RS1 RS0 OV ------ P

CY, the carry flag

This flag is set whenever there is a carry out from theJl1-bi-t. This flag
bit is affected after an 8-bit addition or subtraction. It can also be set to I or 0 directly

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by an instruction such as SETB C" and "CLR C" where. "SETB C" stands for "set bit
carry" and "CLR C. 'for "Clear carry"..
AC, the auxiliary carry flag

If there is a carry from D3 to D4 during an ADD or SUB operation, this

bit is set; otherwise, it is cleared. This flag is used by instructions that perform BCD
(binary coded decimal) arithmetic.
P, the parity flag
The parity flag reflects the number of Is in the A (accumulator) register
only. If the A register contains an odd number of Is, then P = 1. Therefore, P = 0 if A has
an even number of 1s.
Ov, the overflow flag
This flag is set whenever the result of a signed number operation is too
large, causing the high-order bit to overflow into the sign bit. The over flow flag Is set to
1 either the following two condition occurs

1. There is a carry from D6 to D7 but no carry from D7 2.

There is a carry from D7 but no carry from D6 to d7.

In general, the carry flag is used to detect errors in unsigned arithmetic operations. The
over flow flag is only used to detect errors in signed arithmetic operations and
RS0, RS1 - Register bank select bits.
These two bits are used to select one of four register banks of RAM. By
setting and clearing these bits, registers R0-R7 are stored in one of four banks of RAM

RS1 RS0 REGISTER ADDRESS

BANK
0 0 0 00H- 07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

Stack and stack pointer (SP)

If the stack is a section of RAM ,there must be registers inside the
CPU to point to it. The register used to access the stack is called the SP (stack pointer)
register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take
values of 00 to FFH. When the 8051 is powered up, the SP register contains value 07.

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This means that RAM location 08 is the first location being used for the stack by the
8051. The storing of a CPU register in the stack is called a PUSH, and loading the
contents of the stack back into a CPU register is called a POP. In other words, a register
is pushed onto the stack to save it and popped off the stack to retrieve it. The job of the
SP is very critical when push and pop actions are performed. To see how the stack
works, let's look at the PUSH and POP instructions
Pushing onto the stack
In the 8051the stack pointer (SP) is pointing to the last used location
of the stack. As we push data onto the stack, the stack pointer (SP) is incremented by
one. Notice that this is different from many microprocessors, 1n x85 processors in
which the SP is decremented when data is pushed onto the stack. When each PUSH is
executed, the contents of the register are saved on the stack and SP is incremented by
1. Notice that for every byte of data saved on the stack, SP is incremented only once.
Popping from the stack

Popping the contents of the stack back into a given register is the
opposite process of pushing. With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer is decremented once.
The upper limit of the stack

As mentioned earlier, in the 8051 RAM locations 08 to IF can be used

for the stack. This is due to the fact that locations 20 -2FH of RAM are reserved for
bitaddressable memory and must not be used by the stack. If in a given program we
need more than 24 bytes (08 to IFH = 24 bytes) of stack, we can change the SP to point
to RAM locations 30 - 7FH. This is done with the instruction "MOV SP, #xx"
Internal RAM

The 8051 microcontroller has a total of 128 bytes of RAM. The 128
bytes of RAM inside the 8051 are assigned addresses 00 to 7FH. They can be accessed
directly as memory locations. These 128 bytes are divided into three different groups as
follows.

1. A total of 32 bytes from locations 00 to IF hex are set aside for register banks and
the stack. These 32 bytes are divided into 4 banks of registers in which each bank
has 8 registers, RO - R7. RAM locations from 0 to 7 are set aside for bank 0 of RO
- R7 where RO is RAM location 0, Rl is RAM location 1, R2 is location 2, and so
on, until memory location 7 which belongs to R7 of bank O. The second bank of
registers RO-R7 starts at RAM location 08 and goes to location OFH. The third
bank of RO- R7 starts at memory location 10H and goes to location 17H; finally,
RAM locations 18H to 1FH are set aside for the fourth bank of RO -R7. The
following shows how the 32 bytes are allocated into 4 banks

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2. A total of 16 bytes from locations 20H to 2FH are set aside for bit addressable
read/write memory. A bit-addressable area of 16 bytes occupies RAM byte
addresses 20h to 2Fh, forming a total of 128 addressable bits. An addressable bit
may be specified by its bit address of ooh to 7Fh, or 8 bits may form any byte
address from 20h to 2Fh. Thus, for example, bit address 4Fh is also bit 7 of byte
address 29h. Addressable bits are useful when the program need only remember
a binary event (switch on, light off, etc.).

2. A total of 80 bytes from locations 30H to 7FH are used for read and write storage,
or what is normally called a scratch pad. These 80 locations of RAM are widely
'used for the purpose of storing data and parameters by 8051 programmers.

Internal ROM
The 8051 contain an internal ROM of 4K byte capacity, it occupies
code address space ooooh to OFFFh. The PC is ordinarily used to address program
code bytes from addresses ooooh to FFFFh. Program addresses higher than OFFFh,
which exceed the internal ROM capacity, will cause the 8051 to automatically fetch
code bytes from external program memory. Code bytes can also be fetched

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exclusively from an

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external memory, addresses ooooh to FFFFh, by connecting the external access pin (EA
pin 31 on the DIP) to ground. The PC does not care where the code is; the circuit designer
decides whether the code is found totally in internal ROM, totally in external ROM, or
in a combination of internal and external ROM.
PIN DESCRIPTION OF THE 8051

Although 8051 family members (e.g., 8751, 89C51, DS5000) come in different
packages, such as DIP (dual in-line package), QFP (quad flat package), and LLC
(leadless chip carrier), they all have 40 pins that are dedicated for various functions
such as I/O, RD, WR, address, data, and interrupts.

From above figure note that of the 40 pins, a total of 32 pins are set aside for the four
ports PO, PI, P2, and P3, where each port takes 8 pins. The rest of the pins are
designated as Vcc, GND, XTALl, XTAL2, RST, EA, PSEN. Or these 8 pins, six of them
(Vcc, GND, XTALl, XTAL2, RST, and EA) are used by all members of the 8051 and 8031
families. In other words, they must be connected in order for the system to work,
regardless of whether the microcontroller is of the 8051 or 8031 family. Vcc,

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Pin 40 provide the voltage to chip. The voltage source is +5v.

GND
Pin 20 is the ground.
XTAL 1 and XTAL2

The 8051 has an on-chip oscillator but requires an external clock to run it. Most often
a quartz crystal oscillator is connected to inputs XTALl (pin 19) and XTAL2 (pin 18).
The quartz crystal oscillator connected to XTAL1 and XTAL2 also needs two capacitors
of 30 pF .One side of
Each capacitor is connected to the ground as shown in Figure

If you decide to use a frequency source other than a crystal oscillator, such as a TTL
oscillator, it will be connected to XTALl; XTAL2 is left unconnected, as shown in Figure
.

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RST
Pin 9 is .the RESET pin. It is an input and is active high (normally low). Upon applying
a high pulse to this pin, the microcontroller will reset and terminate an activities. This
is often referred to as a power-on reset. Activating a power-on reset will cause all
values in the registers to be lost. Table provides a partial list of 8051 registers and their
values after power-on reset.

Reset value of some 8051 register

Register Reset value
PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000

Notice that the value of the PC (program counter) is 0 upon reset, forcing the CPU to
fech the first opcode from ROM memory location 0000. This means that we must place
the first line of source code in ROM location 0 because that is where the CPU. wakes up
and expects to find the first instruction. Figure shows two ways of connecting the RST
pin to the power-on reset circuitry. In order for the RESET input to be effective, it must
'have a minimum duration of 2 machine cycles. In other words, the high pulse must be
high for a minimum of 2 machine cycles before it is allowed to go low.

Power on reset circuit

̅ 𝑬𝐴̅̅̅̅/VPP

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Module 2 ECT206- Computer Architecture and Microcontroller

The 8051 family member ,such as the 8751, 89C5J, or DS5000, all come with on-chip
ROM to store programs. In such cases, the EA pin is connected to Vcc .For family
members such as the 8031 and 8032 in which there is no on-chip ROM, code is stored
on an external ROM and is

Fetched by the 8031/32. Therefore, for the 8031 the EA pin must be connected to GND
to indicate that the code is stored externally. EA, which stands for "external access," is
pin number 31 in the DIP packages. It is an input pin and must be connected-to either
Vcc or GND. In other words, it cannot be left unconnected

𝑷
̅ 𝑺𝑬𝑁̅̅̅̅̅̅̅̅

This is an output pin. PSEN stands for "program store enable." In an 8051-
based system in which an external ROM holds the program code, this pin is connected
to the OE pin of the ROM.
ALE

ALE (address latch enable) is an output pin and is active high. When
connecting an 8051 'to external memory, port 0 provides both address and data. In other
words, the 8051 multiplexes address and data through port 0 to save pins. The ALE pin
is used for de multiplexing the address and data by connecting to the G pin of the
74LS373 chip.

I/O port pins and their functions

The four ports PO,PI, P2, and P3 each use 8 pins, making them 8-bit
ports. All the ports upon RESET are configured as output, ready to be used as output
ports. To use any of these ports as an input port, it must be programmed,

Port 0
Port 0 occupies a total of 8 pins (pins 32 - 39). It can be used for input
or output. To use the pins of port 0 as both input and output ports, each pin must be
connected externally to a 10K ohm pull-up resistor. This is due to the fact that PO is an
open drain, unlike PI, P2, and P3. Open drain is a term used for MOS chips in the same
way that open collector is used for TTL chips. In any system using the 8051, we
normally connect P0 to pull-up resistors. In this way we take advantage of port0 for
both input and output. With external pull-up resistors connected upon reset, port 0 is
configured

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as an output port. For example, the following code will continuously send out to port 0
the alternating values 55B and AAH.

MOV A, #55H
BACK: MOV PO,A
ACALL DELAY
CPL A
SJMP BACK

Port 0 with pull-up resistor

Port 0 as input

With resistors connected to port 0, in order to make it an input , the

port must be programmed by writing 1 to all the bits. In the following code, port 0 is
configured first as an input port by writing 1s to it, and then data is received from that
port and sent to PI.

MOV A, #OFFH ; A= FF hex

MOV PO, A ; make p0 as an input port by writing 1s to it

BACK: MOV A, PO ; get data from p0

MOV Pl. A ; send it to port 1

SJMP BACK ; keep doing it

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Dual role of port 0

Port 0 is also designated as ADO-AD7, allowing it to be used for both

address and data. When connecting an 8051/31 to an external memory, port 0 provides
both address and data. The 8051 multiplexes address and data through port 0 to save
pins. ALE indicates if PO has address or data. When ALE = 0, it provides data DO- D7,
but when ALE = 1 it has address AO - A7. Therefore, ALE is used for de multiplexing
address and data with the help of a 74LS373 latch.

Port 1

Port I occupies a total of 8 pins (pins 1 through 8). It can be used as

input or output. In contrast to port 0, this port does not need any pull-up resistors
since it already has pull-up resistors internally. Upon reset, port 1 is configured as an
output port. For' ex-ample, the following code will continuously send out to port 1 the
alternating values 55H and AAH.

MOV A,
#50H BACK:
MOV Pl, A
ACALL DELAY
CPL A
SJMP BACK
Port 1 as input

To make port I an input port, it must programmed as such by writing 1 to

all its bits. In the following code, port I is configured first as an input port by writing I s
to it, then data is received from that port and saved in R7, R6, and R5.

MOV A, #OFFH ; A=FF hex

MOV P1, A ; make P1 an input port
MOV A, P1 ; get data from P1
MOV R7, A ; save it in reg R7

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ACALL DEALY ; Wait

MOV A, P1 ; get another data from P1

MOV R6, A ; save it in reg R6
ACALL DELAY : wait
MOV A, P1 ; get another data from P1
MOV R5, A ; save it in reg R5
Port 2
Port 2 occupies a total of 8 pins (pins 21 through 28). It can be used as
input or output. Just like PI, port 2 does not need any pull-up resistors since it already
has pull-up resistors internally. Upon reset, port 2 is configured as an output port. For
example, the following code will send out continuously to port 2 the alternating values
55H and AAH. That is, all the bits of P2 toggle continuously.

MOV A,
#55H BACK:
MOV P2,
A
ACALL DELAY
CPL A
SJMP BACK

Port 2 as input
To make port 2 an input, it must programmed as such by writing I to all its bits. In the
following code, port 2 is configured first as an input port by writing 1s to it. Then data
is received from that port and is sent to PI continuously.

MOV A, # OFFH ; A=FF hex

BACK MOV P2, A ; make P2 an input port by writing all ls to it

BACK: MOV A, P2 ; get data from P2

MOV P1,A ; send it to Port 1

SJMP BACK ; keep doing that

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Module 2 ECT206- Computer Architecture and Microcontroller

Dual role of port 2

In 805I-based systems, port 2 must be used along with P0 to
provide the 16-bit address for the external memory. Port 2 is also designated as A8 -
A15, indicating its dual function. Since an 8051 is capable of accessing 64K bytes of
external memory, it needs a path for the 16 bits of the address. While PO provides the
lower 8 bits via AO-A7, it is the job of P2 to provide bits A8 - A15 of the address. In
other words, when the 8031 is connected to external memory, P2 is used for the upper
8 bits of the 16-bit address, and it cannot be used for I/O.
Port 3
Port 3 occupies a total of 8 pins, pins 10 through 17. It can be used
as input or output. P3 does not need any pull-up resistors, the same as PI and P2 did
not . Although port: 3 is configured P3.0 as an output port upon reset, this is not the
way it is most commonly used. Port 3 has the additional function of providing some
extremely important signals such as interrupts. P3.0 and P3.1 are used for the.RxD
and TxD serial communications signals. Bits P3.2 and P3.3 are set aside for external
interrupts. Bits P3.4 and P3. 5 are used for timers 0 and 1.Finally, P3.6 and P3.7 are
used to provide the WR and RD signals of external memories connected in 8051-based
systems.
P1 - P3 structure and operation
Since all the ports of 8051are bidirectional they all have the following three components
in their structure:
1. D latch

2. Output driver
3. Input buffer

Port 1 structure

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Figure shows the structure of PI and its three components. The other
ports, P2 and P3, are basically the same except with extra circuitry to allow their dual
functions. In Figure notice that the Ll load is an Internal load for PI, P2, and P3. When
reading the ports there are two possibilities : (1) reading the input pin, or (2) reading the
latch.

Reading the input pin

To make any bits of any port of 8051 an input port, we first must write
a 1 (logic high) to that bit. Look at the following sequence of events to see why.

1. As can be seen from Figure bellow, a 1 written to the port bit is written to the latch
and the D latch has "high" on its Q. Therefore, Q = 1 and Q = O.
2. Since Q = 0 and is connected to the transistor Ml gate, the Ml transistor is off.
3. When the Ml transistor is off, it blocks any path to the ground for any signal
connected to the input pin and the input signal is directed to the tri-state TBl.
4. When reading the input port in instructions such as "MOVA, PI" we are really
reading the data present at the pin. In other words, it is bringing into the CPU the
status of the external pin. This instruction activates the read pin of TBI (tristate
buffer 1) and lets data at the pins flow into the CPU's internal bus. Figures 1 and
2 show high and low signals at the input, respectively.

Reading” High” at input pin (figure 1)

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Reading “low “at the input pin (figure 2)

Writing "0" to the port,

The above discussion showed why we must write”high” to a

port’s bits in order to make it an input port. What happens if we write a "0" to a port
that was configured as an input port? From Figure 3 we see that if we write a 0 (low) to
port bits, then Q = 0 and Q = 1. As a result of Q = I, the Ml transistor is "on". If Ml is
"on," it provides the path to ground for both Ll and the input pin. Therefore, any attempt
to read the input pin will always get the "low" ground signal regardless of the status of
the input pin. This can also damage the port,

( Figure 3)

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Reading latch

Since, in reading the port, some instructions read the port and others
read the latch, we next consider the case of reading the port where it reads the
internal port latch. "ANL PI, A" is an example of instruction that reads the latch instead
of the input pin. Look at the sequence of actions taking place when an instruction such
as "ANL PI, A" is executed.

1. The read latch activates the tri-state buffer of TB2 (Figure C-l7) and brings
the data from the Q latch into the Cpu.
2. This data is ANDed with the contents of register A.
3. The result is rewritten to the latch.

After rewriting the result to the latch, there are two possibilities: (1) If Q
= 0, then Q = 1 and M1 is "on," and the output pin has "0," the same as the status of
the Q latch. (2) If Q = 1, then Q = 0 and the M1 is "off," and the output pin has "I," the
same as the status of the Q latch. From the above discussion, we conclude that the
instruction that reads the latch normally reads a value, performs an operation
(possibly changing the value), and rewrites the value to the latch. This is often called
"readmodify- write,"

Reading a latch
PO structure

A major difference between PO and other ports is that PO has no

internal pull-up resistors. Since PO has no internal pull-up resistors, it is simply an

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open drain

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as shown in Figure 8. (Open-drain in MOS is the same as open-collector in TTL). Now

by writing a "I" to the bit latch, the M1 transistor is "off" and that causes the pin to
float. That is the reason why when PO is used for simple data I/O we must connect it to
external pull-up resistors. As can be seen from Figures 8 and 9, for a PO bit to drive an
input, there must be a pull-up resistor to source current.

Port 0 structure (figure 8)

P0 with external pull up (figure 9)

Two 16 bit timer or counter

The 8051 has two timers: timer 0 and timer 1. They can be used either
as timers or as event counters. In this section we first discuss the timers' registers and

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then show how to program the timers to generate time delays. 'Both timer 0 and timer
1 are 16 bits wide. Since the 8051 has an 8-bit architecture, each 16-bit timer is
accessed as two separate registers of low byte and high Byte. Each timer is discussed
separately.
Timer 0 registers
The 16.-bit register of timer 0 is accessed as low byte and high byte. The low byte
register is called TLO (timer 0 low byte) and the high byte register is referred to as
THO (timer 0 high byte). These registers can be accessed like any other register, such
as A, B, RO, Rl, R2,

THO TLO

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 0 registers
Timer 1 registers

Timer 1 is also 16 bits, and its 16-bit register is split into two bytes, referred to as TLl
(timer 1 low byte) and THI (timer 1 high byte). These registers are Accessible in the same
way as the registers of timer O.
TH1 TL1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 1 registers
TMOD (timer mode) register
Both timers 0 and 1 use the same register, called TMOD, to set the various timer
operation modes. TMOD is an 8-bit register in which the lower 4 bits are set aside for
timer 0 and the upper 4 bits are set aside for timer 1. In each case, the lower 2 bits are
used to set the timer mode and the upper 2 bits to specify the operation. Figure be low
shows TMOD register.

Bits of this register have the following function:

M1,MO;
MO and Ml select the timer mode.

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M1 M2 MODE

C/T (clock/timer)

This bit in the TMOD register is used to decide whether the timer is used as a delay
generator or an event counter. If C/T = 0, it is used as a timer for time delay
generation. The clock source for the time delay is the crystal frequency of the 8051.
GATE

The other bit of the TMOD register is the GATE bit. . GATE = 1, meaning that external
hardware is needed to start and stop the timers. In using software to start and stop the
timer where GATE = 0.
SBUF register
SBUF is an 8-bit register used solely for serial communication in the
8051. For a byte of data to be transferred via the TxD line, it must be placed in the
SBUF register. Similarly, SBUF holds the byte of data when it is received by the 805I's
RxD line. SBUF can be accessed like any other register in the 8051

SCON (Serial control) register

The SCON register is an 8-bit register used to program the start bit,
stop bit, and data bits of data framing, among other things. The following describes
various bits of the SCON register.

• SM0 - Serial port mode bit 0 is used for serial port mode selection.
• SM1 - Serial port mode bit 1.

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• SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable
bit. When set, it enables multiprocessor communication in mode 2 and 3, and
eventually mode 1. It should be cleared in mode 0.

• REN - Reception Enable bit enables serial reception when set. When cleared, serial
reception is disabled.
• TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem
of Transmitting the 9th bit in modes 2 and 3. It is set to transmit logic 1 in the 9th bit.

• RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if
9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.

• TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte
is sent. It’s a signal to the processor that the line is available for a new byte transmits.
It must be cleared from within the software.
.RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that
byte is received and should be read quickly prior to being replaced by a new data. This
bit is Cleared from within the software.
PCON (power control) register
D7 DO
SMOD --------
----------- -
PCON register is an 8-bit register. Of the 8 bits, some are unused, and
some bits are used for the power control capability of the 8051( for setting idle and
power down mode ,IDL& PD bits are used). The bit which is used for the serial
communication is D7, the SMOD (serial mode) bit

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TCON register

Figure shows the bits of the TCON register.

D7 D0
TF1 TR1 TFO TRO IE1 IT1 IE0 IT0

ITO and IT1

TCON.O and TCON.2 are referred to as ITO and ITI, respectively. These two
bits set the low-level or edge-triggered modes of the external hardware interrupts of
the INTO and INTI pins. They are both 0 upon reset, which makes them low-level
triggered. The programmer can make anyone of them high to make the external
hardware interrupt edge-triggered.

IE0 and IE1

TCON.I and TCON.3 are referred to as 1E0 and lEI, respectively. These
bits are used by the 8051 to keep track of the edge-triggered interrupt only
TRO and TR1

These are the D4 (TCONA) and D6 (TCON.6) bits of the TCON register.
We were introduced to these bits in Chapter 9. They are used to start or stop timers 0
and 1, respectively.

TFO and TF1

These are the D5 (TCON.5) and D7 (TCON.7) bits of the TCON register. They
are used by timers 0 and 1, respectively, to indicate if the timer has rolled over.

Interrupts in the 8051

There are really five interrupts available to the user in the 8051 but many
manufacturers’ data sheets state that there are six interrupts since they include reset.
The six interrupts in the 8051 are allocated as follows.

1. Reset. When the reset pin is activated, the 8051 jumps to address location 0000.

2. Two interrupts are set aside for the timers: one for timer 0 and one for timer I.
Memory locations OOOBH and 001BH in the interrupt vector table belong to
timer 0 and timer 1, respectively.

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3. Two interrupts are set aside for hardware external hardware interrupts. Pin
numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware
interrupts INTO and INTI, respectively. These external interrupts are also
referred to as EXI and EX2. Memory locations 0003H and OO13Hin the interrupt
vector table are assigned to INTO and INTI, respectively.

4. Serial communication has a single interrupt that belongs to both receive and
transfer. The interrupt vector table location 0023H belongs to this interrupt.

Interrupt vector table of 8051

interrupt Rom pin

location
Reset 0000
External hardware interrupt0(INT0)
0003 P3.2(12)
Timer 0 interrupt (TF0) 000B
External hardware interrupt (INT1)
0013 P3.3(13)
Timer interrupt (TF0) 001B
Serial communication interrupt (RI0023
or
TI)

Enabling and disabling an interrupt( IE interrupt enable Register )

Upon reset, all interrupts are disabled (masked), meaning that none will
be responded to by the microcontroller if they are activated. The interrupts must be
enabled by software in order for the microcontroller to respond to them. There is a
register called IE (interrupt enable) that is responsible for enabling (unmasking) and
disabling (masking) the interrupts. Figure shows the IE register. Note that IE is a
bitaddressable register
D7 D0
EA ------ ET2

• EA - global interrupt enable/disable:

If EA = 0 - disables all interrupt requests.
1 - Enables all individual interrupt requests.
• ES - enables or disables serial interrupt:

If ES = 0 - UART system cannot generate an interrupt.

1 - UART system enables an interrupt.

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• ET1 - bit enables or disables Timer 1 interrupt:

If ET1= 0 - Timer 1 cannot generate an interrupt.
1 - Timer 1 enables an interrupt.
• EX1 - bit enables or disables external 1 interrupt:
If EX1= 0 - change of the pin INT0 logic state cannot generate an interrupt.

1 - enables an external interrupt on the pin INT0 state change.

• ET0 - bit enables or disables timer 0 interrupt:
If ET 0=0 - Timer 0 cannot generate an interrupt.

1 - Enables timer 0 interrupt.

• EX0 - bit enables or disables external 0 interrupt:

If EX0= 0 - change of the INT1 pin logic state cannot generate an interrupt.
1 - Enables an external interrupt on the pin INT1 state change.
Steps in enabling an interrupt

To enable an interrupt, we take the following steps:

1. Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take
effect.
2. If EA = 1, interrupts are enabled and will be responded to if their corresponding bits
in IE are high. If EA = 0, no interrupt will be responded to, even if the associated bit
in the IE register is high.
INTERRUPT PRIORITY IN THE 8051
When the 8051 is powered up, the priorities are assigned according to Table. for
example If external hardware interrupts 0 and 1 activated at the same time, external
interrupt 0 (INTO) is responded to first. Only after INTO has been serviced is INTI
serviced, since INTI has the lower priority. In reality, the priority scheme in the table is
nothing but an internal polling sequence in which the 8051 polls the interrupts in the
sequence listed in Table and responds accordingly.

interrupts
Highest to lowest priority
External hardware interrupt0 (INT0)
Timer 0 interrupt (TF0)
External hardware interrupt (INT1)
Timer interrupt (TF0)

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Serial communication interrupt (RI or TI)

Interrupt priority register (IP)

D7 D0
---- ----- PT2 PS PT1 PX1 PT0 PX0

The interrupt priority register is an 8 bit register .it is used change the priority of the
interrupt in 8051.following the bits of IP register
Priority bit = 1 assigns high priority. Priority bit = 0 assigns low priority.

IP.7 --- reserved

IP.6 --- reserved

IP.5 PT2 Timer 2 interrupt priority (8052)
IP4 PS Serial port interrupt priority bit IP.3
PT1 Timer I interrupt priority bit
IP.2 PX1 External interrupt 1 priority bit

IP.I PT0 Timer 0 interrupt priority bit

IP0 PX0 External interrupt 0 priority bit

The 8051 Oscillator and Clock

The heart of the 8051 is the circuitry that generates the

clock pulses by which all internal operations are synchronized. Pins XTALl and XTAL2
are provided for connecting a resonant network to form an oscillator. Typically, a
quartz crystal and capacitors are employed, as shown in Figure The crystal frequency
is the basic internal clock frequency of the microcontroller. The manufacturers make
available 8051 designs that can run at specified maximum and minimum frequencies,
typically 1 megahertz to 16 megahertz.
The oscillator formed by the crystal, capacitors, and an
onchip inverter generates a pulse train at the frequency of the crystal, as shown in

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Module 2 ECT206- Computer Architecture and Microcontroller

Figure. The clock frequency, f, establishes the smallest interval of time within the
microcontroller, called the pulse, P, time. The smallest interval of time to accomplish
any simple instruction, or part of a complex instruction, however, is the machine cycle.
The machine cycle is itself made up of six states. A state is the basic time interval for
discrete operations of the microcontroller such as fetching an opcode byte, decoding
an opcode, executing an opcode, or writing a data: byte. Two oscillator pulses define
each state. Program instructions may require one, two, or four machine cycles to be
executed, depending on the type of instruction. Instructions are fetched and executed
by the micro controller automatically.

To calculate the time any particular instruction will take to

be executed, find the number of cycles, C, The time to execute that instruction is then
found by multiplying C by 12 and dividing the product by the crystal frequency:

Tins’ = C x 12d

Crystal frequency

Special Function Registers

The 8051 operations that do not use the internal 128-byte
RAM addresses from ooh to 7Fh are done by a group of specific internal registers, each
called a Special- Function register (SFR), which may be addressed much like internal
RAM, using addresses from 80h to FFh. Some SFRs are also bit addressable, as is

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the case

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Module 2 ECT206- Computer Architecture and Microcontroller

for the bit area of RAM. This feature allows the programmer to change only what
'needs to be altered, leaving the remaining bits in that SFR unchanged. Not all of the
addresses from 80h to FFh are used for SFRs, and attempting to use an address that is
not defined or empty, results in unpredictable results.

Name Function Internal RAM Address (HEX)

A* Accumulator OEO
B* Arithmetic OFO
DPH Addressing external memory 83
DPL Addressing external memory 82
IE* Interrupt enable control A8
IP* Interrupt priority B8
PO* Input/output port latch 80
P1* Input/output port latch 90
P2* Input/output port latch AO
P3* Input/output port latch 0B0
PCON Power control 87
PSW* Program status word 0D0

SCON* Serial port control 98

SBUF Serial port data buffer 99
SP Stack pointer 81
TMOD* Timer/counter mode control 89
TCON* Timer/counter control 88
TLO Timer 0 low byte 8A

THO Timer 0 high byte 8C

TL1 Timer 1 low byte 8B
TH1 Timer 1 high byte 8D

*Bit addressable register.

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