MAPT

Microelectronics and
Advanced Packaging
Technologies Roadmap
2023
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Acronym Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1

Application Drivers and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 2

Sustainability and Energy Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 3

Security and Privacy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 4

Digital Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 5

Analog and Mixed-Signal Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Chapter 6

Photonics and MEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Chapter 7

Advanced Packaging and Heterogeneous Integration . . . . . . . . . . . . . . . . . . 140

Chapter 8

Materials, Substrates, and Supply Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Chapter 9

Design, Modeling, Test, and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Chapter 10

Manufacturing and Process Development Metrology . . . . . . . . . . . . . . . . . . 183

Chapter 11

Workforce Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

1
Semiconductors are ubiquitous in modern society. In every hour of every day, these devices
intersect with our lives—from the timers that turn on our coffee makers in the morning to the
countless modes of transportation we utilize to move ourselves around the globe to the computers
on which we make our livelihoods and pursue our educations to the sleep apnea devices, hearing
aids, implantable medical devices, and fitness trackers that monitor and improve our health.
In industry, these devices enable high performance computers that convert data into insights,
robotics that operate precision industrial facilities, and communications networks and energy grids
that reach nearly every human being on Earth.

Today, we are pleased to release the Microelectronics and Advanced Packaging Technologies (MAPT)
Roadmap, which extends the work of the Semiconductor Research Corporation’s 2030 Decadal Plan
for Semiconductors. The Decadal Plan identified five seismic shifts in the industry related to smart
sensing, memory and storage, communication, security, and energy efficient computing. The MAPT
Roadmap summarizes the key drivers of technology progress, provides guidance for how to achieve
the technical challenges outlined in the Decadal Plan, and strategizes for developing the workforce
required to realize the promises of these innovations. These advances build upon breakthroughs
in advanced packaging, 3D monolithic and 2.5D/3D heterogeneous integration, electronic design
automation, analog and mixed signal processing, nanoscale manufacturing, new materials,
photonics and MEMS integration, and energy-efficient computing.

Innovation has always been at the very heart of the semiconductor industry. For decades, that
innovation was a quest to miniaturize devices to maximize capability. But today, as devices
approach fundamental limits of physics and myriad new uses of semiconductors are discovered,
the industry is running towards new frontiers to transform the design and production of future
microchips. On the other side of these frontiers lies a trillion dollars in annual semiconductor
industry revenue that could be achieved in a few short years.

The 2022 CHIPS and Science Act has created a monumental opportunity for the federal government
and the private sector to supercharge the U.S. semiconductor manufacturing industry and spur
world-leading innovation and growth for generations. Now is the time for bold action.

Microelectronics is already a crowning achievement of human ingenuity. It has enriched our present
and will enable our future. A new wave of innovation is on the horizon.

Sincerely,

John Neuffer Todd Younkin

President & CEO President & CEO
Semiconductor Industry Association (SIA) Semiconductor Research Corporation (SRC)

2
MAPT Roadmap Extended Executive
Committee
Victor Zhirnov (SRC) – Chair David Gundlach (NIST) Timothy Rost (Texas Instruments)

Ameen Akel (Micron) Erik Hadland (SIA) Bahgat Sammakia (SUNY Binghamton)

James Ang (PNNL) Carol Handwerker* (Purdue Univ.) Farhana Sheikh (Intel)

Muhannad Bakir (Georgia Tech) Mitch Heins (Synopsys) Ganesh Subbarayan (Purdue Univ.)

Griselda Bonilla (IBM) David Henshall (SRC) Madhavan Swaminathan (Penn State)

Henning Braunisch (Intel) Michael Ignatowski (AMD) Johanna Swan (Intel)

Jason Campbell (NIST) Matt Kelly (IPC) Min Tsao (Siemens EDA)

Timothy Chainer (IBM) Markus Kuhn (Rigaku) Brooke Tvermoes (IBM)

Ramesh Chauhan (Qualcomm) Tayseer Mahdi (Intel) George White (Georgia Tech)

Richard Chow (Intel) Mary Ann Maher (SoftMEMS) Jim Wieser (Texas Instruments)

Alain Diebold (SUNY Poly) Rafic Makki (Mubadala Technology) Chuan Xie (AMD)

Guy Eristoff (Tower Semiconductor) Dale McHerron (IBM) Jie Xue (Cisco)

Farimah Farahmandi (Univ. of Florida) Suresh Ramalingam (AMD) Todd Younkin (SRC)

Mark Fuselier (AMD) Sandeep Razdan (Cisco) Katie Yu (NXP)

Kanad Ghose (SUNY Binghamton) Ganal Refai-Ahmed (AMD) Zoran Zvonar (Analog Devices)

John Goodenough (Univ. of Sheffield) David Robertson (Analog Devices)

*Through 7/30/2023

SRC Editorial Team

Jennifer Dickens, Lisa Green, David Henshall, Mary Nichols, John Oakley, Dilcia Paguada, Michael Sullivan,
Kashyap Yellai

MAPT Roadmap was supported by the U.S. Department of Commerce, National Institute of Standards
and Technology, Advanced Manufacturing Technology Roadmap (MFGTech) Program (Federal Award ID
70NANB22H039). SRC and SIA are grateful for this support.

3
The MAPT Roadmap
A Plan to Revitalize the Semiconductor Industry for
Decades to Come
Executive Summary bring about the next generation of semiconductor innovations.”4
In other words, the current 2D hardware-software paradigm in
information and communication technologies (ICT) has reached
The U.S. semiconductor industry leads the world in fundamental
its limits and must change. Industry needed a new plan that
science and technology innovation, enabled in large part by
would replace the roadmap established decades earlier. In this
aggressive research and development (R&D) spending. The
plan it is important to identify significant trends that are driving
industry invests nearly 20% of its annual revenue in R&D each
information and communication technologies and defining
year1. In addition, Federal funding of semiconductor R&D
the roadblocks and opportunities ahead. As the first step
amplifies and catalyzes private R&D spending2. While private
Semiconductor Research Corporation (SRC), partnering with SIA,
and Federal semiconductor R&D funding have kept the U.S. near
launched a new community-wide roadmapping initiative called
the forefront of global innovation, recent years have witnessed
the 2030 Decadal Plan for Semiconductors, or Decadal Plan5.
a noticeable inadequacy in funding to bridge the widening
The Decadal Plan identified five seismic shifts to attack through
chasm between academic exploration and a commercially
innovative research and development:
viable manufacturing sector. This ominous “Valley of Death”
has increasingly hindered the pace and competitiveness of the 1. Analog Data Deluge / Intelligent Sensor Systems
domestic semiconductor ecosystem. In passing the Creating
2. Growth of Memory and Storage Demands
Helpful Incentives to Produce Semiconductors (CHIPS) Act of
2022, the U.S. government mustered bipartisan support to 3. Communication Capacity vs. Data Generation
attack this national deficiency3. The CHIPS Act is now staged to
4. Information and Communication Technologies Security
offer generational opportunities that improve the “lab to fab”
Challenges
translation of ideas to product, allowing the U.S. and its allies
to restore and reestablish leadership positions for both the 5. Compute Energy vs. Global Energy Production
R&D and manufacturing of chips, advanced packages, and the
engineered systems they create. As a direct result, the CHIPS First previewed in November of 2020, followed by the full
Act will deliver the atmosphere that drives future economic and document’s release in January 2021, the Decadal Plan outlines
national security. research priorities for each of these five seismic shifts.
Seeking to ensure sustainable growth for semiconductor and
The Moore’s Law era of electronics was guided by the ITRS, or ICT industries, the Decadal Plan informs and supports the
International Technology Roadmap for Semiconductors. For strategic visions of companies and government agencies,
approximately 40 years the focus of the entire industry was
two-dimensional (2D) transistor scaling: smaller transistors
The Decadal Plan is, by design, agnostic on specific
integrated on a single chip for greater functionality, faster
solutions; it identifies what is needed, rather than how
operation, and less power usage per transistor. The fundamental
it will be accomplished.
physical limits associated with 2D transistor scaling, however,
have been drawing the ITRS era to a close. The last ITRS report This Microelectronics and Advanced Packaging
was published in 2015. The Semiconductor Industry Association Technologies (MAPT) Roadmap continues the spirit
(SIA), the ITRS coordinator, issued a statement at that time: of the Decadal Plan and discusses how to achieve its
“Faced with ever-evolving research needs and technology system-level goals, outlining the implementation plan
challenges, industry leaders have decided to conclude the ITRS and for semiconductor industry.
transition to new ways to advance semiconductor research and

4
guiding the evolution of collaborative academic, industry, and Integration are key to meeting future microelectronics
government research programs. To this end, the Decadal Plan needs. The limits of transistor scaling will require assembling
called for a significant and immediate increase of annual U.S. separately manufactured components, called chiplets, to
federal research spending relevant to the semiconductor and create Systems in Package (SiPs) by connecting multiple
ICT industry that would continue throughout the decade. The chiplets with high-density, high-speed interconnections. This
CHIPS Act, with $11B to now invest in semiconductor R&D, can represents a radical departure from the era of including a
serve as a catalyst to meet the goals that the Decadal Plan single chiplet inside the package. Heterogeneous Integration
envisioned, but only if the dollars move into the ecosystem in thus allows systems to be scaled up in terms of both function
ways that generate a truly collaborative community, lowering and size inside a single package to realize the equivalent of
the barrier to entry and accelerating ideas to market. a single, large, and expensive chip, enabling Moore’s law of
scaling to be sustained and even surpassed.
Microelectronics and Advanced Packaging Technologies
(MAPT) is a critical multidisciplinary strategy with the potential A critical contribution of this roadmapping effort is to
to transform the design and manufacture of future microchips. assure future design, development, and manufacturing of
These transformations build upon breakthroughs in advanced heterogeneously integrated chips in the U.S. and like-minded
packaging, 3D integration, electronic design automation nations. The MAPT Technical Committee has identified the
(EDA), nanoscale manufacturing, new materials, and energy- above as key drivers of MAPT innovation and begun planning
efficient computing. Advanced Packaging and Heterogeneous related R&D efforts.

5
The MAPT Consortium includes 112 organizations with the opportunities of tomorrow in AI, 5G/6G, autonomous
representation from the relevant industry stakeholder across vehicles, and quantum computing. These next-gen
the entire value chain. Participation by academic experts breakthroughs are unachievable without major advancements
ensures the project is informed by leading-edge science and as existing hardware faces impossible constraints from
engineering in key disciplines. There are also government fundamental physical limits.
participants from agencies with missions that align with MAPT
Significantly, the MAPT Roadmap focuses explicitly on
research and development of advanced manufacturing in ICT.
sustainability as a major factor for planning future innovations.
In fact, the entire roadmap is framed around fundamental
The MAPT Roadmap is the first industry-wide 3D and practical limits of ICT sustainability, including: energy
semiconductor roadmap to guide the forthcoming sustainability3, environmental sustainability6,7, and workforce
microelectronics revolution. sustainability8.

Informed by SRC’s 2030 Decadal Plan, the Consortium The MAPT Roadmap is framed around fundamental and
has developed the MAPT Roadmap, with SRC providing practical limits of ICT sustainability:
administration, coordination, and expertise. Experts in
• Energy sustainability
Technical Working Groups, as well as Crosscut Groups,
identified technology targets/goals, assessed and debated the • Environmental sustainability
state of each technology area, determined critical application
• Workforce sustainability
drivers of MAPT, identified challenges and barriers to
advanced manufacturing, defined quantitative objectives and
metrics of progress, and prioritized overall needs. It is expected that with ongoing engagement, the MAPT
Roadmap will have a major impact on the semiconductor
The MAPT Roadmap outlines research priorities and
industry, similar to the impact of the International Technology
challenges that must be addressed to ensure sustainable
Roadmap for Semiconductors.
growth and true innovation for our industry, as well as realize

References
1
Semiconductor Industry Association (2020), https://www.semiconductors.org/wp-content/uploads/2020/06/SIA_Sparking-Innovation2020.pdf
2
Semiconductor Research Corporation 2022 Annual Report, https://www.src.org/about/corporate-annual/2022.pdf
3
A Strategy for the CHIPS for America Fund (2022), https://www.nist.gov/chips/implementation-strategy
4
Semiconductor Industry Association (2016), https://www.semiconductors.org/international-technology-roadmap-for-semiconductors-examines-
next-15-years-of-chip-innovation/
5
SIA/SRC Decadal Plan for Semiconductors (SRC 2021) https://www.src.org/about/decadal-plan/
6
Making AI Less Thirsty - https://arxiv.org/pdf/2304.03271.pdf
7
Could the world go PFAS-free? https://www.nature.com/articles/d41586-023-02444-5
8
2023 SIA/Oxford Economics Workforce report– https://www.semiconductors.org/chipping-in-sia-jobs-report/

6
Introduction
The MAPT Roadmap is organized into 11 chapters, grouped Foundational Ecosystem: Includes Chapter 8 on Materials,
into four categories as shown in the figure. Substrates, and Supply Chain, Chapter 9 on Design, Modeling,
Test, and Standards and Chapter 10 on Manufacturing and
Needs and Drivers: Serves as the input to the MAPT Roadmap Process Development Metrology.
and is framed around the Three Pillars of Sustainable
Development: Prosperity, Planet, and People. Includes Critical Enabler: Represented by Chapter 11 on Workforce
Chapter 1 on Application Drivers and System Requirements Development, focusing on future generations of talent for the
(addressing prosperity), Chapter 2 on Sustainability and benefit of society.
Energy Efficiency (addressing planet and people), and Chapter
3 on Security and Privacy (addressing people and prosperity). While the MAPT Roadmap is organized by chapters, readers
should note that there is a high level of interdependence and
Chips, Chiplets, and SiPs: Technology-centric focus that cross-referencing across the chapters. Readers are encouraged
includes Chapter 4 on Digital Processing, Chapter 5 on Analog to explore the roadmap in whatever order their interests
and Mixed-Signal Semiconductors, Chapter 6 on Photonics dictate. Editorial highlighting has been used to call out key
and MEMS, and Chapter 7 on Advanced Packaging and challenges, promising technologies, key findings, trends and
Heterogeneous Integration. needs for foundational capabilities in each of the chapters.

7
MAPT Roadmap in the context of related roadmapping activities
After the close of ITRS, there have been several follow-up by NIST in 2022-2023: the 5G/6G mmWave Materials and
microelectronic roadmapping activities, most notably the Electrical Test Technology Roadmap (5G/6G MAESTRO)3, the
Heterogeneous Integration Roadmap (HIR)1, sponsored Manufacturing Roadmap for Heterogeneous Integration and
by IEEE together with SEMI, and the American Society for Electronics Packaging (MRHIEP)4, and the Quantum Technology
Mechanical Engineers’ Electronics and Energy Efficiency Manufacturing Roadmap5. The MAPT Roadmap collaborates
Scaling (EES2) Roadmap , sponsored by Department of Energy.
2
with all the above-mentioned Roadmaps.
There are also several other related roadmaps sponsored

References
1
Heterogeneous Integration Roadmap (HIR) https://eps.ieee.org/technology/heterogeneous-integration-roadmap.html
2
Energy Efficiency Scaling Roadmap (EES2) https://www.energy.gov/eere/amo/articles/department-energy-announces-pledges-21-
organizations-increase-energy-efficiency
3
5G/6G mmWave Materials and Electrical Test Technology Roadmap (5G/6G MAESTRO) https://www.inemi.org/article_content.
asp?adminkey=cc22bf8eb1bfb8248c594509fe54dd9b&article=275
4
Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP) https://www.semi.org/en/news-media-press-
releases/semi-press-releases/ucla-and-semi-win-nist-funding-to-produce-heterogeneous-integration-roadmap
5
Quantum Technology Manufacturing Roadmap https://www.sri.com/quantum/quantum-technology-manufacturing-roadmap/

8
Acronym Definitions
2.5D IC Advanced packaging technique that combines multiple
IC dies in a single package without stacking them into BCI Brain-Computer Interface
a three-dimensional integrated circuit
BCP Block Co-Polymer
3D Three-dimensional
BEOL Back End of Line (in semiconductor process)
4G forth wgeneration wireless technology
BGA Ball Grid Array package
5G fifth generation wireless technology
Bi Bismuth (material)
6G sixth generation wireless technology
BIST Built-in Self-test
III-V compound of type III and type V elements from
periodic table bits/s, bps Bits per second

AAR Ambient Adjusted Rating BLE Bluetooth Low Energy

ABF Ajinomoto Build-up Film BMS Battery Management System

ADAS Advanced Driver Assistance Systems BoW Bunch of Wires PHY specification

ADC or A/D Analog to Digital Converter BS Bachelor of Science

ADK Assembly Design Kit BSM Backside Metal

AEC Automotive Electronics Council – a standards BW bandwidth

organization for automotive electronics. For example,
AEC-Q100 defines the standard tests for active CAD Computer Aided Design
components such as switches and power amplifiers
Cap Capacitor
(PAs); AEC-Q200 covers tests for passive devices such
as RF filters used in Wi-Fi and cellular communications. CCS Compute-Centric SiPs
AECG0 AEC-Q100 Grade 0 – reliability requirement for -40C to CD Critical Dimension (patterning, metrology)
150C ambient operating temperature range CDSAXS Critical Dimension Small Angle X-ray scattering
AECG2 AEC-Q100 Grade 2 – reliability requirement for -40C to (metrology tool)
105C ambient operating range CDU Critical Dimension Uniformity (patterning)
AES Advanced Encryption Standard CFD Computational Fluid Dynamics
AF Acceleration Factor (AF) CFET Complementary FET
AFM Atomic Force Microscopy CH Contact Holes
AI Artificial Intelligence CHIPS Creating Helpful Incentives to Produce
aJ attojoule (10-18 joules) Semiconductors
ALD Atomic Layer Deposition CMP Chemical Mechanical Planarization/polishing
ALE Atomic Layer Etching CMUT Capacitive Micromachined Ultrasonic Transducer
AlN Aluminum Nitride (material) CMOS Complementary Metal-Oxide-Semiconductor
AMMTO Advanced Materials and Manufacturing Technologies CNN Convolutional Neural Network
Office CNT Carbon Nanotube
AMS Analog/Mixed Signal COTS Commercial Off-The-Shelf
APT Atom Probe Tomography CPO Co-packaged Optics
AR/VR Augmented Reality/Virtual Reality CN Core Network
AS Application Server CPE Customer-premise Equipment
ASA American Semiconductor Academy CPU Central Processing Unit
ASD Area-Selective Deposition CRN Critical Raw Materials
ASIC Application Specific Integrated Circuit CSAM Confocal Scanning Acoustic Microscopy
ASIP Application Specific Instruction set Processor CTE (ch. 8) Coefficient of Thermal Expansion
ATE Automated Test Equipment CTE (ch. 11) Career And Technical Education
Au Gold material CTI Comparative Tracking Index

9
Cu Copper (materials) EDFA Erbium Doped Fiber Amplifier
CUF Capillary Underfill EDP Energy-Delay Product
CuP Copper Pillars EE Electrical Engineering
CXL Compute Express Link EES2 Energy Efficiency Scaling for Two Decades
EIRP Effective Isotropic Radiated Power
D2D Die-to-Die ENEPIG Electroless Nickel / Electroless Palladium / Immersion
D2W Die-to-Wafer Gold

DAA Digitally-assisted Analog ENIG Electroless Nickel/Immersion Gold

DAC Digital to Analog Converter EM Electromagnetic

dB decibels – logarithm of a ratio EMC Epoxy molding compound

DARF Digitally Assisted RF EMIB Embedded multi‐die interconnect bridge

DARPA Defense Advanced Research Projects Agency ESD Electro-static Discharge

DCM Digital Code Modulation EUV Extreme Ultraviolet

DEI Diversity, Equity and Inclusion EV Electric Vehicle

DERs Distributed Energy Resources EVB Evaluation Board

Df Imaginary part of dielectric constant FC Flip Chip

Dk Real part of the dielectric constant FDA Food and Drug Administration

DFM Design for Manufacturability FDD Frequency Division Duplexing

DFT (ch. 2) Density Functional Theory FDSOI Fully-depleted Silicon-on-Insulator

DFT (ch. 9) Design for Test FE, Fe Ferroelectric

DIB Dual Ion Beam FeFET Ferroelectric FET

DLL Delay-Locked Loop FEM Finite Element Method

DLP Digital Light Processing FEOL Front End of Line (in semiconductor process)

DLRM Deep Learning Recommendation Model FERAM Ferroelectric Random Access Memory

DNN Deep Neural Network FET Field-effect Transistor

DoD Department of Defense FHE Fully Homomorphic Encryption

DoS Denial-of-Service FIB Focused Ion Beam

DRAM Dynamic Random Access Memory FinFET field effect transistor built as a “fin” vertically

DRE Destruction or Removal Efficiency fJ/op femto (10-15) Joule per operation

DMR Digitally Modulated Radar FLOPs Floating Point Operations

DNA DeoxyriboNucleic Acid FoM Figure of Merit

DOE Department of Energy FPGA Field-Programmable Gate Array

DOF Depth of Focus FTJ Ferroelectric Tunnel Junction

DPD Digital Pre-Distortion

DPU Data Processing Unit GaN Gallium Nitride (transistor material)

DRC Design Rule Checking Ga2O3 Gallium Oxide (transistor material)

DSA (ch. 1) Domain-Specific Accelerator/Architecture GB Giga Byte (109)

DSA (ch. 3) Digital Signature Algorithm Gbps Gigabits Per Second

DSA (ch. 4) Directed Self-assembly GDDR Graphics Double Data Rate

DSP Digital Signal Processing GDSII Graphic Database System Information Interchange

DTC Deep Trench Capacitor GHz giga-Hertz (109)

DTCO Design and Technology Co-Optimization GHG Greenhouse Gas

DVFS Dynamic Voltage and Frequency Scaling GNN Graph Neural Network

DWDM Dense Wavelength Division Multiplexing GPU Graphics Processing Unit

GSPS, GS/s Giga-samples per second (109)

EB Exabyte (1018 Bytes) GW Giga Watt (109)

ECE Electrical and Computer Engineering GWP Global Warming Potential

EDA Electronic Design Automation

10
HAST Highly Accelerated Stress Test LF Lead Frame Package
HBM High Bandwidth Memory LGA Land Grid Array Package
HBM3 High Bandwidth Memory 3 is a memory standard for LiDAR Light Detection and Ranging
3D stacked DRAM LLM Large Language Model
HBT Hetero-junction Bipolar Transistor LNA Low Noise Amplifier
(HD) FOWLP High Density Fan-Out Wafer Level Packaging LNO Lithium Niobate (material)
HEMT High Electron Mobility Transistor LO Local Oscillator (in RF circuit)
Hf Hafnium (material) LOS Line of Sight
HI Heterogeneous Integration L/S Lines and Spaces
HIR Heterogeneous Integration Roadmap LSC Land-Side Capacitor
HPC High Performance Computing LTS Low-Temperature Solder
HTF Heat-Transfer Fluids LWC Lightweight Cryptography
HTSL High Temperature Storage Life LVS Layout-vs-schematic (design)
HVM High-volume Manufacturing
HW Hardware MAC Multiply–Accumulate operation
MAPT Microelectronics and Advanced Packaging
IC Integrated Circuit Technologies
ICT Information and Communication Technologies MB Motherboard
IEEE Institute of Electrical and Electronics Engineers Mbps Million bits per second
IGBT Insulated-Gate Bipolar Transistor MCM Multi-Chip Module
IHS Integrated Heat Spreader MDM Medical Device Manufacturer
InP Indium Phosphide (transistor material) MIM Metal-Insulator-Metal
INT Integer MEMS Micro- electromechanical systems
I/O Input / Output MIMO Multiple-Input and Multiple-Output
IoT Internet of Things ML Machine Learning
IP or IP block semiconductor Intellectual Property core MLCC Multilayer Ceramic Capacitor
IPDs Integrated Passive Devices MLSE Maximum Likelihood Sequence Estimation
IPCC UN Intergovernmental Panel on Climate Change MOSFET Metal Oxide Semiconductor Field-Effect Transistor
IR Infrared mm-Wave millimeter wave
IVR Integrated Voltage Regulators MPP Massive Parallel Processor
MRAM Magnetic Random Access Memory
J Joule MS Master of Science
MSPS, MS/s Mega-samples per second (106)
k Dielectric constant MTJ Magnetic Tunnel Junction
K-12 Kindergarten to 12th grade MUF Mold Under Fill
KEM Key Encapsulation Mechanism MW mega watt power (106 watts)
KGD Known Good Die mW milli watt power (10-3 watts)
KSA Knowledge, Skills, and Abilities
kSPS, kS/s kilo-samples per second (103) NA Numerical Aperture (optics)
NAND flash highest-density silicon-based electronic nonvolatile
L4 Level 4 of driving automation memory

L5 Level 5 of driving automation Ni/Au Nickel/Gold

LDE Layout Dependent Effects NICE National Institute of Cybersecurity Education

LDMs Low-Dimensional Materials NIST National Institute of Standards and Technology

LDMOS Laterally-Diffused Metal-Oxide Semiconductor nJ nanojoule (10-9 joules)

(transistor) NLoS Non Line of Sight
LDO Linear/Low Drop-Out Voltage Regulator NLP Natural Language Processing
LER, LWR Line Edge/Width Roughness nm nano meter (10-9 meters)

11
NMOS n-channel Metal-Oxide-Semiconductor transistor PUF Physical Unclonable Function
NN Neural Network PUE Power Usage Effectiveness
NoC Network-on-Chip PVT Process, Voltage, Temperature
NSF National Science Foundation PZT Lead-Zirconia Titanate (material)
NSP Network Security Platform Qdot or QD Quantum Dot
NSTA National Science Teaching Association QFN Quad Flat no-Lead package
NTN Non-terrestrial Network
NVM Nonvolatile Memory R&D Research and Development
NVRAM Nonvolatile RAM RAM Random Access Memory
RAN Radio Access Network
OCM Original Component Manufacturer RCS Radar Cross-Section
ODSM Open Domain-Specific Architecture RDL Redistribution Layer
OEM Original Equipment Manufacturer ReRAM, Resistive Random Access Memory
OEO Optical to Electrical to Optical RRAM

OPA Optical Phase Array RF Radio Frequency

OPCF Open Platform Communications Foundation RLS Resolution, Line-width roughness, Sensitivity
(patterning)
ORNL Oak Ridge National Laboratory
ROI Return on Investment
OSAT Outsourced Semiconductor Assembly and Test
(manufacturing) RoT Root of Trust

OSP Organic Solderability Preservative RTL Register-transfer Level is a design abstraction which
models digital circuits
OTA Over-The-Air

SAC Tin-Silver-Copper (solder alloy materials)

PA Power Amplifier (in an RF cicrcuit)
SCVR Switched Capacitor Voltage Regulator
Pb Lead (material)
SDL Schematic-Drive-Layout (design)
PCB Printed Circuit Board
SEM Scanning Electron Microscopy
PCAST President’s Council of Advisors on Science and
Technology SEU Single Event Upset

PCIe Peripheral Component Interconnect Express SEMI Semiconductor Equipment and Materials International
(organization)
PCM, PCRAM Phase Change Memory / RAM
SFDR Spurious-free Dynamic Range
PDK Process Design Kit
SFF Small Form Factor
PE Processing Element
Si Silicon (material)
PFAS Per- and poly-fluoroalkyl substances
SIA Semiconductor Industry Association
PhD Doctor of Philosophy
SIRI Smart Industry Readiness Index
PHY Physical Layer
SiC Silicon Carbide (transistor material)
PIC Photonics IC
SiCN Silicon Carbon Nitride (material)
PIM Processing In Memory
SiGe Silicon Germanium alloy (transistor material)
PiP Package in Package
SIMO Single Input Multiple Output
PIPES Photonics in the Package for Extreme Scalability
SIMS Secondary-ion mass spectrometry
PLC Programmable Logic Controller
SiP System in Package
PLL Phase-Locked Loop
SiOx Silicon Oxide (material)
PLP Panel Level Packaging
SMT Surface-mount Technology
PMCW Phase-modulated Continuous Wave
Sn-Cu Tin-Copper (material)
PMU Power Management Unit
SNN Spiking Neural Network
PMUT Piezoelectric Micromachined Ultrasonic Transducer
SNDR Signal-to-Noise plus Distortion Ratio
PoP Package on Package
SoC System on Chip
PPM Parts Per Million
SPICE transistor / component level simulation program
PQC Post-Quantum Cryptography
SPM Scanning Probe Methods (metrology)
PSA Power Side-Channel Attack

12
SOI Silicon-on-Insulator
SONOS Silicon–Oxide–Nitride–Oxide–Silicon (NVM structure)
SOT Spin-Orbit Torque
SRAM Static Random Access Memory
SRC Semiconductor Research Corporation
STCO System Technology Co-Optimization
STEM (ch. 10) Scanning Transmission Electron Microscopy
STEM (ch. 11) Science, Technology, Engineering and Math
STM Scanning Tunneling Microscopy
SW Software
SWAP-C Size, Weight, Power, and Cost
TBD To Be Determined
Tbps Terabit-per-second
TDP Thermal Design Power
TEM Transmission Electron Microscopy
TCAD Technology CAD
TDD Time Division Duplexing
THz Terahertz (1012)
TID Total Ionizing Dose
TIM Thermal Interface (Material)
Tj Junction temperature
TLPS Transient Liquid Phase Sintering
TMDs Transition Metal Dichalcogenides (a class of materials)
TN Terrestrial Network
TO Transistor Outline Package
TOPS Tera Operations per Second (1012)
TSM Topside Metal
TPU Tensor Processing Unit
TSVs Through-Silicon-Vias

UCIe-A Universal Chiplet Interconnect Express specification

for Advanced Packaging
USB Universal Serial Bus
UVM Unified Virtual Memory
UWBG Ultra Wide Band Gap (transistor technology)

VCSEL Vertical Cavity Surface Emitting Laser

VLIW Very Long Instruction Word
VLSI Very Large Scale Integration
VR Virtual Reality

WB Wafer-bonded
WBL Work Based Learning
WFD Workforce Development
WG Working Group

XPS X-ray Photoelectron Spectroscopy

XR eXtended Reality

13
Chapter 1
Application Drivers and
System Requirements
1.1. Introduction especially where a new algorithm completely changes the
landscape of a solution space. Evolutionary changes often
Architects and end users alike have enjoyed increased system manifest as increasingly larger data or greater performance
performance and increased energy efficiency over the past many requirements, whereas revolutionary inflection points—like
decades because of transistor scaling according to Moore’s law. AI inference and training, including large language models—
Additionally, as application domains continue to expand beyond introduce brand-new compute requirements, systems design,
traditional computing and toward more bio-inspired and bio- hardware specialization, and algorithms.
aware solutions, systems and the elements that comprise them
must better enable these use cases. As the industry transitions One guiding goal across all workloads and use cases considered
to a new era of computing systems and applications, we must is a strong need for energy proportionality. As mentioned in
advance computing systems with a full-stack approach, where the Decadal Plan for Semiconductors, energy efficiency must
all layers, from application to bits, are explored together. This improve dramatically to support the current trajectory of
chapter considers the impacts of a wide variety of application compute demands37. Barroso and Hölzole advocate for energy
domains to drive the impact of future applications, as well as to proportional computing in Data Centers38 where computer
influence the direction of key enabling technologies covered by systems scale energy linearly with usage. This observation would
the MAPT roadmap. These include Data Center and HPC, mobile benefit systems across all workloads considered in this chapter.
communications and infrastructure, edge and IoT, automotive,
bio-applications and health, and defense and harsh environments. Systems of 2037 must exhibit true energy proportionality:
Energy per operation should remain constant for all possible
Each of these application areas will evolve in distinct ways utilization targets.
and will require domain-specific systems to achieve next-level
performance. It is critical to understand these workloads, the Furthermore, another overarching goal across all systems use
systems that will be built to run them, and their implications cases is to ensure that future systems, chips, and packages
for forward-looking technologies. are developed to increase performance with reasonable cost.
Refai-Ahmed, et. al. suggest that there is a potential of 30-
Systems and applications can scale incrementally by increasing 40% performance improvement between generations51. It’s
requirements gradually over time or through an inflection, important to balance performance gains with cost increases,

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 14
ensuring that the incremental cost of a chip doesn’t exceed to continue current application scaling trajectories.
the global inflation rate. Designs must consider technology Optimized HI and 3D-stacked architectures, both for logic
nodes, silicon architecture, package integration, product and memory, are necessary, and the thermal implications of
lifetime, operational expenses, and capital expenses. Overall, these architectures must be addressed.
the roadmap should prioritize flexibility to achieve ongoing
• Following this, data movement continues to impede the
performance increases while effectively managing costs.
energy efficiency and performance of numerous systems,
especially as it relates to the lack of memory bandwidth
As detailed in this chapter, each application driver and
scaling and inter-chiplet communication. Advances must
associated system will evolve in a different manner, as they
address the cost of interconnects, whether they span
possess diverse requirements and drive different use cases.
compute and memory, compute chiplets, wireless mobile/
Common conclusions are highlighted across all application
IoT devices, or Data Centers. 3D-stacked architectures and
drivers and systems requirements:
new techniques like processing- or compute-in-memory
• Innovative architectures, like domain-specific accelerators, are must play a role in future computing solutions.
required to continue to enable new use cases across application
• Biological use cases, as well as defense and harsh
classes, including XR, HPC, Data Center workloads, etc.
environment use cases, have stringent packaging
• Following this, software/hardware codesign is paramount in requirements (e.g., biocompatibility and rad hardness) whose
defining new architectures, especially HI systems, domain- requirements do not intersect with conventional computing.
specific architectures, analog computing, etc. The resulting
• For many workload classes, new technologies must be cost-
innovations must be easily programmable, and the focus on
effective to be broadly deployed.
the associated software stack cannot be overstated.

• Many application classes are limited in interconnect and The following table summarizes the findings from this chapter.
memory bandwidth. Transistor scaling alone is not sufficient

Table 1.1: Workloads and systems environments all exhibit different characteristics and requirements. This table
attempts to simply represent the future requirements for the application drivers and systems requirements
evaluated in this chapter, with each application class and system being expanded upon throughout the chapter.

Memory Storage
Key Metrics
Compute Bandwidth Bandwidth Interconnect Reliability
Application Class Specialization Required (Cost, Power,
Limited / Capacity / Capacity Limited Considerations
Performance)
Limited Limited
H H M H L Architectures + hardware/ Performance /
Data Center: AI
M – Large software codesign Power
training / inference
Models
Data Center: Cloud H H L H L Architectures + hardware/ Performance /
graphics / XR software codesign Power
HPC: Engineering H H H H M Architectures + hardware/ Performance /
simulation <100 FIT software codesign Power
Automotive: ADAS, H H L M H Architectures + hardware/ Performance /
entertainment, <100 FIT software codesign Power
networking,
automation
Automotive: L L L M H Analog and power Power / Cost
Electrification electronics
IoT / Edge L L L M M None Power / Cost

Bioapplications L L L M M Packaging Cost/Other

and health
H H M H L Architectures + hardware/ Performance /
Mobile
software codesign Power
Communications H H L H H Thermals Performance
and infrastructure / Cost
Defense and harsh M M L M H Packaging, reliability, and Power / Cost
environments thermals

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 15
1.2. Data Center and High- hardware and software limitations, models of this scale
drive longer training times, with many modern state-of-
Performance Computing (HPC) the-art models requiring more than 1024 floating-point
operations (FLOPs) to train, taking weeks or months in
Computing technologies are main drivers for many of
Data Centers with hundreds of graphics processing units
the world’s technological advances. In many cases, these
(GPUs) or special-purpose, domain-specific inference
application areas require broad advances across the entire
and training accelerators. In the absence of advances in
compute stack, including compute engines and processors,
hardware, application and model developers must rely on
high-bandwidth and efficient memories, high-density
new algorithms—or, in the AI space, new building blocks
storage technologies, high-speed and efficient network
and model organizations—to advance model capacity and
infrastructure. paired with a With this framework, Data
task-level accuracy. The Switch Transformer13 represents
Center and HPC applications often span cores, sockets,
one such example that enables sparse activations of smaller,
platforms, racks, and entire Data Centers.
specialized, and easier-to-train submodels, which are
composed to form models exceeding a trillion parameters.
An endless diversity of applications spans the Data Center
In the same way that the general-purpose processor
and HPC space:
performance boom in the early 2000s was enabled by
1. Data analytics, both structured and unstructured. relatively easy transistor scaling, although algorithm-level
advances are possible, researchers can often advance the
2. Biological, genome-based, and other similar analysis,
state-of-the-art more quickly with more capable hardware.
including an understanding how these function in humans
and beyond.
State-of-the-art AI models change at a rapid pace, with
3. Simulation techniques, including molecular dynamics, exponential growth in publications over time14. Although it
computational fluid dynamics, aerodynamics, and structural is unlikely that the number of parameters per network will
analysis. continue to scale without significant innovation, enabling
models with considerably greater numbers of parameters
4. Large-scale inference and training, including large
will enable different classes of models to scale for longer
language models, natural-language processing, image
periods without substantial changes to the underlying
recognition, recommendation systems, etc.
model architecture.
5. Entertainment and gaming, including eXtended Reality
(XR), cloud-based gaming, and rendering. Since learning cycles for large AI models are critical in
evolving model architectures, it will be important to train
6. Applications enabled by quantum computing, which
models of increasing size in shorter periods of time. The
require unique operating conditions, close to zero Kelvin.
most sophisticated Data Centers should be able to train a
500 trillion parameter AI model in a week in 2037.
Future Data Center and HPC use cases will strongly benefit
from advances in scalability, reliability, energy efficiency,
In contrast with training, once trained, models are queried
application latency, and application throughput. As in other
in an inference step to execute predictions. As a workload,
application domains, end-to-end Data Center metrics rely
inference exhibits different performance characteristics
heavily on the application or workload under execution. This
than training, and often employs a different domain-specific
chapter will discuss the implications of popular workloads as
accelerator. For inference, both inference latency and
representative use cases.
inference throughput matter. Users expect an answer in
a short period of time, especially when used for search15
1.2.1 AI Training and Inference
(<100s of ms for a search query). Even on state-of-the-art,
AI training and inference has evolved greatly over the past domain-specific hardware capable of several petaFLOPs
several years. Increases in both complexity and capability of low-precision arithmetic with hundreds of gigabytes of
of AI workloads drive prevalent deep neural network (DNN) high-bandwidth HBM, inference for many Data-Center-class
models like GPT-4, PaLM, LLaMA, and other large language models, is limited by either memory bandwidth or compute
models (LLMs). Some of the largest LLMs require hundreds throughput16. Increasing model sizes will only exacerbate this
of billions of parameters: GPT-3 at 175B10, Megatron- problem, which will require continued scale-out of platforms
Turning NLG (530B) , and LLaMA (65B) . Given current
11 12
at untenable increases in energy and interconnect overhead.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 16
 Table 1.2: Scaling challenges of AI workloads.

Facet Scaling bottleneck Recommended solutions

Continued CMOS scaling, reducing area and improving

High-operational-intensity models limited by compute
Compute scaling energy; 3D-based packaging technologies, which enable
unit scaling
densely interconnected compute
Low-operational-intensity models limited by availability More efficient chip-to-chip interfaces for 2.5D integration
Parameter scaling of parameters, often stored in DRAM when SRAM is too between memory and compute; heterogeneous,
small potentially 3D, integration of memory and compute
Increased chip- or rack-level interconnect technologies;
Model capacity DLRM-class models limited by availability of co-located
improved memory density, either through emerging
(e.g., DLRM) weights
memories or 3D integration

Even with parameter reduction techniques (e.g., pruning, See section 1.6 for more detail regarding XR and its
quantization, and distillation), further innovations are associated bottlenecks. However, for the cloud rendering use
required to continue today’s pace. case, Data Centers must be equipped with very-low-latency
communication fabrics (<<10ms).
In addition to LLMs, alternate classes of models like
recommender systems also dominate Data Center cycles, 1.2.3 Engineering Simulations
with 24% of Google’s accelerators executing Deep Learning
A large fraction of high-performance computing workloads
Recommendation Model (DLRM) tasks16. Users employ DLRMs
includes engineering simulations. Supercomputers are
to provide recommendations to users, from ads and social media
often constructed with engineering simulation workloads
content to movies and TV shows. As such, they are essential in
in mind. This section motivates workload trends and system
various personalized applications, including e-commerce, music
requirements for various classes of engineering simulations,
and video streaming services, social media, etc. Embeddings or
including computational fluid dynamics (CFD), structural
feed-forward layers often dominate DLRM-class models, which
analysis, multi-physics computation, electronic design
often consume significant memory capacity but still require
automation (EDA), and weather prediction.
good memory latency and bandwidth characteristics.

To enable future HPC workloads, this workgroup envisions a

1.2.2 Cloud-based Graphics and eXtended
zettaflop supercomputer operating within ~500MW of power.
Reality (XR)
Emerging virtual and augmented reality (VR and AR, Computational fluid dynamics simulations study the flows of
respectively, or XR to contemplate both) use cases continue fluids, which can be computationally intensive, often scaling
to create new requirements for Data Center architecture and out to achieve higher memory bandwidth at a fixed rate per
performance. Up-to-date XR assets must be stored and served core17. Multi-physics simulations study the interactions of
in Data Centers in the same way that transport maps are stored. multiple physical phenomena, including fluid flow, heat transfer,
Additionally, in contrast with traditional local rendering use and electromagnetics. These workloads can often be more
cases, cloud gaming aims to render all graphics at the Data computationally intensive vs. CFD, but with very low operational
Center and transmit completed frames to end users. As a intensities18. This implies that current memory bandwidth
concrete, business-critical example, the same technologies capability limits scaling in forward-looking systems. EDA,
enable digital twin use cases across various market segments. driven primarily by design-rule complexities and the challenges
Server-side rendering for XR and cloud gaming both require brought forward by heterogeneous integration, continues
transmit and synthesis of inputs from users, rendering of the to be compute intensive and has not yet been accelerated by
next frame(s) and transmit of the final frames to each user. domain-specific accelerators. To this end, continued transistor
scaling and increased interconnected compute density through
To accommodate cloud-based rendering for graphics and heterogeneous integration will improve performance of
XR workloads in 2037, the communication building blocks EDA workloads. Weather prediction aims to predict weather
and rendering capabilities must be capable of a 10ms phenomenon with real-time updates at high accuracy, which is
end-to-end frame-rendering time, with a specific focus on often compute-limited. Although limited by current systems
communication latency. capabilities, revolutionary trends in weather prediction aim

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 17
to use spatial transformer models to drive physics-inspired • Level 1 (Driver Assistance): Has a single automated system
weather forecasting . In addition to trends in AI workloads,
39
to control speed, but human manual control is required for
continued transistor scaling and increased logic density through all other functions.
heterogeneous integration will improve workloads in this area.
• Level 2 (Partial Driving Automation): Performs steering
assist and automatic acceleration and braking, but human

1.3. Automotive manual control of the vehicle is required.

• Level 3 (Conditional Driving Automation): Controls most

Between 2023 and 2037, automobiles will be transformed
driving tasks, but human control is still required.
in almost every way to further improve efficiency, safety,
driver experience, and sustainability, as we drive toward • Level 4 (High Driving Automation): Controls all driving tasks,
a world in which vehicles are perfectly safe with zero but georeferencing and human override is required.
emissions. Many of these changes will impact other
• Level 5 (Full Driving Automation): Controls all driving tasks
transportation modes, including commercial and industrial
without human intervention.
vehicles, motorized scooters, and aviation. In short, vehicles
will become more autonomous, sustainable, networked, and Table 1.2 summarizes key automotive trends and their impact
connected, driving special requirements for semiconductor on microelectronic technology and package requirements.
devices and packaging. Figure 1.1 summarizes some of the Although other applications also drive the need for HCP,
upcoming trends seen by many in the industry. cost-effective heterogeneous integration and integrated
high-voltage capabilities, these requirements will be pushed
The levels of vehicle autonomous control achieved by Advanced in unique ways as vehicles evolve over the next 10-20 years.
Driving Assistance Systems (ADAS) have been categorized into
six levels, summarized below. The industry aims to achieve a Increased performance at greater energy efficiency will be
fully autonomous vehicle without requiring human intervention. required to advance widely available ADAS beyond current
capability levels.
• Level 0 (No Driving Automation): Functions are manually
controlled.
The ADAS community aims to enable an energy-efficient,
fully connected, cost-effective, software-defined, Level 5

Figure 1.1: Major automotive trends across the next 15 years.1

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 18
 Table 1.3: Requirements unique to automotive technical trends.

Autonomous Networked Sustainable Connected

Intra-vehicular networking Carbon-neural transport: Infotainment and Vehicle-to-

Purpose ADAS and safety
and software-define vehicles electrification and hydrogen Everything (V2X)
Requirements Synthesize from multiple More sophisticated zonal or Manage battery lifecycle: Increased connectivity to
and bottlenecks sensor sources: domain controllers for more enable V2X features in
More complex local or
sophisticated sensor and communication with other
• Real-time environmental cloud-connected battery
response networks vehicles, infrastructure,
modeling management systems,
pedestrians, and external
aimed at increasing battery
• Path planning networks.
lifecycles
• Low-latency, high-
bandwidth sensor-
compute connectivity

autonomous vehicle with cost characteristics appropriate of low-latency vehicle control. Given the number of sensors
for a mass market vehicle by 2035. required, new, domain-based and zonal architectures will
require ~100Gb/s intra-vehicle networks. Coupled with high-
The following table describes 5-, 10-, and 15-year requirements bandwidth wireless internet and infrastructure connections,
as incremental steps towards achieving this grand challenge. these capabilities will enable software-defined vehicles,
immersive infotainment, and new use models (shared
To achieve level-five autonomy, vehicles will require enormous ownership, rideshare, etc.). Legislation and an increased
processing power: hundreds of general-purpose TFLOPS desire for sustainability will drive adoption of carbon-neutral
for sensor fusion across tens to hundreds of sensors and propulsion, including battery- and fuel-cell-EVs, which
specialized, domain-specific processing of sensor data to will also require significant increases in processing power.
model the surrounding environment and to direct all aspects Overall, these capabilities will require performance similar

Table 1.4: Automotive-driven technology requirements deployed in the median automobile over the next 15 years.

Technology
2023 2027 2032 2037
attribute
ADAS level
(widely Level 1-2 Level 2-3 Level 3-4 Level 5
available)
Compute 250 TOPS >2-5 TFLOPS >10 TFLOPS >100 TFLOPS
performance

Network speed 10 Gbit/sec 100 Gbit /sec

Architecture and Up to four-core, 28/40nm, Up to eight-core, sub-20nm 10nm, domain-specific Sub-5nm, domain-specific
semiconductor embedded microcontrollers MPUs architectures architectures
requirements (MCUs)
Advanced Monolithic designs or board- Reduced-cost, chiplet- Better integration with high- Reduced power and cost
packaging and level integration; system-in- enabled, SiP designs with performance, high-capacity and higher-performance
heterogenous package (SiP) solutions too better analog, HV, and RF memory below cost of communication through
integration expensive integration monolithic designs more aggressive in-package
integration

Higher voltage Some logic platforms limited Better chiplet integration Better chiplet integration for 2.5-3.3V capability with more
IO to 1.8V for 2.5-3.3V capability with advanced logic nodes
advanced logic nodes
High voltage 5V analog capability; Specialized analog at 120V; Increased support for high kV capability for EVs
analog specialized analog at ~80V; initial support for kV range
early adoption of 400V in for EVs
EVs

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 19
 Figure 1.2: Technology enablement required for the path to level 5 autonomous driving.2

to modern high-performance compute systems with battery- analog capabilities for battery management, NVM, sensor
operated energy consumption requirements. Associated development, among other capabilities. Infotainment and
automotive environment requirements will include a wide other connected vehicle functions will require increased
temperature range (-40C to 150C junction temperature), memory capacity requirements, both in byte-addressable
elevated quality and reliability targets, elevated functional memory and block storage. All of this will demand increased
safety and security, and strict thermal management limits. integration and interconnection of heterogeneous functions,
Figure 1.2 illustrates these predictive requirements overlayed including NVM, sensors, and analog/RF, and compute. Real-
with levels of autonomy. To achieve this level of autonomy time functions require low-latency operations across these
and connectedness, the vehicle of 2035 must become a automotive capabilities, requiring close proximity, high
portable data center on wheels. data-transfer bandwidth, and reduced power consumption
and dissipation. While continued monolithic integration
Similarly, increased levels of autonomy will require will partially enable these capabilities, advanced, multi-die
integration of high-capacity, better integrated (e.g., near- packaging will enable cost-effective interoperability and
sensor), emerging (e.g., reduced latency) volatile and/ reuse. It is critical that these multi-die solutions scale to meet
or non-volatile memory and mmWave, as well as other the power and cost requirements for automotive systems.
RF communication and ranging technologies. Given the
communication requirements of interconnected vehicles, Finally, to achieve automotive industry goals by 2035, higher
the transition from analog modulation techniques to digital voltage analog will be required, including increased IO
code modulation technologies, including DCM, have the voltages on advanced logic, 3.3V/5V analog for sensor data
advantage of leveraging advanced CMOS scaling for greater processing, and 20V/48V—and up to 800V or above—needed
power efficiency and improved interference performance. for EVs and battery management.
Advanced packaging techniques will further miniaturize
sensing modules and reduce costs 4. As the number of sensors Enable mass market automobiles with precision and high-
increase, fully networked vehicles will drive the need for voltage analog circuits that operate at optimal voltages to
high speed PHYs and related hardware. EVs and other drive increased efficiency, performance, and cost by 2035.
sustainable transport technologies will require precision

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 20
Security and privacy requirements must be bolstered in To maintain sustainability and energy-efficiency goals of
future automotive systems, especially as vehicles approach 2035, the industry should aim to maintain electric vehicle
levels of autonomy with no driver interaction expected. energy efficiency above 85%.

Automotive security is critical for widespread adoption of In summary, automotive applications for future cars and
autonomous and connected driving, ranging from trusted trucks will continue to leverage developments in other
supply chain and secure hardware to malware and virus application areas, including high-performance computing
detection. Also critical is the prevention of attacks on cloud systems, but they will drive unique requirements that must
services and infrastructure, as well as robustness in the be met while maintaining performance, power, cost, security,
presence of targeted attacks that can disrupt traffic and and efficiency gains. These advances will also benefit other
threaten national security by causing widespread gridlock. vehicle types (scooters, e-bikes) and transportation modes
Past work has shown that automotive security had largely (long-haul trucks, trains, aviation, aerospace, and maritime).
been considered an afterthought5. Both physical hardware
security and defensive programming techniques will play key
roles in securing future autonomous systems. For example, 1.4. IoT and Edge
future ADAS systems must address physical attacks that
The next several decades will see electronics integrated into
compromise or alter the data from a sensor, those that alter
nearly every terrestrial location, including natural locations
the behavior of neural networks by influencing inputs or
that must be maintained and protected. In short, electronics
changing weights6, and denial-of-service attacks that flood
will be truly ubiquitous. We cannot predict every application
in-vehicle interconnects.
for electronics across every industry, but we can understand
the broad expectation that electronics enable enhanced
The sustainability of automobiles includes manufacture,
observations of environments and materials, automation of
operation, and recycling throughout the vehicle lifecycle. The
processes, automation of decision making, and an overall
manufacture of automobiles requires assembly of a multitude
amplification of human effort. Accounting for the desire
of materials/components, including metals, plastics, glass,
to observe and interact with a diverse set of processes and
chemicals, electronics, batteries, etc., all of which require
systems, it’s obvious that requirements for small unintrusive
varying amounts of carbon to produce. The operation of
electronics, including internet-of-things and edge computing
automobiles produces a carbon footprint that depends upon
use cases, will become more demanding over time.
the vehicle size, weight, performance, and energy source
(e.g., gas, diesel, hydrogen, electric). Another factor is vehicle
IoT and edge computing occupy emerging market spaces
utilization, which may be revolutionized by new models for
adjacent to many established markets, such as industrial
ownership and usage enabled by autonomous vehicles. Finally,
automation and personal electronics. IoT and edge computing
the recycling of automobile components is a key part of the
include a complex system of technological and other
vehicle ecosystem that can be optimized by design choices.
components closely coupled to user behaviors. This area
is typified by markets and applications that sit at the edge
To illustrate the role of sustainability in all-electric vehicles,
of what is possible and economical in close integration of
it’s helpful to explore the factors driving energy efficiency.
unconventional and conventional semiconductor components.
EVs can convert more than 77% of electric energy provided
As time goes on, the leading edge of unconventional
from the grid to power at wheels. In contrast, gasoline engine
integration will expand, leaving behind new markets and new
vehicles covert 12-30% of chemical energy of gasoline fuels
conventions for semiconductors.
to power at the wheels3. Losses from battery charge and
discharge totals about 10%, plus 18% loss from the electric
Economically, the outcome of integrating these technologies
motor drive system. The additional electricity usage of
is referred to as the fourth industrial revolution, with a
autonomous, networked EVs must come from the remaining
substantial commercial impact from the combination of
77% electricity used to power the wheels, totaling an
sensors, automation, digitization, and intelligence. The
additional 10-20% overhead, or 5-10 kWh for an average EV
Smart Industry Readiness Index (SIRI) is a framework for
battery capacity of 50 kWh. Even considering the efficiency
understanding the process from which industry moves from a
gains of regenerative breaking, this reduces the overall
completely manual process to one which takes full advantage
electric energy efficiency to 57-67% of total available energy.
of automation and intelligence enabled by electronics.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 21
 Figure 1.3: The impact of the Smart Industry Readiness Index (SIRI) framework, illustrated.

Figure 1.3 shows how the SIRI framework evaluates facility these areas are required within five years. This prioritizes
intelligence. standardization of chiplet interfaces, including an open
chiplet marketplace and the integration of low-power local
The capabilities necessary to enable industrial automation on networking, sensing, and computing.
this scale require fusion of a diversity of sensors, including
optics, sound, magnetic fields, temperature, pressure, and For example, agricultural automation requires a diverse set
chemical detection. of sensors and compute that must operate in an isolated,
independent environment with limited connectivity to
Improve IoT and edge systems design in 2035 through external sources of electricity. This motivates the need for
standardized chiplet interfaces. increased energy-harvesting circuits and architectures, as well
as packaging to support sampling of liquids and biological
Communication and interface standards are particularly materials for chemistry, biochemistry, and genetics. In 15
important. In an initial effort, the Open Platform years, new smart farm devices will track pests and will be used
Communications Foundation (OPCF) recently published an to track and validate the genetics and health of agricultural
open standard for communication between sensors and cloud products at the farm and through the logistics chain. Given
applications. Broad implementations of these standards, the volume of sensors and systems, enabling technologies in
which may be different from similar standards in other this area must be cost-effective. Agricultural automation will
technical areas, will be critical to enabling pervasive edge also require standardized microfluidic integration packaging.
and IoT computing, as well as achieving the economic success Other application areas, including synbio applications, will
expected from an Industry 4.0 revolution. likewise require similar functionality.

Home automation, as another example, consists of devices Infrastructure monitoring is one of the most exciting areas
such as smart thermostats and network-connected lightbulbs of IoT and edge applications, in large part driven by advances
and kitchen appliances. In the future, local power balancing during the COVID-19 pandemic, where researchers pioneered
and conservation will be controlled by a consumer-class wastewater monitoring for population-level COVID-19
power-management unit (PMU) equivalent, and network infection7. In 15 years, monitoring wastewater for disease
security and privacy in the home will be centralized via a or unusual contamination will become commonplace in local
home network security platform (NSP). Primary challenges government infrastructure. This will require packaging and
of IoT and edge deployment include energy efficiency and sensor integration, standards development as in industrial
integrated cybersecurity, and significant improvements in automation, and evolving best practices for cybersecurity.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 22
 Table 1.5: Application requirements for emerging IoT and edge use cases.

Home automation Agriculture Industrial automation Infrastructure

Requires mixture of
Low-power Requires battery operation;
power sources and levels;
operation, Access to power must consume low power; Access to power
need inter-network
standby, infrastructure; may consume requires drone integration infrastructure; may consume
interoperability between
and energy high powe and must allow for multiple high power
low- and high-power
harvesting energy inputs
components
Power < 1W standby power; 10W < 10uW standby; < 1W standby power; N/A
requirements active power 1mW-100mW active 10 W operation range

Packaging and Integration for consumer Integration and packaging Integration and packaging Integration and packaging
environmental applications; PMU and HSP for continuous exposure of for wide variety of for wide variety of
integration for the home liquids or biological samples sensors, including optics, sensors, including optics,
to sensor in integrated electromagnetics, electromagnetics,
package temperature, pressure, and temperature, pressure, and
chemicals chemicals
Security High: Protection against Medium: Protection against High: Protection against Extremely High: Protection
criminal activities targeting industrial espionage and industrial espionage and against industrial espionage
individuals, including hijacking nuisance threats, including and state actors, including
theft and malware; desire information theft and information theft, misuse,
for privacy enabled by malware and malware
confidential computing
Cost constraints Potential premium Extremely low-cost but high- Low-cost, high-volume Extremely low-cost, high-
market-2023-2027 volume systems systems required volume systems

Timing 2023-2027 2028-2031 2028-2031 2032-2036

1.5. Bioapplications and Health living atop of and engaging in two-way communication with a
CMOS device (a silicon backend).
Synthetic biology (or ‘synbio’) harnesses the power of
biological systems for useful purposes. Semiconductor- Semiconductor devices have also recently been used to
based applications of semiconductor synthetic biology 1
manufacture DNA for binary data storage. DNA is an ideal
(SemiSynBio) are rapidly growing but have unique packaging storage medium given its chemical stability and its nearly
considerations and constraints. These applications generally universal use in nature for reliable, long-term information
require the semiconductor device and packaging to directly storage. This universality is an additional strength, as there will
contact or contain a liquid interface. They may also be always be a large economic incentive to build the capability to
required to operate in a narrow range of biologically relevant read DNA, ensuring that binary data stored in DNA will always
temperatures at ultra-low power levels, or to interface with be directly readable. Synthesis of DNA for binary data storage
biological processes that take place at much longer time scales is an application requiring densely packed semiconductors,
than other semiconductor applications. advanced electrochemistry, microfluidics, and enzymatics
that could increase the density for binary data storage by
SemiSynBio devices make excellent biosensors, allowing for orders of magnitude over existing data storage technologies.
sampling and detecting specific analytes against complex
backgrounds. Sensing applications include environmental SemiSynBio devices can also be used in personalized medicine,
monitoring (e.g., detecting toxins in public water systems both to diagnose patient conditions (in a point-of-care setting)
or viruses in ambient air samples) and medical applications and to manufacture treatments in real-time at individual-
for diagnostics (e.g., detecting pathogens or evidence of patient scales. Current-generation micro-bioelectronic
cancer from blood samples). Such sensing devices can range devices can be ingested and pass through the digestive tract,
in complexity from simple chemically functionalized silicon collecting data via onboard sensors such as Medtronic’s
surfaces to entire communities of cells (a biological frontend) PillCam. Future-generation devices may be small enough to

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 23
 Figure 1.4: Illustration of communities of cells communicating with CMOS devices.52

travel through, or hold position within, blood vessels. These • Integrating microfluidics for reagent distribution and waste
devices will monitor blood over time and transmit results or product removal into semiconductor packaging, up to and
outside of the body for collection and analysis. They may even including distribution of such hybrid devices into traditional
use the turbulent passage of blood itself to generate power data centers.
for ongoing operation. Such devices could also be used to
• Synthesis of ~1 billion unique DNA sequences on a single
locally manufacture therapeutic compounds at low doses in
device in a single run.
real time, responding to and addressing biological risks to the
host, including infection or cancer. • Improving the ability of semiconductor devices to operate at
lower temperatures required by many enzymatic processes.
SemiSynBio devices also have applications in building brain/
• High-performance computing approaches to design and
computer interfaces (BCIs). BCIs are an exquisitely complex
model molecular computational approaches.
marriage of semiconductors in direct contact with neurons
and other nervous-system tissues. Such devices will allow for • On a longer time horizon of 10-15 years, to enable the broad
two-way communication between the brain and traditional promise of SemiSynBio technologies, advancements must:
computing systems. Ensuring these devices have a low
• Evolve microfluidics capabilities to enable reagent delivery
immune profile while embedding deep enough into the
and waste removal, as well as direct, on-device downstream
brain to communicate with all requisite brain structures
processing to isolate and purify output compounds.
remains a significant challenge.
• Lower the immune profile of SemiSynBio devices to allow
Lastly, SemiSynBio-based devices can harness their direct integration into—and long-term contact with—
thermodynamics directly in molecular computation-based living tissues and cell communities.
applications to efficiently solve otherwise intractable (or
• Enable creation and maintenance of cell populations in
simply expensive) problems. These applications may make use
artificial ecosystems for years in standalone SemiSynBio
of CMOS devices to carry out synthesis of the components
devices, using these populations to manufacture materials,
that will carry out the computation (e.g., DNA or other
directly communicate with other biological systems, or to
polymers), read back the results of the computation from the
sense changes in their environment.
fluid interface, or both.

Given the challenges facing binary data storage and the need
Advancement in these applications over the next five years
for improved areal density called out in the SRC Decadal Plan,
will require:
the industry should aim to store and recover 1 EB of binary
• Improved control over electrochemical and electro-optical data in DNA in a standard data center rack by 2037.
interfaces with semiconductor devices and packaging
strategies.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 24
1.6. Mobile, Communications, Even with tethered XR platforms, many bottlenecks persist in
key XR functions8, including:
and Infrastructure • Eye tracking: Implemented as a deep neural network with
Mobile applications and use cases have become more weights larger than a typical last-level cache, which makes
pervasive over the last 10-20 years, beginning with simple this kernel memory-bandwidth-bound.
feature phones, transitioning to smartphones. Alongside
• Scene reconstruction: Primarily GPU-bound with 200-
these transitions, communication infrastructure has co-
400GB/s of memory bandwidth, which exceeds both memory
evolved to enable novel use cases: high-resolution and
bandwidth and power budgets of untethered XR devices.
high-fidelity streaming services (e.g., Netflix), interconnected
gaming experiences (e.g., Pokemon Go), high-fidelity • Reprojection: Both instruction fetch and memory bound,
productivity and meeting tools (e.g., Zoom, Teams, etc.), due to the large volume of code and the high byte-per-flow
machine learning, and AI. With these significant advances ratio of reprojection shaders.
in use cases and the technology that underpins them, the
• Hologram: Consists of high-precision floating point
mobile, communications, and infrastructure technical area
operations (e.g., FP64 GPU operations) on a large
represents one of the fastest moving and most demanding
framebuffer, which drives significant memory bandwidth
technical areas. As current use cases evolve, users will pursue
consumption (75-140GB/s).
more immersive and more interconnected experiences.
• Audio encoding and playback: Compute-bound operations
In addition to mobile use cases, 6G communication whose performance is increasingly bottlenecked by
infrastructure will be built on the confluence of several key hardware divide performance and availability.
technological paradigms: digital twin infrastructure, effective
spectrum harnessing, integration of sensing capabilities, XR application exemplify key takeaways for applications
cloudification of radio access networks (RANs), and the relevant for MAPT:
evolution of spatial processing.
• Intentional hardware/architecture/software codesign can
enable better sophisticated architectures for XR workloads.
1.6.1 Untethered eXtended Reality Systems
• Chiplet-based modularity of XR accelerators will enable
End-to-end, ideal, untethered eXtended Reality (XR)
reusable, domain-specific accelerator blocks without
systems and use cases directionally represent the extreme
requiring the design and manufacturing of a monolithic
future of mobile platforms, frameworks, and use cases.
design for each change to algorithms and underlying
Mobile and communications infrastructure of 2037 must
domain-specific hardware.
enable ideal, untethered XR capabilities.
• Significantly increased memory bandwidth for diverse
Over the next 15 years, XR will enable pervasive use cases, workloads and memory-access patterns with significantly
altering how humans interact with the world around them improved energy/bit characteristics, even over incumbent
and creating new worlds with which to interact: remote GDDR and HBM memory technologies.
surgery, immersive gaming, and remote telepresence
• For reasonable untethered use, power efficiency must
only begin to explore the possibilities with ideal XR.
improve by multiple orders of magnitude.
Unfortunately, the promise of idealized, pervasive XR remains
unfulfilled, as multiple orders of magnitude in platform and
silicon capability remain to create a compelling XR platform8.

Table 1.6: End-to-end XR platform and workload requirements.

Metric Ideal VR8 Ideal AR8 Gap to Ideal8

Resolution (MPixels) 200 200 46x

Power (W) 1-2 0.1-0.2 70x

Silicon area (mm2) 100-200 <100 1.73x

Weight (grams) 100-200 10s <50x

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 25
3D-integrated, HI packaging technologies developed with • Continued system efficiency improvement and power
architecture awareness across both logic and memory silicon consumption is required for 6G advances. Doherty power
will be paramount in achieving compelling XR systems. amplifiers are the workhorse architecture for both
mMIMO, as well as more traditional high-power, macro
Additionally, while it addresses some of the compute base-stations (usually 4-8T). Doherty power amplifiers are
requirements for traditional untethered VR systems, not overly complex, and they can work up to ~40% relative
significant gaps remain with cloud rendered XR. Plus, bandwidth with high efficiency in the 6-9 dB average power
while cloud processing trades local compute for remote backoff from peak power. Note that most FDD and TDD
connectivity, this solution space comes with even further systems operate with the signal peak-average ratio in
challenges. For instance, moderate confidence targets for that same 6-9 dB range. Digital Predistortion (DPD) is the
multi-party VR approach 2Gb/s per player with baseline, main linearization technique. Future systems may
reliable network latency of <10ms at the 99th percentile . 9
push wave-shaping to higher-efficiency amplifier classes
such as class F, inverse class F, class J, etc., and still allow
XR capabilities will drive the needs of communications and linearity correction. Reducing the number of nonlinear
infrastructure in 2037 (including 5G-Advanced and similar coefficients in the DPD ASICs also allows for improved
technologies), and infrastructure should pursue pervasive overall system efficiency.
connectivity at >2Gb/s/user with stringent, consistent
latency requirements of <10ms at the 99th percentile. Future communication infrastructure, especially 6G, will be
a complex amalgamation of various technologies designed
1.6.2 6G Infrastructure and Beyond to meet a wide array of demanding use cases in addition to
XR, including collaborative robotics, telemedicine, and more.
The era of 6G invites big-data solutions for wireless
These use cases require significant advancements in underlying
technologies, where AI/ML solutions will play a significant role.
technological paradigms, pushing the boundaries of AI/ML in
The broad implementation of AI/ML across network layers will
communications infrastructure, spectrum utilization, sensing,
enable site-specific optimizations, better beamforming in high-
digital twins, cloudification, and spatial processing. 6G will build
dimensional antenna systems, improved channel coding, and
on the evolutionary technical foundation established by Beyond
efficient resource allocation, among other benefits. Moreover,
5G (B5G) and usher in revolutionary technologies to become the
the integration of AI in dynamic spectrum management and
unified innovation platform for 2032 and beyond.
the evolution of non-orthogonal, multiple access will pave
the way for efficient spectrum utilization, providing increased
Current and future mobile communication infrastructures are
data rates. Furthermore, 6G will integrate sensing capabilities
based on what is called a Service-Based Architecture (SBA),
as an integral part of the network. The potential for very
which implements IT network principles and a cloud-native
accurate sensing based on radar-like technology arises with the
design approach within radio access networks (RAN) and
introduction of terahertz bands. This will provide the network
core networks (CN). For example, 5G Core (5GC) implements
with spatial knowledge of the physical surroundings, enabling
the new 3GPP network architecture that will unleash the
a host of new use cases and performance improvements.
full power of 5G standalone (i.e., it is not dependent on any
• Digital twins will be employed to plan, operate, optimize, other network architecture), enabling faster connectivity
and train 6G networks, which will boost in operational speeds, ultra-low latency, and higher bit rates with high grade
efficiency and will generate massive AI training datasets. of network reliability. These capabilities, combined with
network automation, network slicing, and edge computing,
• The cloudification of RAN—or CRAN—will provide flexibility,
are instrumental to addressing multiple verticals and enabling
efficiency, and reduced cost for communication service
an innovation ecosystem with use cases like enhanced
providers. Cloudification will enable radio workloads on
mobile broadband, ultra-reliable low-latency communication,
general-purpose computing hardware that can also process
massive machine-type communication, and time-critical
AI pipelines.
communication31-33. Figure 1.5 demonstrates the end-to-end
• Spatial processing, particularly through massive MIMO latency in mobile communication infrastructures divided
(mMIMO) and Reconfigurable Intelligent Surfaces (RIS), will into sub-domains.
provide capacity and throughput gains. Advances in this
area may enable machine learning to one day control meta-
material arrays.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 26
 L end-to-end = Latency experienced at the RAN (½ L radio + L Tansport Network) + Latency experienced at the Core Network
(L CN + ½ L User Plane Functions-to-Application Server )+ LApplication Server + L Peering Point

Figure 1.5: Latency components in the mobile communication infrastructure.

In current 5G deployments, there are several reports of use cases, such as real-time augmented reality, virtual reality,
uplink and downlink radio latencies varying from 1ms to 5ms, and autonomous vehicles. In addition, web-scale player
depending on the RAN configuration. The latency introduced computing platforms can be used to host core network
by the transport and core networks is usually modeled nodes. By leveraging the infrastructure of these large-scale
using fixed values. For example, some reports considered Data Centers and cloud service providers, mobile network
that the one-way core network latency is 200μs or 100μs operators can reduce capital and operational expenses while
for non-standalone and standalone networks. Also, latency benefiting from the expertise and resources of these web-
introduced in the link between the core network and the scale players. This collaboration can lead to more efficient
location of the Application Server (AS) was introduced in the network operations and improved network performance.
order of 5.4μs. Finally, the core network latency is estimated
as a single value of 20ms considering the processing delay The strategic placement of core network workloads
introduced by the core network nodes with neglecting the on distributed computing platforms enables optimal
propagation or queuing delays. The final end-to-end latency performance and power consumption. Centralized
can reach upto 200ms. orchestration allows for resource elasticity, while the
interconnection of these platforms supports a wide range
In terms of power consumption, core network workloads are of applications and services. By leveraging web-scale player
optimally placed on highly distributed compute platforms to infrastructure, mobile network operators can further
deliver optimal performance as per use case requirements. optimize network performance and reduce costs34-36.
These distributed cloud platforms are interlinked, and
workloads are orchestrated centrally to achieve elasticity Based on the above use cases, mobile communication
based on availability. infrastructure is expected to support critical communications
with ultra-reliable and low-latency features. Many have
Distributed mobile communication cloud platforms can be implemented vRAN (virtualized RAN) stacks across various
used to host web-scale player application platforms, such as compute accelerators with mixed results, including GPUs,
content delivery networks, gaming servers, and IoT services. FPGAs, CPUs + accelerators, etc. These all produce modest
These platforms provide low-latency access to applications gains in latency and bandwidth, but more improvements are
and services, improving user experience and enabling new necessary to meet the latency targets required by XR41-42.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 27
As complexity grows from 5G to 6G, and the protocol begins higher-performance defense application devices are driving
to integrate AI concepts, both increased compute and intense research efforts on ultra-wide band gap (UWBG) device
increased memory bandwidth requirements will be needed. materials, including β-Ga2O3, diamond, and AlN with Eg = 5-6
3D integration and HI will help to alleviate these bottlenecks eV and the correspondingly larger breakdown field strength (3-
in scaling out compute and memory. Additionally, trends 5x of GaN), which enables even higher electronic performance
suggest that even more pervasive acceleration may be limits. The critical bottleneck in realizing the high-power device
necessary, and analog accelerators may be able to reduce performance for GaN, and even more seriously for UWBG
latency as the protocol becomes more complex. devices, is the ability to remove the heat generated at the hot
spots of the high-power devices due to the scaling and the
Overall, these key infrastructure innovations are required increasingly complex multiple layers and interfaces in 2.5D and
to enable the end-to-end latencies essential for pervasive 3D heterogeneously integrated structures.
system-level use cases like single- and multi-party XR.
Considering the previous timeline of GaN and SiC power-device
development of the last two decades, we expect that the
1.7. Defense and Harsh UWBG device development will also take a decade or more to

Environments optimize the electronic performance of the device materials.

Since the electronic performance of device materials cannot be
While defense applications have driven unique requirements utilized without the heat-removal solutions to current GaN and
for a low volume of harsh environment microelectronics, future UWBG high-power devices, the expected performance
commercial sectors that operate in harsh environments of high-power devices will be determined by the development
should see a growth in symbiotic relationships between the of efficient heat-removal solutions over the next 5, 10, and 15
defense and commercial sectors. Here, the modern devices years. Specifically, the next five years will bring a 10x increase
that drive our daily life often require the cooperation of in output power density for GaN devices. Within the next 10
disparate electronic parts merged into a system-in-package years, UWBG devices are expected to surpass the performance
(SiP) through heterogeneous integration (HI). However, many of GaN devices, but they will still be limited by heat-removal
of these parts are not designed or integrated in a way that solutions. Within the next 15 years, UWBG devices are expected
is compatible with use in extreme environments. Examples to realize a significant portion of 3-5x better performance than
include applications that require high reliability and lifetime, GaN devices based on the device technology maturity and high-
as well as the ability to operate in environments of high or performance heat-spreader solutions.
low temperature, high shock/vibration, and electromagnetic
and extreme ionizing radiation. Future thermal solutions must enable future GaN and
UWBG devices in extreme environments.
Therefore, as the microelectronics community is moving to
deploy these HI assemblies, there is a need to understand the 1.7.2 Radiation Requirements
knowledge gaps for heterogeneous integration for extreme
The investment and development of chiplets that are
environments.
intrinsically capable of withstanding harsh environments must
be realized at the commercial level. Leveraging application
1.7.1 Thermal Management
areas for commercial growth will be necessary for utilization in
Higher-power operation ultimately drives junction niche and low-volume regimes. As an example, the commercial
temperature beyond operational functionality, impacting satellite industry is anticipated to grow over the next 15 years.
reliability. Advanced thermal management techniques (active Though commercial satellites may not require high-reliability
and passive) within a 3D package need to be developed that qualification standards similar to life-consequence systems
minimize operational complexity and power consumption, such as those required for commercial airlines, they will still
particularly as advanced packaging can collocate more need to be developed with environmental stability, reliability,
components in smaller volumes. It is expected that advanced and radiation hardness in mind.
packaging will minimize the ability to utilize current techniques
like passive heat sinks from surrounding architecture. There are different approaches for developing
microelectronics systems for space applications, specifically
Current high-power device performance is limited by the for evaluating radiation-induced effects within the space
heat removal at the device scale. The increasing demands for environment. In order of complexity, these include:

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 28
• Shielding to reduce radiation effects: Beneficial for does not satisfy the needs of defense or harsh environment
simplicity of insertion and the ability to use products that applications and use cases. Advanced packaging and 3D
are designed for higher-volume applications, even at an integration for these use cases will require robust qualification
overall weight increase. of integration schemes, determination of failure modes,
and an understanding of component lifetimes. An increased
• T-hard by design: Provides robustness to radiation effects
number of integration processes, number of interfaces, and
through redundancy in design. While this can alleviate
new materials in direct contact with previously qualified parts/
system impacts due to effects of SEU, TID, etc., it requires
components will require a complete requalification, including
cost and time for specialized design. Alternatively, future
new failure modes and operating limitations.
EDA platforms should enable automated robustness to
radiation events, as they do for reliability today.
In reference to Table 1.7, the SEE class events are defined as
• Rad-hard by process: Uses specific materials properties the following:
or fabrication means to provide robustness to radiation
• Class A: The lowest risk tolerance that is driven by technical
effects. However, this can drive an even greater impact
objectives. A very high-priority mission with very high
on cost and timelines for development and qualification.
complexity.
Further, rad-hard by process often requires a separate
fabrication line, driving greater cost and time. • Class B: Low-risk tolerance that is driven by technical
objectives. A high-priority mission with high complexity.
Redundancy in advanced packaging has the potential to
• Class C: Moderate-risk tolerance that is driven by technical
revolutionize radiation hardness in microelectronics with
objectives. A medium-priority mission with medium
high volume manufacturing components and minimal
complexity.
impact to SWAP, potentially with commodity chiplets.
This enables redundancy of critical elements like memory • Class D: High-risk tolerance that is driven by programmatic
without increasing layout area. It Is desirable to enable a constraints. A lower-priority mission with a medium to low
chiplet marketplace, where systems designers select the complexity.
best conventional chiplets mixed with inherently rad-hard
Classes C and D are rare in MEO, GEO, and HEO missions.
products (e.g., GaN amplifiers). This enables advanced
Classes C and D payloads sometimes ride on deep space
capabilities for harsh environment use cases like space
missions with Class A and B requirements.
applications (e.g., satellite systems).

Enable chiplet capabilities and designs that can be

Qualification of individual, high-volume manufacturing parts
made rad-hard with only a selection of off-the-shelf
for harsh environments or defense applications is costly
components, especially as it relates to integration of
and time-consuming. The introduction of chiplets alone
heterogeneous chiplets.

Table 1.7: Typical radiation effects by orbit or mission.

Typical mission Temperature Total ionizing

Mission type Single-event effects (SEE)
duration cycles per day dose (TID)

SEL onset threshold (LETTH) of 60

Exo-atmospheric / Suborbital Minutes to Hours N/A 100 Krad
MeV-cm2/mg

SEL LETTH > 37 for class C, D programs;

Low-earth orbit (LEO) <7 years 16 (every 90min) 10-25 Krad
SEL LETTH > 60 to 75 for class A, B programs

Mid-earth orbit (MEO) <20 years 2 (every 12 hours) 100-300 Krad SEL LETTH > 60 to 75 for class A, B programs

Geosynchronous orbit (GEO) <20 years 1 (every 24 hours) 100-300 Krad SEL LETTH > 60 to 75 for class A, B programs

Highly elliptical orbit (HEO) <20 years 1 (every 24 hours) 100-300 Krad SEL LETTH > 60 to 75 for class A, B programs

Deep space (cislunar,

<20 years Varies by orbit 100-300 Krad SEL LETTH> 60 to 75 for class A, B programs
heliocentric, interplanetary)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 29
1.7.3 Reliability Requirements packages typical of commercial builds. In this case, biased and
unbiased Highly Accelerated Stress Test (HAST) may be used
As the semiconductor industry move towards HI, the industry
to detect moisture-related corrosion, whisker growth, and
will need to address thermomechanical and reliability issues
related failure modes. Suggested test conditions for biased
that stem from the integration of non-silicon mechanical
and unbiased HAST can be found in JESD22-A110E.01 and
properties. One challenge is the integration of organic
JESD22-A118B.01, respectively. For ceramic parts, such as
constituents that can expand and contract at a rate that is
those typical for defense and space, the appropriate corrosion
an order of magnitude greater than silicon. This can impose
test procedures can be found in MIL-STD-883 Method 1004.7
thermomechanical stress during transport and operation,
and 1009.8. The hermeticity of these parts are defined in
thereby affecting performance and reliability.
MIL-STD-883 Method 1014.9. Compromised hermeticity can
influence the risk of environmental corrosion.
To understand these mechanical risks, the environmental and
temperature swings presented in MIL-HDBK-217 represent
In general, the acceleration factor associated with HAST
valuable use cases.
testing has been derived using an Arrhenius relationship, using
the activation energy for corrosion that is characteristic of the
MIL-STD-810 also contains operational conditions that
interconnects used in the package29,30.
include the relative humidity in an environment. In this case,
humidity presents unique challenges by depressing the glass
1.7.4 Space and Defense Use Cases
transition temperature in polymers24,25, which can serve to
increase expansion and contraction of organic constituents, SAR and SIGINT require higher and higher instantaneous
thereby causing mechanical failures in interconnects. Water bandwidths, requiring higher and higher capability analog
also presents issues with interface weakening and corrosion26. to digital conversion (ADC) and processing loads. Harsh
Both deleteriously affect the lifetime and reliability of a part. environment use cases drive smaller size, lower weight, and
lower power constraints. ADC and digital processing engines
Because the reliability and lifetime of an HI part depends co-located with integrated analog conditioning chiplets in the
significantly on the interconnect and bonding processes used in same package will improve harsh environment systems greatly.
its construction, it is very difficult to predict how and when they
will fail without knowledge of the processes and components Proliferation of massive Low Earth Deployments (e.g., Starlink
used in the package. Therefore, to accurately predict the and Kuiper) are driving somewhat less harsh environments
lifetime and reliability of these parts, one must model and than defense-related higher-orbit constellations, but
test the package in its design and development cycle. To this proliferation is driven by shorter satellite lifecycles,
inform simulation, these use cases require characterization accelerating the traditional space-environment technology
of materials and interface properties. This will lead to higher curve. As a result, semiconductor innovations are migrating to
fidelity models. This is especially true for parts with significant high-reliability environments at an accelerated pace.
organic constituents, such as plastic interposers, or parts built
using new bonding techniques like hybrid bonding. The nature of defense-related satellite communications is
migrating to a distributed model, where satellites talk to
To estimate the lifetime and reliability performance of a each other to distribute the communication load, providing
hetero-integrated part, temperature-cycling and power- network resilience to kinetic and non-kinetic threats. This
cycling can be employed to accelerate the effects of thermal- requires additional RF datalinks and improvements in wireless
mechanical strain. Temperature cycling and Power cycling communication, driving up the need for modular design and
are form of accelerated aging that expedites a part’s time-to- increasing the need for a chiplet ecosystem.
failure by revealing latent defects
Emerging Electromagnetic Spectrum Operations in contested
When a part is deployed and exposed to cumulative stresses in and congested RF environments portends the advent of
the field9,10, the Coffin-Manson equation can be used to define Electronic Warfare satellites, wherein satellites become EW
the acceleration factor (AF) .”
28
delivery effects platforms and move the need for digital-
to-analog conversion at wider rates and higher power
Corrosion in bondpads and interconnects can be a concern amplification.
for non-hermetic packages, such as the plastic encapsulated

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 30
1.8. State of the Art / Product proportionality strongly influence energy usage, whether
in battery-powered systems or systems that require large-
Examples scale, deliberate power delivery. Future systems will have
to rely on battery scaling and a proliferation of power
Cross-stack solutions are prevalent in the industry today,
generation to scale performance, but, as mentioned in the
with TPUs, GPUs, mobile accelerators, etc., as commonplace.
Decadal Plan, the industry will reach a point where the
Google’s TPU and Tesla’s AI in-car inference accelerators both
power demands become untenable.
required significant hardware/software codesign. As we enter
a new AI paradigm with LLMs, even these one-dimensional • Compute performance, even with the proliferation of
DSAs will not be sufficient to continue to scale performance domain-specific architectures, as interconnects will
without significant algorithmic changes. dominate performance and silicon area.

• Miniaturization, especially for systems that require small

Various HPC application drivers already benefit from
form factors to unlock new use cases, like biological sensors.
architectures that employ 3D stacking technology. For
instance, AMD’s V-cache-enabled Data Center processor • Adequate hardware/software codesign efforts, especially
improves performance measurably for HPC workloads. those involving domain-specific architectures, where
These kinds of accelerated systems are just the beginning, as architectures evolve in conjunction with the higher-level
workloads and algorithms catch up to what’s available. software stack.

1.9. Limitations with Current 1.10. Challenges, Future

Technology Needs, and Possible Solutions
For conventional systems and workloads like Data Center, This chapter aims to identify trends and needs from the
HPC, edge, IoT, mobile, etc., even with increasing amounts application and system spaces. Its development has identified
of specialization, the slowing of linear transistor density and a strong need to cultivate an industry-wide, full-stack view
energy-efficiency scaling limits the end-to-end performance of applications through bits, focused innovations that could
and energy-efficiency gains possible. With limited performance enable technical breakthroughs (e.g., with a focus on memory
and power benefits, 2.5D scaling for domain-specific bandwidth and capacity). The industry requires a forum where
accelerators has reached a plateau without significant these full-stack optimizations are encouraged and enabled.
changes to compute architecture. Additionally, with increased This includes a forum that enables and encourages hardware/
specialization, systems designers are limited to the assembly of software codesign for novel architectures, as well future
heterogenous systems. For performance and energy optimized semiconductor process and packaging innovations and their
workloads and systems, today’s chips and chiplets are often impact on systems.
perimeter- and interconnect-limited. This arrangement limits
performance and power benefits, which are key bottlenecks in Additionally, engineering skillsets that span multiple domains
applications, even on optimized, domain-specific architectures. (e.g., memory devices and computer architecture, hardware
design, and operating systems) are both limited and in
As this chapter discusses, today’s systems with existing increasingly high demand. The industry must enable and
technology are limited by the following: encourage a workforce that can reason about problems across
the entire stack. Reasoning across one domain is helpful, but
• Memory bandwidth, which is a critical component of system
many of the challenges identified in this chapter span many
performance in many application spaces, has been outpaced
domains at once.
by compute performance by greater than 10x.

• Memory and storage capacity will remain limited, which places 1.10.1 Addressing Data Center Workload
more strain on scale-out interconnect for capacity-bound Challenges
workloads like recommendation-based AI model inference.
Compute-performance scaling
• Energy and power usage, especially in mobile systems (e.g.,
Demands on Data Center infrastructure continue to increase
XR), edge, and IoT systems, as well as Data Center and HPC
as programmer productivity drives more complex workloads
systems. Interconnect, memory bandwidth, and energy

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 31
and there is a greater focus on more stringent performance To overcome interconnect limitations between compute
requirements while maintaining or improving energy and memory chiplets, systems require 3D integration at
efficiency, as well as larger data-set sizes. Nevertheless, as very-fine-pitch interconnects, with the ability to pursue
Data Center overheads decrease, the importance of the modest stack heights of 10s of die at interconnect
energy efficiency of IT infrastructure grows significantly38. bandwidths approaching on-die interconnects.

Over the last 40 years, semiconductor process improvements Memory scaling

primarily drove energy-efficiency improvements, but process
As described in the application examples above, memory
improvements over the last decade have slowed as Dennard
is a crucial component of the compute ecosystem, forming
scaling has stalled46. In response to these trends, Data Center
the foundation for HPC and Data Center use cases. Despite
operators have turned to heterogeneous computing with
improvements in transistor density and domain-specific
domain-specific accelerators (DSAs)—GPUs, FPGAs, TPUs,
architectures, SRAM densities cannot address the demand
IPUs, etc.—to improve performance of target workloads at
for workload datasets. Additionally, with the prevalence
reduced energy. Due to increasing levels of specialization,
of attention-based AI models and similar workloads, the
Domain Specific Architectures (DSAs) require thoughtful
number of bytes required for each compute FLOP continues
design. Successful implementations require tight coupling
to increase47,48. Moreover, as compute engines continue
between algorithms, frameworks, and architectures,
to improve, memory becomes increasingly important, as
otherwise referred to as hardware/software codesign.
its connection with compute engines has not increased
proportionally over time40. With constant or growing
Nevertheless, focus on transistor process improvements
bytes-per-FLOP, increasing compute bandwidth through
should continue, as improvements in transistor efficiency are
specialization or otherwise also increases systems bottlenecks
additive with architecture improvements. Furthermore, other
on memory devices, even those architected for high
promising technologies, including quantum computing, optical
performance. AI inference and training workloads and DSAs,
computing, analog computing, and neuromorphic computing,
mentioned above, represent the compelling system-level
may demonstrate a path to exceptionally compelling energy
benefits possible with memory-bandwidth optimizations.
efficiency and energy proportionality for specific domains
and use cases.
High-performance, high-density (e.g., DRAM or denser)
memory devices must close the gap with compute
Interconnect scaling
architecture scaling. By 2037, system-visible memory-
In addition to compute elements, interconnects are critical to device bandwidth must improve by >10x through end-
both system performance and energy efficiency. Applications to-end optimizations in 3D integration, memory system
and use cases that scale across multiple systems and multiple co-optimization, and/or processing- or compute-in-memory
racks expend significant energy in communication and often techniques.
spend productive cycles waiting for responses from remote
computers. Additionally, modern Data Center network In addition to performance, many workloads discussed
infrastructure is often oversubscribed, limiting inter-rack above remain limited by memory or storage capacity, as
application scaling38. Modern switches are often power- programmers and systems operators are left with no choice
and pin-limited. Even within modern server infrastructure, but to scale out to additional servers inter- or intra-rack.
intercommunication between hardware elements (or chiplets) This adds additional latency and restricts bandwidth in the
are often limited by chiplet perimeters. Past advancements same manner as general-purpose interconnect technologies.
in transistor scaling and complex signal processing, which Emerging memories are poised to address these challenges.
have driven increases in interconnect bandwidth and
energy efficiency, have nearly reached a plateau because Following the Decadal Plan, system-consumable memory
of untenable channel losses. Discussed in detail in the next and storage density must improve by >10-100x by 2037,
section, connection to memory is even more important, given and usable local capacity must increase analogously.
the increase in data set sizes.
Thermal and power-delivery challenges
Interconnects between systems elements must continue
The exponential increase in High-performance Computing
current energy efficiency and performance trajectories
(HPC) and Data Centers application workloads described
when normalized to channel quality.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 32
in this chapter will require advancements in compute Most Data Centers use energy-intensive chilled-air cooling,
performance, including chip architectures and multi-chip which utilizes 25-35% of total Data Center energy usage and
modules, to achieve system-performance scaling. An consumes water in cooling towers. The replacement of energy-
additional challenge includes advancing energy infrastructure intensive air cooling with cooling solutions that transfer heat
to increase the power usage effectiveness (PUE) given by the to outdoor ambient environments eliminates energy-intensive
ratio of total power to compute power. chillers. This requires reducing the thermal resistance from
the chip to the coolant, such that coolant temperatures above
In addition to 2.5D architectures, chiplet-based, the outdoor ambient can be used to achieve the operational
heterogeneous, 3D-stacked architectures, and system-on- chip junction temperature. A demonstration of ambient
wafer architectures will become prevalent as solutions to warm water achieved a reduction in cooling energy usage
future workload and systems bottlenecks between now and >90%50 compared to compressor-based chilled-air cooling and
2033, extending into 2037. Thermal management solutions eliminated water usage by deploying dry coolers.
must maintain the same or better junction temperatures in
3D-stacked architectures. 1.10.2 Thermo-mechanical Challenges
Thermo-mechanical challenges, while not necessarily
Chips or 3D stacks
application drivers in and of themselves, must be addressed
Compute and memory-scaling challenges driven by application to enable future HI use cases. The industry must focus on
requirements must be addressed by 3D stacking and reductions in thermal resistance across all use cases, beginning
heterogeneous integration. The proliferation of 3D stacks to with reductions in packages overall. SiP design, where
increase performance and reduce energy efficiency introduce package contents are in direct contact with the system-level
ever-increasing power densities. These stacks must be kept thermal solution, present one opportunity to reduce thermal
at reasonable temperatures, as architectures cannot relax resistance. This poses challenges in thermal management,
thermal requirements through junction temperatures without including performance, reliability, and cost. Additionally,
reducing overall performance. It’s likely that thermal solutions looking forward to future systems, thermal solutions must
will need to provide cooling at different places in a 3D-stacked manage contamination from surrounding fluids and must
architecture. Additionally, since these individual chiplets mitigate the impact of photonics and high-speed signals.
will still require similar input power as their non-3D-stacked
counterparts, there must exist area-efficient power-delivery The DSA solution space for package power and heat density
solutions for powering tall 3D-integrated stacks without may surpass 2kW by 203343. This will be associated with
significantly imposing upon compute architectures. a rise in power density to an average of 0.5W/mm2. To
address this anticipated increase, systems must consider the
Servers or modules thermal resistance between silicon hotspots and the average
temperature at the system-silicon interface, as well as the
As described in Chapter 7, system performance scaling will rely
thermal resistance between silicon-hotspot temperature
on advanced, high-density packaging. These modules will have
and the system-sink temperature. By 2033, the temperature
higher power dissipation, which will require advanced cooling
rise between silicon-hotspot temperatures and the average
solutions beyond the air-cooling solutions deployed today.
system-interface temperature could reach 75ºC, compared
High-density, 3D-stacked packaging will stress today’s thermal
with just 10ºC in 2023. More prevalent use of stacked die or
solutions, and future thermal solutions must address the high-
higher silicon-power concentrations explain this trend. By
density nature of these solutions while maintaining today’s
2033, it is essential that the target system-silicon average
junction temperatures.
interface temperature remain at 35ºC or lower, as opposed to
100ºC or lower in 2023.
Data Centers

The growth in applications will continue to fuel expansion As Data Center cooling requirements shift to more aggressive
of HPC and large-scale Data Centers. The Office of Energy cooling solutions, heterogeneous cooling solutions should
Efficiency & Renewable Energy reports that US Data Center be possible. Data Center products must accommodate
energy usage is roughly 2% of total US electricity usage potential condensation challenges for surrounding air-cooled
and consumes 1.7 billion liters/day of water . The path to
49
components that may not be cooled by direct liquid cooling
reducing both energy and water usage includes improvement plates (e.g., processors vs. memory)44.
in computation efficiency and Data Center infrastructure.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 33
The following principles apply equally across all workloads and 1.10.3 Security Challenges
systems considered:
Providing robust systems security has become increasingly
1. Heterogeneous integration, especially of new technologies challenging over the past 10 years. Security will become
like silicon photonics that address interconnect challenges of increasingly more important as MAPT systems become more
today’s systems. prevalent. The zero-trust doctrine has gained widespread
recognition as the new standard for system security across
2. A full-system view of thermal design and mitigation,
sectors and application domains45. In response, there will be
including a deep understanding of component thermo-
two major impacts to systems: (1) overheads in implementing
mechanical performance and behavior, as well as the
the baseline zero-trust stack, especially in deeply embedded
architectural implications of that behavior (e.g., performance
platforms, and (2) active defense mechanisms. Each class of
impacts of throttling, etc.).
system will implement these differently, imposing different
3. Furthering commercially appropriate solutions, when application requirements. However, the building blocks will
possible. Air cooling should remain a primary thermal- remain similar.
management strategy. This can be enabled by limiting power
consumption or improving air cooling. Systems will need to implement the five tiers of the zero-trust
stack, which include single-packet authentication, mutual
4. More innovative thermal-management solutions like liquid
transport-layer security, device validation, dynamic firewall
cooling should be enabled where air cooling is no longer
provisioning, and application binding. Executing these layers
effective, or it impacts system-level performance or form-
will create additional overhead that must be factored into
factor requirements.
their design, especially for certain classes of systems. Some
5. Other cooling techniques should be considered a last resort platforms may benefit from explicit accelerators, whereas
and should only be applied when there is no alternative, or in others can provision the compute bandwidth necessary from a
special applications with unique requirements. general-purpose pool of compute.

6. The impact of cooling techniques on high-speed signals,

The active defense mechanisms required will depend heavily
ESD, EMI, and system reliability must be fully qualified.
on the attack surface of each platform. The MAPT chapter 3 on
Additionally, cooling techniques should now impact the silicon
security expands on the types of attacks hypothesized today by
or package performance, nor their manufacturing process.
application drivers. However, it’s well understood that an active
security mechanism will be necessary for future systems in order
to guard from untrusted hardware and outside attack sources.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 34
Contributors
Ameen Akel (Micron) – Chair Swaroop Ghosh (Penn State) Umit Ogras (UW-Madison)

Gamal Refai-Ahmed (AMD) – Vice Chair Brett Goldsmith (Paragraf) Matt Oullette (AMD)

Madhavan Swaminathan (Penn State) – Steffen Hellmold (Pithos) Partha Pande (Washington State University)
Vice Chair
Amr Helmy (University of Toronto) SB Park (SUNY Binghamton)
Brice Achkir (Cisco)
Dave Henshall (SRC) Dusan Petranovic (Siemens EDA)
Sohrab Aftabjahani (Intel)
Deukhyoun Heo (Washington State Jonathan Pickering (independent)
Frank Baker (NXP) University)
Rahul Razdan (Razdan Research Institute)
Kevin Barker (PNNL) Pravind Hurry (Qualcomm)
Joshua Rubin (IBM)
Ashraf Bastawros (Iowa State University) Ahmed Hussein (University of Guelph)
Sadasivan Shankar (SLAC Nat’l Lab)
Asif Bhatti (America’s Frontier Fund) Mir IM (SK hynix)
Kevin Sheridan (LANL)
Timothy Chainer (IBM) Yousef Iskander (Microsoft)
Ness Shroff (Oregon State University)
Krishnendu Chakrabarty (ASU) Steve Kosier (Skywater Technologies)
Ravi Sundaram (Amazon)
Kyeongjae Cho (UT-Dallas) Stephen Kosonocky (Uhnder)
Min Tsao (Siemens EDA)
Stan Chou (SNL) Timothy Lee (Boeing)
Gene Tsudik (UC-Irvine)
Richard Chow (Intel) Patrick Madden (SUNY Binghamton)
Steven Verhaverbeke (Applied Materials)
Srabanti Chowdhury (Stanford) Rafic Makki (Mubadala Technology)
Jeffrey Vetter (ORNL)
James Diggans (Twist Bioscience) Sasikanth Manipatruni (Kepler Computing)
Andrew Wheeler (Hewlett Packard
Hoa Do (AMD) Carl McCants (DARPA) Enterprise)

Rajeev Dokania (Kepler Computing) Benoit Montreuil (Georgia Tech) Chip White (Georgia Tech)

Erica Douglas (SNL) Jeremy Muldavin (GlobalFoundries) Lu Yuan (Qualcomm)

Mark Downey (Analog Devices) Scott Norrholm (AMD) Ming Zhang (PDF Solutions)

Ibrahim Gedeon (TELUS) Mike O’Connor (NVIDIA)

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(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 37
Chapter 2

Sustainability and Energy

Efficiency
2.1. Introduction
Microelectronics are a key enabler to bring efficiency to and systematic efforts to reduce the overall environmental
critical system-level economic processes. As an example, impact within and across all phases of a product’s lifecycle. This
digitalization made possible by the combination of edge devices, includes product design, development, manufacturing, use and
communications technology, and data centers enables important end-of-life management. Proactively integrating environmental
capabilities such as e-commerce, telehealth, online education, considerations into normal business operations through
streaming, and remote working. In addition, digital technologies collective actions, across the entirety of the semiconductor
that are powered by microelectronics could provide new ecosystem, will be essential for a meaningful and lasting impact.
insights and accelerate progress toward environmental goals, As described here, the key to success for microelectronics and
yielding the potential to offer solutions to monitor, mitigate, applied packaging technologies (MAPT) moving forward is to
and adapt to the impacts of climate change. Looking forward continue developing new and beneficial technologies, while
to concepts such as Industry 4.0, many industries are relying simultaneously ensuring that environmental considerations are
on electronics to provide more sustainable solutions for an integral part of the product lifecycle.
their markets. For instance, electronics are necessary for the
sustainability-driven $7.8 billion agricultural robotics market1,2 Continuing to build off this foundation, this chapter addresses
and the $31.8 billion smart-grid technology market . 3
the need for 1) dramatic increases in energy efficiency for
information and communication technologies (ICT), which
Thus, while microelectronics can help facilitate powerful will herein be referred to as “compute,” and 2) increased
solutions to global, regional, and local environmental environmental sustainability and efficiency across the
sustainability challenges, the potential environmental entire lifecycle of microelectronics, while simultaneously
impact associated with the manufacture, use, and end-of-life meeting performance criteria. This chapter also
management of microelectronics must also be considered, as acknowledges the need to develop a workforce with the right
each phase in the lifecycle of a microelectronic product can skills and tools to accomplish this sustainability transformation
impact the environment. Sustainability, as used in this context, that is catalyzed and underpinned by semiconductors.
refers to a comprehensive accounting of these potential impacts

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 38
2.2. Energy Efficiency effect that orders of magnitude more computing is consumed
each decade. This correlation between increased efficiency
There are three main elements of energy efficiency for and increased utilization is known as Jevon’s Paradox5. This
microelectronics that are discussed in this chapter: energy- increasing appetite for computing, along with the slowing of
efficient computing, energy-efficient power electronics, scaling for the newer technologies, is why information and
and energy-efficient products, processes, and end-of-life communication technologies are poised to consume a major
management. Energy-efficient computing and communications fraction of the world’s energy in the coming decades.
is addressed in section 2.2.1., and energy-efficient power
electronics are addressed in section 2.2.2. The energy As such, energy-efficient processing, communication, and
efficiency of wafer fabrication is addressed in Section memory/storage during the operating life of microelectronics
2.3.4., along with additional environmental sustainability is an increasing concern for computing advances, including
considerations for microelectronics fabrication. This sub- the energy consumption associated with the computational
section closes with a discussion of the technical challenges, requirements for leading-edge foundation training and
future needs, and possible solutions. inference. Further, it has been estiamted that data centers6
and servers use approximately 1% to 2% of the world’s
2.2.1. Energy Efficiency of Computing and electricity, with significant growth projected in the next
Communications decade driven by blockchain, machine learning, and mobile
data traffic to name a few. Future challenges for beyond 5G
In the last decade there has been an explosion of demand for
advanced wireless communications will also require energy-
computing driven by cloud-connected smart mobile devices.
efficiency improvements. Hence, increased energy efficiency is
The energy-efficiency requirements in computing have been
a major driver of new microelectronics, circuits, architectures,
driven by five key trends.
and advanced packaging technologies.
1. The geometrical technology scaling cadence has slowed to
more than two years between two succeeding technologies. Energy efficiency of information processing systems, in terms
As the geometric scaling provided a critical aspect of energy of energy per operation, has been intertwined with progress
reduction, this has slowed energy efficiency. in computing for decades. Specifically, the energy per bit
per transistor of computing systems has decreased by 27×
2. There has been a slower improvement in DRAM memory
over the last 50 years due to a combination of innovations
speed compared to processor speed.
in geometrical scaling, materials, devices, interconnects,
3. Power constraints are driven by more stringent requirements memory, hardware, and architectures, together with new
for mobile devices, data centers, and all consumer devices. methods in algorithms and software. Nonetheless, even
with these improvements in energy efficiency facilitated by
4. Multiple design trade-offs, including challenges of thermal
geometrical scaling, supercomputers needed for large-scale
management, have led to the premise of dark silicon,
scientific computing have required significant increases
which is defined as those parts of a heterogeneous chiplet
in total power consumption to address larger and more
package that can be turned off when not used in concurrent
complex scientific computations.
operations.

5. The accelerated use of machine learning across all applications, For example, in June 1997, ASCI Red supercomputer at
including sensing, automation, autonomous cars, smart Sandia National Laboratories passed the TeraFlop milestone
grids, etc., has caused a data deluge. Given the unsustainable with a power consumption of 0.85 MW. In May 2008, the
trajectory, the U.S. Department of Energy has embarked on a Roadrunner System at Los Alamos National Laboratory
roadmapping effort for enabling sustainable computing . 4
passed the PetaFlop milestone with a power consumption
of 2.35 MW. During those 11 years, the power requirement
In the context of computing, energy efficiency is closely linked only increased by a factor of 2.76. This was enabled by an
with performance. The computing performance possible with architectural innovation to transition from homogeneous
a fixed power is defined by the energy of computing (in terms of x86 CPU nodes to heterogeneous CPU-Cell Video Gaming
energy used per unit of computing operation). On average, the accelerators. In June 2022, the Frontier System at Oak Ridge
energy efficiency of computing has improved exponentially, National Laboratory (ORNL) passed the ExaFlop milestone
enabled by the scaling provided by Moore’s law. While this with a power consumption of 21.1 MW. This took 14 years,
has provided great benefits to society, it has also had the and the power requirement increased by a factor of 8.98.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 39
The longer duration and significant increase in power Figure 2.1: Energy estimated per operation for
requirement to reach ExaFlops can be traced to a technology different products and processors from 2010 to 2022
in Joules/Instruction. The closed circles represent
tradeoff between geometrical scaling and the complexity
floating point operations, while the open symbols
of heterogeneous compute nodes in a large-scale, massively
represent integer operations per second9 (courtesy
parallel processor architecture. of Sadasivan Shankar, SLAC National Laboratory).

In Figure 2.1, energies are plotted in units of Joules per

instruction for different execution types. The energies
are computed from the power and the peak number of
instructions per second for integer 4-bit (INT4), integer 8-bit
(INT8), floating point 16-bit (FP16/BF16), floating point 32-bit
(FP32), and floating point 64-bit (FP64). The energies are
based on either floating point or integer operations.

As depicted in Figure 2.1, the energy of operation (instruction)

for a supercomputer in a given year can be more than 1000x
of that required for the most energy-efficient integer
operation. The data transfer to and from memory does form
an important aspect of energy consumption, as seen by the
energy difference between that of a single instruction and
that of a bit switch, resulting in a higher bit utilization based
on the top-down analysis. Another critical factor is that the
rate of increase in performance of microprocessor speed is
higher than that of DRAM memory7. Options to reduce energy
usage associated with data access include using architectures
in which memory and compute are proximate, use of low
energy, low-latency interconnects like optical components
especially for long data paths8, reuse of data before writing it
in memory, more efficient materials and devices for memory
(e.g., using fewer transistors in SRAM), etc.

In the absence of such dramatic improvements in energy-

efficient computing, sustainability concerns for high-
performance computing will likely limit further increases
in power capability for supercomputer facilities and public engaged in all aspects of microelectronics from materials,
cloud data centers. The combination of advanced packaging, design, architectures, hardware, and algorithms with the goal
emerging technologies, and codesign with new architectures, of 1000x improvement in microelectronics and computing
algorithms, and software will support the SRC Decadal Plan energy efficiency in two decades. The metrics currently extend
goal of achieving a 1000x to 1,000,000x increase in computing- over all layers of computing from materials to algorithms and
energy efficiency over the next two decades. software. The EES2 initiative serves as an organizing principle
designed to help decrease the energy of computing. In turn,
To address unsustainable trends in energy consumption in this is expected to meet new energy requirements and offers
microelectronic systems in an ever-expanding digital world, a path to technology leadership that yields economic and
the Department of Energy (DOE) Advanced Materials and other public benefits.
Manufacturing Technologies Office (AMMTO) is leading the
development of an R&D roadmap, titled Energy Efficiency The roadmap has effectively divided its scope into seven
Scaling for Two Decades (EES2). The EES2 roadmap is a specialized working groups (WG): Materials and Devices; Circuits
collaborative effort between Federal agencies, corporations, and Architectures; Advanced Packaging and Heterogeneous
academia, and international organizations and companies Integration; Software and Algorithms; Power and Control

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 40
Electronics; Metrology; and Benchmarking Manufacturing including specific technologies and their impact on energy
Energy Efficiency and Sustainability. The table below provides a efficiency compared with incumbent technology, will be
high level overview of the technology roadmap for 5 areas that included in the EES2 Roadmap, which is expected to be
impact energy efficient computing. More detailed information, published in the first half of 2024, but are not included here10.

Table 2.1: Energy Efficiency for Computing and Microelectronics*

EES2 Energy
Working Efficiency Near Term (0-5yrs) Mid Term (5-10 yrs) Long Term (10+ yrs)
Group Pathway
Building upon CMOS Technology- Beyond CMOS including Novel Advanced Device Architectures
Technology compatible Transistors, Interconnects, devices, Device Architectures, with heterogeous systems including
Directions Memory with innovations in materials/ integration with Interconnects and Energy Efficient ways of information
processes Memory processing
• As dimensions decrease, reducing • Demonstrate novel devices with
Materials and Devices

passive power including leakage is performance exceeding CMOS in

critical key metrics while improving energy
efficiency
• Materials for reducing parasitic • Down-selecting from a wide
dissipation, and understanding • Growth of defect free materials for breadth of materials, designs, and
fundamental interfacial behavior devices reliant on novel materials/ approaches that fit need
Challenges and material interactions material systems
• Performance loss during
• Understanding gap between • Technology and process modeling integration with conventional
theoretical and actual device of devices and integrated systems technologies
performance
• Integration of novel materials
• Trade-off performance and and fabrication technologies with
reliability with energy efficiency conventional CMOS fabs
Domain-Specific Architectures Design, Integration, and Compute in Memory
Technology including ASICs/FPGAs as Accelerators Manufacturing of heterogeneous Analogue-Digital-Optical integration
Directions for Heterogeneous Integration in systems for distinct Applications with for different Applications with Energy
Chips and in Packages Energy Efficiency as a design variable as a design variable
• TCAD and ECAD Simulations
from devices to circuits is still
complicated; Multi-scale models
that can enable evluating
Circuits and Architectures

trade-offs of Energy with other

• Efficient Co-design with
Technology requirements
Architecture-Hardware-Algorithms
for the entire computing stacks • 3D stacked technologies need
fundamental studies as well as • Software difficulties are preventing
• Increasing trends in new ASICs may integration
methods for power delievery and
drive to heterogeneous integration
Challenges thermal management • Circuits/Architecture changes
not to be adaptable to other
systems • EDA: Heterogeneous systems are needed to increase energy
are hard to design, especially efficiency of CIM technologies
• Energy Efficiency communication
with multiple domain specific
and Clocking for inter-system and
architectures but AI may help
intra-system”
• Energy is still not part of design
tool flow at the chip level and at
the packaging level
• Sorting and Testing Tools needed

Potential Contribution to 1000x <10k 10-100x 100-1000x or more

*Courtesy of Department of Energy EES2 Team/Working Group Chairs: M. Ahmed, J. Atulasimha, J. Ballard, J. Baniecki, A. Bhavnagarwala, J.
Booth, B. Hirano, C. Green, N. Johnson, T. Kaarsberg, D. Lu, N. Li, P. Fischer, R. Jones, T. McDonald, S. Misra, P. Nagapurkar, E. Salman, T. Shah, P.
Sharps, K. Shimizu, E. Taylor, and S. Shankar

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 41
 Table 2.1: Energy Efficiency for Computing and Microelectronics (cont.)

EES2 Energy
Working Efficiency Near Term (0-5yrs) Mid Term (5-10 yrs) Long Term (10+ yrs)
Group Pathway
3D Heterogeneous Integration at
Technology Thermal Engineering, Reliability, and New methods for integrating Devices, the Packaging level for different
Directions Interface Materials Interconects, and Memories architectures and hardwares across
multiple technology nodes
Heterogeneous Integration
Advanced Packaging and

• Integration of diverse devices with

different functional performance,
• Thermal engineering for Systems in and reliability characteristics
the Package needs to be well-understood and • Stacked devices require new novel
characterized thermal managment techniques
• Thermal resistance at interfaces
Challenges needs to be characterized • Lowering resistance and • 3D Monolithic technologies face
capacitance is needed for next performance limitations in higher
• CTE material mismatch can cause tiered technology due to thermal
generation interconnects
cracking thus lowering heat budget constraints
removal” • Packaging, Testing, and Reliability
of systems are driven by the
complexity of systems
Technology Energy-Aware Algorithms and Optimization of memory access in
Improved Training Algorithms
Directions Software algorithms
• Algorithm and Software Design for
Energy Efficiency for both Multiply • Achieving continual/sequential
Software and Algorithms

and Accumulate ( in addition to learning

MAC Operations, Fetch, etc..) • Optimization depends on
• Dynamical precision change which
• Algorithms with lower complexity includes energy efficiency during architecture
and mixed precision computing • Software compatibility
Challenges
• Scheduling work both temporally • Data/dimensional reduction and • Use of AI to write software
and spatially for lowering energy specificity for energy, performancce, and
and also with low-carbon impact Accuracy
• Energy monitoring designed in
• Near-real-time resource availability algorithms as a dynamical option
disseminated to participating and at the system level”
nodes
Technology End-to-end power delivery for Use of wide bandgap power devices Power delivery for photonic
Directions sustainability in data centers and optimized technologies integrated circuits
Power and Control

• Low carbon footprint power

Electronics

distribution for data centers and • Need for low capacitance

• Bulk (substrate) and epitaxial
within systems photodetectors, low energy
growth
Challenges modulators, array optics
• Energy modeling of internal power • Passive components (magnetics
conditioning • Low power monolithic Si photonic
and capacitors)
links
• Incorporation of renewable energy

Potential Contribution to 1000x <10k 10-100x 100-1000x or more

2.2.2. Energy Efficiency of Power Electronics lines and distribution is top to bottom. The evolving power grid
still has a small number of large power plants, but these large
Grid
producers of electrical energy are augmented by many small
Energy-efficiency improvement opportunities for the power intermittent power producers—distributed energy resources
grid extend to the manner in which electrical power is (DERs) that include wind and solar farms. Power generation and
generated, transmitted, and distributed. The U.S. electrical transmission is decentralized with small-scale transmission and
grid is transforming away from a legacy structure with a small distribution that support bidirectional electrical energy flows.
number of large power plants that supply electrical energy
to widely distributed loads via a centralized “hub and spoke” The evolution of the power grid aligns with several
model. In this structure, transmission is based on large power opportunities to increase energy efficiency.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 42
1. New decentralized grid architectures require advanced goal there are several challenges that must be overcome,
power electronics to control the flow of energy from such as those related to scaling, power consumption, and
generators to both loads and grid-scale energy storage. thermal constraints.

2. The use of edge computing and AI/ML methods will provide

At the device level, as scaling pushes beyond 5nm to the 2-3nm
low-latency decentralized and distributed control of the
process generations, vertically stacked nanosheet transistors
Smart Grid.
are becoming increasingly more important. At 1nm and beyond,
3. As data center and cloud computing becomes a larger possible transistor designs include complementary FETs
fraction of the total nationwide load, there is significant (CFETs) and vertical transport nanosheet FETs (VTFETs). These
opportunity for efficiency improvements from reducing the architectures have the potential to offer advantages in terms of
5+ rectification and step-down stages to direct conversion reduced leakage currents, improved electrostatics, and better
from medium-voltage distribution-feed AC power to low- gate control, which can lead to lower power consumption and
level DC voltages (1–5 V). improved energy efficiency of the device. At the interconnect
level, backside power distribution is a key disruptive innovation
4. The R&D of new ultra-wide-bandgap semiconductors will
that can also help enhance energy efficiency by reducing
enable higher power, more efficient, smaller, and cheaper
losses in the power delivery network. The energy cost of
power conditioning systems.
data movement dominates the chiplet and package power
footprint (see Chapter 4). Architectural paradigm shifts are
Electric vehicles
needed to reduce data movements and associated energy cost
In the context of power electronics, electric vehicle (EV) and develop new data-processing paradigms, as discussed
requirements are focused on energy-efficiency and in Chapter 4, Section 2. Enhanced integration techniques
sustainability improvements that arise from the shift from for realizing 3D chiplet stacks with fine-pitched face-to-face
internal combustion engines (ICE) to battery electric vehicles connections between chiplets offer another way to reduce
(BEV). In August 2022, California became the first state to data movement costs. 3D integration offers energy-efficiency
pass a law ending the sale of ICE vehicles and requiring BEV improvements with shorter interconnects and improved
or plug-in hybrid EVs by 2035. The Nordic region, Denmark, signal integrity, but thermal management challenges are
Finland, Iceland, Norway, and Sweden, already have a exacerbated. Device and interconnect innovations, as discussed
significant fraction of EVs due to government incentives to in Chapter 4, Section 3, are also needed to realize additional
reduce or eliminate Value Added Taxes, road taxes, and tolls. energy-efficiency gains in a Heterogeneous Integration system.
In 2022, 86% of new car sales in Norway were EVs. Additional opportunities for energy-efficiency improvements
are also discussed in Chapter 7, with respect to HI, and Chapter
EV battery-pack reliability, safety, and lifetimes already benefit 5, with respect to photonics. All of these areas need to continue
from cell-level IoT sensors and control to monitor charge level, to be developed to dramatically reduce the overall energy
temperature, and other state measurements on a fine-grained consumption of microelectronics.
level. Continued advances in AI/ML will increase energy efficiency
and performance metrics such as the charging rate of the In addition, as artificial intelligence (AI) and machine learning
overall EV battery. For the U.S., the adoption of EVs will increase (ML) methods evolve with advanced techniques like Generative
with the buildout of a nationwide charging infrastructure. This AI, and Graph Neural Networks, they are increasingly being
provides another important load for the nation’s power grid, used across a myriad of applications, including materials
and many of the technology advances for power electronics for discovery, natural language processing, autonomous vehicles,
the power grid will also benefit the performance and electrical and beyond. Given the exponential growth of these AI/ML
efficiency of BEVs and plug-in hybrid EVs. applications, specialized architectures have been proposed
and designed for energy-efficient performance. An analysis
2.2.3. Challenges, Future Needs, and Possible of heterogeneous computing systems with CPUs, GPUs, and
Solutions AI accelerators in a variety of deployment scenarios, including
HPC, Cloud, and AI/ML edge applications for both training
Improving the energy efficiency and power consumption
and inference, show significant growth in the demand for
of microelectronics is essential to sustain the industries
computations, as well as some important trends. First, scaling
projected growth. As such, the SRC Decadal Plan set a goal
in terms of energy efficiency has slowed down compared
of achieving a 1000x to 1,000,000x increase in computing
to ideal geometrical scaling. Hence, the energy-efficiency
energy efficiency over the next two decades. To achieve this

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 43
improvements are being increasingly placed on lower bit
precision and integer instructions, given its relevance to
2.3. Environmental
increased AI/ML applications. In addition to the slow-down Sustainability: Product Design,
and precision-dependent energy efficiency, AI/ML applications
such as Natural Language Processing (NLP) are used to parse
Development, Manufacturing,
vast amounts of literature in all languages and also enable and End-of-Life Management
computer-aided translation between the different languages
The need for microelectronics will continue to rise over
and foundation models. This has also resulted in significant
the next decade with the increasing demand for consumer
energy usage for training. Even with conservative estimates, if
electronics, the continued reliance on chips in the automotive
the current trends were to persist, the energy consumption
industry, the expected growth of electric cars, the rising
in training alone will more than offset the energy efficiency
implementation of Internet of things (IoT), AI, ML, and
from geometrical scaling or that due to architectural
wireless communication. Therefore, as chip manufacturing
advances. It is possible that the computational requirements
increases over the coming years to meet this rising demand, in
for training NLP models may be many more orders of
combination with the increasing complexity of semiconductor
magnitude higher than the estimates, especially for large-scale
devices, it is imperative that microelectronics, materials, and
scientific computing.
processes are designed with environmental sustainability in
mind spanning the entire lifecycle of a product.
In order to attain sustainable computing with practical
constraints, it is important to use energy efficiency as an
Decreasing the environmental impact of microelectronics
additional design variable that bridges design space trade-offs
and associated products will require a continued
across architectures, algorithms, and hardware and software
commitment across the entire semiconductor supply chain
technology. This may need a different framing of computing,
and ecosystem to:
from a general-purpose solution to bespoke computing
systems that are finely tuned end-to-end, specialized for • Lower greenhouse gas (GHG) emissions (e.g., CO2, SF6, CH4,
many applications using co-design with energy efficiency as a N2O, HFCs, PFCs, NF3, etc.) (Scope 1, 2, and 3 emissions**).
key attribute. MAPT capabilities will support the integration
• Develop processes that minimize environmental releases
of composable hardware that include chiplet-based custom
and waste generation, as well as use less input materials
domain-specific accelerator designs with chiplets for
and natural resources.
commodity processor cores, memory, and network interfaces.
Energy-efficient computing performance will drive the creation • Identify alternative chemistries and processing methods
of a full stack that includes system software, algorithms, and that are safer, more efficient, and more effective.
applications that can be modular and usable across many
• Develop circular economy pathways for process materials
customized computing technology advances, from innovations
and end-of-life finished goods to increase reuse or recycling.
in materials to complex heterogeneous systems.

2.3.1. Factory Operation and Tool Design

In addition, there is a need to reduce the number of compute
operations (or operations per second) to perform a function Sustainable manufacturing needs to consider the full factory —
while increasing efficiency (operations per second per power). tool specifications; support environment; sourcing, distribution,
New methods in algorithms, software, and intelligence at and dispensing/reusing of materials and resources (e.g.,
the edge may also present opportunities to save energy by electricity, water); and facility generation, maintenance, and
minimizing data movement. updating. At the tool level, optimization of the manufacturing

**The Greenhouse Gas (GHG) emissions Protocol Corporate Standard, which is a private sector initiative, classifies a company’s GHG emissions into
three ‘scopes’. Scope 1 emissions indicate direct greenhouse gas (GHG) emissions that are from sources owned or controlled by the reporting
entity. Scope 2 indicates indirect GHG emissions associated with the production of electricity, heat, or steam purchased by the reporting entity.
‘Scope 3’ indicates all other indirect emissions, i. e., emissions associated with the extraction and production of purchased materials, fuels,
and services, including transport in vehicles not owned or controlled by the reporting entity, outsourced activities, waste disposal, etc. Scope
3 emissions occur in the value chain of the reporting company, including both upstream and downstream emissions. It is important to note
that Scope 3 emissions of a reporting entity are Scope 1 and 2 emissions of another company. Thus to make a true and lasting impact, each
company needs to continue to build their own capabilities to reduce their GHG emissions by conserving and reducing their overall energy use and
increasing the use of renewable sources of energy.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 44
 Table 2.2: Power Grid Energy Efficiency Technology Roadmap

Energy Efficiency
Current Near Term Mid Term Long Term
Technology
Solid State Power Solid State Power Solid State Power
Substation v1 Substation v2 Substation v3
Goals R&D Challenges Conventional Substations
Up to 34.5kV, Up to Up to 138 kV, Up to All Voltages, All
10 MVA 100 MVA Power Levels
Power Converter “As the electric power Modular, flexible, and scalable for multiple applications with high
Architecture system changed over time reliability and built in cyber-physical security
with different generator
Grid forming and Autononymous/
technologies, different Local intelligence;
Converter Controller synchronization; AI and Distributed
Substation Application

loads, and different system self-aware and

and Communications Wide Area Controls; Peer to
requirements, substations auto-configuration
Connectivity peer
and their components have
also evolved to provide Fault and Over-voltage Tolerant;
Converter Protection advanced functions and Withstand electromagnetic interference Adaptive / Dynamic;
and Reliability features, including: and meets basic impulse level; Manages self healing
• Stability control in steady- inrush/fault currents
state and transient conditions <150kVA, >96%, <125kVA, >96.5%, <100kVA, >97%,
Solid State Power Substation

Converter System • Power flow control to 2MW/m^3, 5MW/m^3, 10MW/m^3,

Cost and Performance minimize system congestion 10 year mean time 20 year mean time 40 year mean time
• More efficient delivery of to failures (MTTF) to failures (MTTF) to failures (MTTF)
power over long distances
Block/Module Cost • Sharing of power between <$20/kVA, >97%, <$15/kVA, >98%, <$10/kVA, >99%,
Converter Building Block

and Performance asynchronous systems 5W/cm^3 10W/cm^3 20W/cm^3

Drivers and Power • Monitoring to improve

≥1.7kV, $0.10/kW ≥3.3kV, $0.10/kW ≥10kV, $0.10/kW
Semiconductors control, protection, and
maintenance
Dielectric, Magnetic, 2,000kV/
• Voltage control for energy 160kV/mm, 0.1H/m, 600kV/mm, 1.0H/m,
and Passive mm, 2.0H/m,
conservation and managing 6.0x10^7 S/m 1.0x10^8 S/m
Components 1.5x10^8 S/m
violations
Packaging and • Increased reliability through > 10,000 W/(m^2
> 500 W/(m^2 °C) > 1,000 W/(m^2 °C)
Thermal Management surge protection and limiting °C)
fault currents
Distribution Asynchronous, Fractal, Hybrid, and Multi-
Grid Architecture • Adoption of cyber and
Platform Paradigm Frequency Paradigm
physical security measures to
Grid Integration

meet evolving standards” Graceful

Dynamic Fault
Grid-Enhancing Coordinates with Degradation and
Detection and
Technologies (GET) Existing Production Automatic Black
Adaptive Protection
Start
Tools and models capable of analyzing advanced controls,
System Modeling and
power flows, short circuits, faults, power quality, dynamics, and
Simulation
transient stability
Static Line Rating (SLR) and
Grid-Enhancing Technologies (GET)

Ambient Adjusted Rating

(AAR) are mostly either
conservative or coarse and
crude approximations. In
2022, the Federal Energy
Increase existing Increase existing Increase existing
Dynamic Line Rating Regulatory Commission
US transmission US transmission US transmission
(DLR) of High Voltage (FERC) is further investigating
system capacity system capacity system capacity
High Capacity the usage of Dynamic Line
by 10%-15% by 15%-20% by 20%-25%
Transmission Line Ratings (DLR). This capability
(comparing to AAR) (comparing to AAR) (comparing to AAR)
tracks the potential of DLR to
provide flexible transmission
capacity and optimize the use
of existing infrastructure, in
order to reduce the need for
transmission expansion.

Solution available for Additional development Significant development effort Information only.
manufacturing work needed. needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 45
process can reduce the use of electricity, water, gases, 2.3.2. Chip Design
material consumption, and waste generation. Tool choices
A chip’s energy consumption has a direct impact on a product’s
and equipment layout can impact a number of factors, such
overall power consumption and energy efficiency. Thus, it is
as support equipment for facility filtering, water cooling/
important to ensure that chips are designed to be increasingly
heating, waste abatement, and factory cooling and ventilation.
energy efficient while still meeting the key requirements for
Similarly, the distribution network of facilities is intimately
each application. For optimal results, energy efficiency must
tied to the tool recipes and utilization, factory layout, product
be addressed at each stage in the lifecycle of microelectronics,
loading, and mix. Correct sizing of both the tools and facilities
starting at the design phase. This means that design practices
can impact demand.
that take into consideration the potential environmental
impact of chip design choices needs to be infused into the co-
Every tool, manufacturing process, material, and factory is
design process and the EDA toolchain.
different, thus, there is no single solution to help reduce
the overall environmental impact of a fab. However, design
Specifically, cell libraries that take into consideration processing
principles do exist, and specific designs can be quantified
steps with a lower environmental impact need to be developed
by taking a “systems of systems” approach to help identify
and suitable metrics must be in place to understand the
opportunities for process and factory enhancement. These
potential environmental impact associated with each cell
opportunities are more easily implemented at the tool
library component. This will allow for design tradeoffs to
design stage and as part of the design of the full factory.
be made between performance, power, and environmental
Considerations can include but are not limited to:
sustainability. Specifically, the metrics need to capture
• Designing tools to enable better reuse of spares and environmental considerations such as energy and water
collaterals, recycling of components and/or systems, consumption as well as chemical and material use associated
and energy efficiency over the entire lifetime. For with the fabrication and design (which are dependent on
example, elimination of water by switching to a purely dry the technology node and the fabrication process), as well as
manufacturing process can help with water utilization, if the those associated with the operational and disposal phases.
trade-off with the energy usage is not severe. These considerations can then be extended to the chiplet
level as an “environmental” cost. The cost of a chiplet has
• Decreasing facility demand by enabling tool hibernation or
several components (e.g., performance, connectivity needs,
low usage modes between processes or during low utilization.
energy, environmental sustainability) and each of these cost
• Running high-utility demand processes during local off-peak components will have an empirically assigned weight which
energy demand timeframes, which can benefit both cost indicates how much the specific cost factor contributes to
and local energy supply. the overall chiplet cost. The environmental cost of the chiplet
can then enable the SiP integrator to make the tradeoffs
• Implementing localized alternative energy solutions, such as
in choosing a particular chiplet over another when the
fuel cells, solar, wind, and micro-nuclear to offset or replace
application needs for a SiP are disaggregated into a set of
fossil fuel energy sources.
chiplets for heterogeneous integration.
• Designing more intelligent tools using sensors to validate
materials being consumed, monitor air emissions (e.g., criteria Finally, sustainability-aware practices need to be percolated
pollutants and GHG emissions) and wastewater discharge, up to the software stack, requiring appropriate facilities to
and monitor changes in facility demand for quicker response. be present and exercised during the use of the SiP. The far-
reaching implications of sustainability across the entire lifetime
• Designing tool layouts to better optimize the factory
of a SiP require a revolutionary change to be made in the EDA
ambient and/or processes. For example, relocating high-
toolchain and the software stack. There is a commensurate
heat-generating tools to areas that allow higher ambient
need to develop this sustainability-aware mindset and the
temperatures or recycling heat for process water heating.
necessary infrastructures for incorporation into materials
• Developing tools and factories that are fully digital and innovation, process development, design (at all levels), use,
autonomous. Apply AI and/or digital twins for optimization and disposal steps. This is a future and long-term need, but it is
of capacity and volume allocation to tools that fully encouraging to see some early efforts in this direction.
comprehend tool availability, location in the factory, cost
of facilities as a function of time, and factory environment
(such as ambient temperature).

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 46
 Figure 2.2: Application driven co-design for sustainability.

2.3.3. Material Selection In addition, the number and complexity of chemical laws and
regulations is unprecedented and will continue to increase,
To continue to drive innovation and achieve the desired
necessitating the need to continuously monitor emerging
functionality required by today’s market, the demand
laws and regulations on a global scale. These laws are
for new and innovative materials and chemistries is
often motivated by a paucity of knowledge regarding the
increasing. At the same time, there is also a need to develop
environmental behavior and toxicity of chemicals. In some
more efficient, more effective, and safer materials and
cases, like per- and polyfluoroalkyl substances (PFAS), there
chemistries. In the 1980s, fewer than 20 elements were
is an absence of even basic physicochemical data on many of
utilized in semiconductor fabs. Today, fabs are using over 50%
these chemicals, which makes it virtually impossible to predict
of the non-radioactive elements in the Periodic Table. The
their potential toxicity and environmental fate and transport.
environmental, health, and safety risks associated with the use
In the absence of basic information to inform safe use, and/
of new materials and chemistries must be fully understood
or demonstrated technology for the control of releases,
and available at the time suppliers introduce them to the
legislators and regulators are motivated to ban rather than
market. Having a detailed understanding of these potential
stipulate the conditions under which they can be used safely.
risks during the development phase enables the industry to
make critical business decisions and allows the industry to
Therefore, it is important to understand basic physicochemical
take more proactive measures in selecting safer materials,
data (e.g., water solubility, octanol-water partitioning
designing out product-content issues, and eliminating
coefficient (Kow), etc.) to better model the potential
chemicals of concern when possible. Without sufficient
environmental and human health risks (e.g., mobile,
environmental, health, and safety data, there is risk that new
persistence, bioaccumulation potential, toxicity) associated
materials may be incorporated into manufacturing processes
with these chemistries and to aide in the identification of
only to later discover that they need to be replaced or the
more environmentally preferable options when feasible.
processes that use them re-engineered.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 47
It is imperative to ensure that critical data needed to AI for materials discovery and materials understanding has
make informed business decisions pertaining to chemical/ the potential to substantially accelerate the development
material choices is collected and made available early in and application of more environmentally sustainable
the development cycle. One approach to accomplish this is materials and chemistries (i.e., safer, biodegradable, improved
developing standards of practice or guidelines for chemical recyclability, etc.).
suppliers that establish a minimum data set needed to better
determine the potential toxicity and environmental fate Some potential approaches are:
of new chemistries. Similar approaches have been taken in
• Geometric Deep Learning (GDL) for analyzing and
the past, such as with the development of SEMI guidelines
understanding complex materials and molecular systems,
for acute chemical safety hazards to ensure, for example,
which can serve to approximate complex simulation
information on chemical stability is understood before
techniques like Density Functional Theory (DFT) and
introducing new chemistries.
molecular dynamics (MD)11,12.

From an environmental perspective, one of the greatest • Generative AI technologies, such as sequential methods
challenges facing the semiconductor industry today is the use like Generative Flow Networks (GFN)13 and Reinforcement
of PFAS, a chemical class representing more than ten thousand Learning (RL)14 for materials to accelerate discovery for
different compounds that are used pervasively throughout many both solid-state and molecular materials. This includes the
industries including the semiconductor industry. Given their development of novel materials design environments and
potential persistence, bioaccumulation, and toxicity, regulators novel algorithms to resolve such dynamic environments and
and policymakers globally are taking actions to mitigate the determine optimal conditions for different kinds of synthesis
potential impacts of these chemicals. There needs to be a focus and fabrication steps where time-dependent information
on understanding basic physicochemical properties to better matters. Non-sequential generative AI, such as diffusion
model the potential environmental and human health risks models15, can be used to create novel material designs that
associated with these chemistries. At the same time, there also have certain desired properties.
needs to be efforts undertaken to identify more benign PFAS-
• Natural Language Processing (NLP) tools like Chat-GPT
free alternatives and make those transitions where possible. In
have shown the great promise of automating knowledge
applications where no known alternatives currently exist, the
extraction across a variety of tasks. Adapting existing NLP
industry needs to optimize processes where PFAS are essential
tools and developing new tools tailored to sustainable
to minimize use and develop efficient and effective controls
manufacturing needs could lead to new insights for
and abatement technologies to prevent environmental
materials discovery and process design16,17.
releases. Finding equally performing alternate materials over
the long term that will not affect overall processing yields and
The above-mentioned AI technologies can be integrated into
throughputs will be a challenge. Given the multiple properties
self-driving materials laboratories, which provide end-to-end
that PFAS provide, it is unlikely there will be a universal
automation framework of materials discovery, fabrication,
replacement for PFAS, but rather a combination of specific
and testing. This circular, closed-loop process consists of AI-
solutions. It is also important that sufficient EHS data is available
guided materials selection for a given application, automated
for any possible alternatives to avoid regrettable substitutions.
synthesis of a given material, and automated material
characterization. For example, a recent paper by IBM highlights
New integrated software tools are needed to bring together
how AI, high-performance computing, and robotics can be
leading-edge computational tools (e.g., modeling and
used to accelerate the discovery of more environmentally
simulation from atomistic to mesoscale) and high-throughput
preferable chemically amplified photoresists18. Work is
experimental tools (e.g., physical chemical characterization and
also being done by Lawrence Berkeley National Laboratory
synthesis), while simultaneously allowing for predictions and/
Laboratories, the Acceleration Consortium, and the University
or optimization against key performance metrics. Such tools
of British Columbia to create functional examples of such a
are essential to help optimize for both key performance
closed-loop AI-driven framework.
metrics and environmental, health, and safety metrics. Tools
encompassing co-optimization of performance metrics and
2.3.4. Wafer Fabrication
environmental, health, and safety metrics will help accelerate
the discovery of more sustainable materials and chemicals The manufacturing of microelectronics is resource intensive,
without compromising the performance of the product. and considerations for the potential environmental impact

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 48
 Table 2.3: Overview of PFAS use within semiconductor manufacturing, parts, and tools(19)

Application PFAS Attributes

Thermal stability (low and high temperatures); low volatility; chemically resistant; good
Photolithography: photoacids, antireflective
compatibility with photoresist; transparent at key wavelengths; strong non-nucleophilic
coatings, immersion barriers, surfactants
photoacids; inert; good solubility
Etching gases/chamber cleans:
tetrafluoromethane (CF4), High selectivity, surface reaction, and etch rate; F-containing gas forms a volatile compound
hexafluorobutadiene (C4F6), with Si substrate
octafluorocyclobutane (C4F8)
Advanced packaging materials: adhesives, Chemical compatibility; required photoactive hydrophobicity/ wetting control; reduces
substrate buildup, flux surface energies; high-temperature stability; defoaming; surfactant
Nonfoaming; high selectivity for SiO2; low particulate adhesion; excellent surface
Wet etch chemistries
smoothness; nonreactive with other chemicals in etch formulation
Heat transfer fluids/thermal test fluids used to
Low viscosity and low-temperature dependence of viscosity; appropriate dielectric
maintain process temperatures (-60⁰C to 80⁰C)
properties; wide operating temperature range; low surface tension; chemical stability
in test equipment
Low volatility; low outgassing; low-friction coefficient; chemically inert; low propensity to
Lubricants, greases, and oils physically migrate from the component; thermal stability; insolubility in organic chemicals;
low gas/chemical solubility
Articles containing fluoropolymers: Inertness; low flammability; thermal stability; resistance to chemical permeation; low coefficient
semiconductor manufacturing equipment and of friction; optical properties; mechanical properties; electrical properties; processability,
facility support equipment resistance to bacterial growth; long service life (>25 years)

of a new technology node need to be an integral part of all Semiconductor manufacturing consists of three main stages:
phases of the technology, from research to product design the formation of raw silicon wafers from an ingot of crystalline
and development to manufacturing at scale. Currently, silicon; the fabrication of integrated circuits onto the wafer
however, there is no universally accepted approach on how within fabs, and the packaging and testing of a finalized chip
to evaluate the potential environmental impact associated product. At each stage there are multiple steps and sub-
with new technology design activity. For example, much of processes. For example, the wafer-fabrication process includes
the environmental impact associated with manufacturing material deposition, photolithography, etching, chemical-
is accounted for using resource-usage metrics (e.g., energy mechanical planarization (CMP) and doping, all of which include
consumption, water consumption, GHG emissions) and, the use of highly specialized and sophisticated chemistries that
therefore, does not provide a comprehensive picture of all must meet multifaceted performance criteria due to the many
environmental impacts. Furthermore, there is no consensus interlocking process steps.
as to the most appropriate functional unit to normalize
environmental metrics, and metrics may vary between Depending on the design, each semiconductor chip might
different technology nodes. In general, metrics need to be require anywhere between 1,000 and 2,000 steps to
comprehensive enough to include assessments of: produce it. A recent study performed20 by the Belgian
research institute imec extended the Design Technology
• Chemical and material properties, usage, and process safety
Co-Optimization (DTCO) framework to include environmental
• More environmentally preferable alternatives and recycling metrics like energy consumption, ultrapure water usage, and
greenhouse gas emissions. The researchers found that the
• Occupational exposures and controls
amount of electricity (x3.46) and ultrapure water (x2.3)
• Environment discharges and controls/treatment needed to produce a wafer, in addition to greenhouse gas
emissions (x2.5) per wafer, increased when going from a
• Waste handling
28nm node to 2nm node. According to the findings of this
• Resource consumption study, the back-end-of-line (BEOL) was the most energy and
resource intensive relative to front-end-of-line (FEOL) and
• Process optimization to minimize chemical consumption
middle-of-line (MOL) because of all the metal layers that are

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 49
introduced. Thus, there is an innovative opportunity that into the semiconductor manufacturing process (e.g., modeling
exists in optimizing or reducing the complexity of BEOL and simulation tools, data for PI systems, etc.) may help lead to
processes and minimizing the industry’s overall environmental more sustainable products and processes by introducing novel
impact with respect to energy use, raw material use, and process schemes, equipment, and product designs.
chemical use during the chip fabrication process. Plus, as
semiconductor transistor complexity continues to increase Lastly, improvements in software tools are also needed to
and device features continue to shrink, the number of metal help facilitate structured data collection and evaluation of
precursor chemicals will likely continue to increase. Therefore, the potential environmental impacts associated with changes
it is critical to use these materials safely and ensure they can in the wafer fabrication process and packaging. These
be managed in an environmentally sustainable fashion. tools should be made open so that both small businesses
and research institutions can avail themselves of these
Within the chemical industry, process intensification is an capabilities*. Furthermore, metrics need to be agreed upon
important and long-standing strategy for reducing the to make comparisons possible between different technology
environmental impact of chemical manufacturing. Utilizing nodes, especially between traditional monolithic systems
various techniques focused on reducing waste, energy and HI technologies. The development of a common set of
consumption, and raw material usage collectively enables environmental metrics will better enable the quantification
a more sustainable and cost-effective manufacturing of the environmental impact of design, technology, and
process . There is a continuing need for process
21–24
manufacturing choices such that progress can be tracked over
intensification techniques to be integrated into semiconductor time. Environmentally significant aspects may vary depending
manufacturing to help improve the efficiency and sustainability on the process or technology node, but environmental
of the manufacturing process. Some examples may include: intersects that should be assessed include material use,
chemical use, water use, electricity consumption, and waste
• Nanoscale processing, such as atomic layer deposition (ADL) and
generation. Identifying the most significant environmental
plasma-enhanced chemical vapor deposition (PECVD), to help
aspect of any new technology choice will highlight areas
reduce the consumption of raw materials and reduce waste
that could benefit from further optimization early in the
by enabling the precise deposition of thin films on wafers.
development cycle. In addition, an overall emphasis on recycling
• Membrane separation to help purify and recycle process and/or circularity at the material and chemical levels may
chemicals, thus reducing the generation of waste and mitigate downstream issues related to effluents and e-waste.
minimizing the use of raw materials.
Photolithography
• Virtualization to help identify process inefficiencies and
provide insight to process optimization opportunities that The most advanced chips have more than 70 photolithography
improve performance and environmental sustainability. layers, many of which are highly interconnected such that a
seemingly small change in one layer can impact the yield of a
• More efficient equipment designs25 that integrate sensors
process three or more steps further down. Integrating these
and control loops that enable data-driven improvements in
successive patterning steps is highly complex. Therefore, there
real time.
is no room for accepting substitutions of photolithography
materials with even slightly inferior alternatives. In this regard,
Process intensification relative to conventional process
the key concern for lithography chemicals such as photoacids,
optimization provides an interesting framework to improve
antireflective coatings, immersion barriers, surfactants,
efficiency and reduce the environmental impacts of
and others, is the need to develop PFAS-free alternatives.
semiconductor manufacturing by minimizing the generation
As discussed above, increasing concerns regarding toxicity,
of waste and optimizing the use of raw materials and natural
persistence, and bioaccumulation potential present a challenge
resources. Research into integrating these techniques more fully
to using PFAS for essential applications in a sustainable manner.

*Imec is developing a virtual fab that helps quantify the environmental impact of fabricating an IC chip. The cornerstone is a
web application called “imec.netzero” that combines process level data on tools, input materials, utility models, fab timing and
process flows. The output is flexible and can be used to generate emissions for an average fab at different technology nodes.
The results reveal high emission sources and identify areas of in the fabrication flow that should be targeted for improvement.
A public version of this software should be released during the summer of 202326.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 50
Figure 2.3: Sustainable manufacturing needs to consider the full factory — tool specifications, support environment, sourcing, distribution, and
dispensing/reusing of materials and resources (e.g. electricity, water). Further, the most feasible time to effect technology change is during
product design and development. Therefore, environmental considerations need to be an integral part of product design and development
and semiconductor devices and processes need to be designed with circularity in mind, meaning processes are designed to: 1. minimize the use
of raw material (e.g., cobalt, aluminum, copper, chemicals, etc.) and natural resources (e.g., water and energy); 2. use more environmentally
preferable materials and chemicals; 3. recover more materials to reduce waste; and 4. minimize environmental releases. (adapted from Ref 19)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 51
Further, as technology scales to sub 7 nm nodes, extreme requirements for patterning at the smallest dimensions.
ultraviolet (EUV) lithography wavelengths are needed to To this end, there are several efforts being undertaken by the
achieve the required resolution. Multi-processing steps (e.g., industry to identify and reduce processes with the highest
double patterning) and numerical aperture enhancements GHG emissions28. Given the higher energy requirements of
are insufficient to meet cost, yield, and emissions targets. EUV over the immersion lithography, it is important that these
However, a single EUV patterning step consumes more energy be extended to the design of the lithographic processes and
than the 193nm immersion lithography that preceded it. The equipment for higher energy efficiency.
lower efficiency and the resulting higher input power (~5X) for
EUV is evident when doing both top-down estimates (based Etching Gases / Chamber Cleans / Chemical Deposition
on energy and power specifications) and bottom-up estimates
As both logic and memory architectures currently trend toward
(based on bond energies in eV). (See Table 2.4.) For this analysis,
vertical integration, the additional etch and deposition steps
the deposition/growth and etch energetics are bound at the
needed will largely drive process gas consumption. These
low end (2.1 eV) and high end (8.42 eV), which correspond
process gases have high global warming potential (GWP) and
to copper-metallic bond energy and copper-tantalum bond
persist in the environment for many years. For companies to
energy, respectively. The total energy per bond varies between
reach their GHG emissions reduction goals, they must develop
3x and 5x for EUV compared to double patterning in 193 nm
processes with greatly reduced emissions, either through
technology. These top-down and bottom-up estimates seem
replacement gases, more efficient use of the high GWP process
to be consistent in indicating significantly higher energy
gases, improved abatement technologies, or a combination of
requirements for the EUV processes, which are likely to increase
all these efforts.
as technology nodes scale below EUV wavelengths.

Targeting improved destruction or removal efficiency (DREs)

It is worth noting, however, that despite the increase in
for the gases identified as the largest potential contributors
energy consumption associated with EUV, the overall GHG
(e.g., NF3 for CVD cleaning steps) will do the most to reduce
emissions (scopes 1 and 2) by logic node per wafer has
the environmental impact of near-term manufacturing. As no
decreased since the introduction of EUV because EUV
current abatement system can reach 100% efficiency, process
eliminates multiple patterning strategies that demand many
optimization to reduce the total gas usage is another avenue
other process steps in addition to lithography27. Yet, given
to reduce emissions. Techniques based on AI and ML have
the higher energy requirements for the EUV lithography
been recently shown to improve signal to noise in endpoint
processes as technologies scale to smaller dimensions,
detection for sensitive processes.
it is still important to continue to look for opportunities
to decrease energy requirements by increasing the
In light of these considerations, industry efforts should focus on:
efficiencies in processing through optimum design of the
processing equipment (e.g., increasing wall plug efficiency), • Developing HFC and PFC abatement systems that can
considering alternate bottom-up processes (e.g., directed achieve higher DREs (99.99%) without generating
self-assembly, growth from solutions, etc.), and minimizing hazardous air pollutants, NOx, CO, and other GHGs.

Table 2.4: Energy requirements for EUV processes.

Deposition/ TOTAL Energy % for

Wavelength Process Flow Litho Etch Litho Etch
Growth per Bond (eV) Lithography
Double
193 nm Min 2.1 6.41 2.1 6.41 2.1 19.12 67.05%
Patterning
Double
193 nm Max 8.42 6.41 8.42 6.41 8.42 38.08 33.67%
Patterning
Single
193 nm Min 2.1 91.67 2.1 95.87 95.62%
Patterning
Single
193 nm Max 8.42 91.67 8.42 108.51 84.48%
Patterning

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 52
 Table 2.5: Global warming potential and • Developing more processes that consume the input high-
atmospheric lifetimes of various gases GWP gases more efficiently.

Global Destruction • Evaluating cleaning-time changes to yield in plasma tools

Process Warming Atmospheric or Removal and characterize how to set end of recipe limits.
Gas Potential Lifetime (yrs) Efficiency
(GWP100yr ) (DRE) • Reduce nozzle flushing (at start) and post-endpoint for

CF4 7,380 50,000 0.89 cleaning/etching using excessive quantities of PFCs that
lead to higher emissions. Excessive run-time on such recipe
C2F6 12,400 10,000 0.95
steps is typically related to fear-of-yield issues.
C3F8 9,290 2,600 0.99
• Develop appropriate empirical models for predicting
c- C4F8 10,300 3,200 0.98
optimal use of PFCs for non-processing/cleaning steps on
CHF3 14,600 228 0.98 CVD/etch tools.
CH2F2 771 5.4 0.98
It should be noted that many of the efforts listed above are
CH3F 135 2.8 0.98
significant undertakings with timeframes spanning at least
NF3 17,400 569 0.95 five to 10 years. In the interim, efforts can be made to reduce
SF6 24,300 1,000 0.95 inefficiencies in existing processes, particularly with respect to
cleaning recipes for process chambers and long-duration etch
N2O 109 273 0.60
processes, such as through-silicon via (TSV) etching where the
GWP and lifetime values from the IPCC 6th Assessment Report (2021),
DRE from the 2019 refinement to the 2006 IPCC guidelines on national dimensions required span hundreds of microns. Recent work
GHG inventories. by Isowamwen, et al.29, demonstrated that the total gas use of
SF6 and C4F8 in a TSV etch process could be reduced by ~30%
• Evaluating alternative etchant or cleaning gases and (averaged between both gases) while maintaining ~98% of the
processes that are effective, safe, and have a lower global desired etch depth and equivalent sidewall roughness to the
warming potential, both for the gas and its byproducts. At baseline condition. This was achieved through trade-offs with
present, a variety of fluorinated gases like CF4, C2F6, SF6, an increase in the RF power utilized. However, it does signify a
NF3 and HFCs are used for plasma etching and chamber notable starting framework through which other such process
cleaning. The choice of chlorofluorocarbon (originally, optimization can be carried out.
replaced with fluorocarbons in the 90s) and fluorocarbon
chemistries was based on the use of silicon/silicon dioxide Chemical mechanical planarization (CMP)
wafers in combination with the use of organic lithography
CMP is one of the largest producers of wastewater. The use of
masks, as well as to provide the ability for anisotropic
ultrapure water is expected to increase as the complexity of
etching of features. The fluorocarbon chemistries supply
the scaled logic nodes increases due to the higher number of
the reactivity needed to break Si-O bonds, while CFx
CMP and other wet steps. To reduce the overall environmental
polymer provides selectivity to the mask and provides
impact of the CMP process and reduce the industries use of
sidewall protection during anisotropic etches. However,
water, the industry needs to prioritize:
these chemicals can be hazardous, have high GWPs, and can
be difficult to destroy via conventional thermal abatement • Improving processes to recover and recycle abrasives.
technology. Thus, alternative chemistries that are safer
• Evaluating more benign and/or easily treatable surfactants,
with lower GWP would be advantageous.
chelating agents, and metal passivating agents. Currently,
• Evaluating alternatives to N2O for use in deposition a wide variety of azoles compounds are used in CMP and
processes. N2O is used extensively in deposition processes wet chemical processes to aid in selective etching/materials
and is difficult to abate. As such, it represents one of the removal and inhibit corrosion. However, azoles are potent
largest unabated GWG emissions in the industry. Thus, nitrification inhibitors and can exert aquatic toxicity.
there is a need for effectiveN2O reduction systems that do
• Developing more efficient recovery and purification
not produce large amounts of NOx.
processes to increase the reuse of water and raw materials.
• Investigating NOx abatement options for POU (point of use) The generation of ultrapure water itself is resource intensive.
or house (end of pipe) abatement of exhaust emissions.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 53
Heat transfer fluids be designed for recycling and recovery in mind. For example,
efforts should be made to understand if packages can be
Many semiconductor manufacturing processes entail physical
designed to be more easily disassembled for recycling or
and chemical processes that require precisely controlled
repair of a defective chiplets.
temperatures and are thus highly reliant on heat-transfer
fluids. Fluorinated heat-transfer fluids (HTF), have a high
The future direction for the semiconductor industry is to
global warming potential. They are employed in both cooling
disaggregate the large system-on-chip (SOC) die into individual
and heating applications and are required to provide the
cells or chiplets. An advantage of disaggregated architecture
precise temperature-control capabilities. Fluorinated HTF
is the modular nature of chiplets, which enables the reuse
also achieve dielectric conditions that are required for
of chiplets in different projects. Chiplets are designed
specific manufacturing operations within the semiconductor
to integrate with other chiplets through package-level
fabrication process, as well as enable the testing of products
integration. The integration of these individual chiplets into a
to ensure the appropriate performance of the semiconductor
multi-chiplet package is referred to as HI. This approach could
chips within finished electronic products. Leakage and
have several advantages that may reduce the environmental
evaporation of these fluids during use is a source of GHG
impact of microelectronics if designed with sustainability in
emissions. With the exceptions of the hydrofluoroethers and
mind. For example, HI may help minimize waste generation and
most of the HFCs, all of these compounds are very long-lived
extend the life of a system by enabling more efficient repairs,
in the atmosphere and have GWPs near 10,000. The industry
upgrades, or modifications without replacing the entire system
needs alternative HTFs with low GWP that can also fulfill a wide
if defective or malfunctioning components can be isolated
range of performance requirements.
and replaced. HI may also help improve the recyclability
of microelectronics by enabling systems to be more easily
2.3.5. Backend Assembly, Test, and Packaging
disassembled or enable the use of chiplets across multiple
Operations
design. This will only be possible, as noted above, only if the
Electrical and water usage are the two most significant packaging is designed for disassembly.
environmental aspects associated with backend assembly,
test, and packaging operations. For example, deflux is the Examples of platforms for HI are Si interposer and
dominant source of water consumption in backend assembly, reconstituted Fan-Out Wafer-Level Packaging (FOWLP). For
accounting for over 50% of the DI water consumption. Dry the assembly of chiplets to the Si interposer approach, solder
manufacturing is an important vector for the industry to methods are currently used which are either solder-capped
work toward to eliminate all flux-based processes. Hybrid Cu pillars or fully collapsible solder bumps. As mentioned
Bonding Interconnect is an example of one of the possible dry above, these materials do not have a circular waste flow and
manufacturing options. Similarly, as direct write-of-additive are typically incinerated, contributing to GHG emissions. The
and functional materials (such as highly conductive inks and future direction for assembly will migrate toward solderless
dielectrics) continue to evolve, the ability to print substrates technologies such as hybrid bonding, where a direct Cu-to-Cu
and interconnects at the micron scale are likely to emerge. bond is made between adjoining devices, eliminating the need
for solder and flux.
PFAS also cannot be ignored, as it is present in packaging
material, dielectric buildup material, underfills, fluxes, and HTFs. The FOWLP technology does not use any solder or flux materials
Use in underfills and fluxes seem to be two specific uses of PFAS in the assembly of the die embedded in the EMC core, which
where replacements for backend assembly may be possible. is then connected to the adjoining buildup layers. Since the
HTFs are the dominant source of PFAS in assembly and test. solder-attach process is eliminated, this design will have a
Organic substrate materials and processing are more similar to dramatic effect on using less energy for processing and will
fab processes and need much work in PFAS elimination. facilitate greater recycling possibilities. In addition, the Cu-plated
interconnect will have a much-improved electrical performance
With respect to recyclability, solder, integrated heat over a solder type of interconnect. So, the inclusion of hybrid
spreaders, and stiffeners, all have good recycling practices bonding for both HI platforms makes for a more environmentally
for process waste. Underfills, molds, solder pastes, flux, safe and improved electrical performance package design. The
adhesives, tape and reel, etc., do not have circular waste use of hybrid bonding for die stacking integrated in both of
practices, and opportunities exist here to reduce the amount the two HI platforms will enable a higher performance design,
of waste going to incineration. Furthermore, packages need to smaller form factor, and a more environmentally sustainable

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 54
packaging solution. As semiconductor manufacturers continue to chemical may not be viable without the aid of a separation
adopt advanced packaging techniques, it’s important to ensure step that removes and concentrates the chemical of concern
that wafer thinning, bonding, and de-bonding processes are for more cost-effective destructive treatment. Areas that can
efficient and benign. be investigated include:

• Improved characterization and technology for separating

The implementation of low-temperature solder (LTS) in
and recovering photolithography and other chemicals from
surface-mount technology (SMT) also represents a promising
wastewater streams.
solution for enhancing the sustainability and energy efficiency
of electronic manufacturing. LTS paste enables a reduction in • Development of cost-effective technology for the removal
reflow temperatures, which can significantly lower the energy of low concentrations of PFAS, triarylsulfonium, and
consumption during SMT by up to 40%30. In turn, this results in diaryliodonium compounds and/or their photodegradation
reduced GHG emissions and manufacturing costs, promoting products from fab wastewater streams. These chemicals
a more environmentally friendly and economically feasible are typically present in photolithography developer
manufacturing process. The implementation of LTS paste can wastewater in the presence of much higher concentrations
also lead to a reduction in high-temperature (HT) warpage, of tetramethylammonium cation.
which enhances the manufacturing efficiency and product yield.
• Developing point-of-use recycling or wastewater treatment
methods for PFAS, TMAH, azoles, and other chemicals.
2.3.6. Chemical Waste and Aqueous Effluent
• Technology advancements, such as concentrating
For the continued growth of the industry, it is imperative to
techniques for separation of water/solvent and other
develop recycling, treatment, and abatement technologies
mixtures, for improved handling, treatment, and recycling
to ensure that the release of chemicals and GHG is minimal.
of mixed waste streams, which in turn can reduce hazardous
In addition, process effluent should be characterized during
waste generation.
the development phase to ensure an understanding of
process byproducts so that leading-edge semiconductor
2.3.7. Challenges, Future Needs, and Possible
devices can be manufactured in the safest possible manner
Solutions
and environmental issues can be addressed proactively.
To identify solutions that do not shift impacts or cause
Chemical waste unintended consequences, a holistic approach across the
entire lifecycle of a packaged semiconductor device is required
The generation, recycling, and disposal of chemical wastes
to appreciably decrease the potential environmental impact
is an important aspect of the industry’s intersects with
of microelectronics. However, environmental metrics and
the environment, and efforts need to continue to identify
measurements required to comprehensively account for the
opportunities to increase chemical recycling and make
environmental impacts of devices are incomplete and need to
semiconductor manufacturing processes more circular
be extended. Realistically, a full set of environmental metrics
by decreasing the use of raw materials and minimizing
has to be developed, and their relative contributions toward
waste generation.
environmental sustainability need to be properly assessed. This
is a future need and an important area of research that will
Aqueous effluent
better enable the quantification of environmental impacts and
Semiconductor manufacturing requires the use of large allow for progress to be tracked overtime. Once developed,
amounts of water and generates large volumes of wastewater. these metrics can be used for the design of the process
As such, many companies are pursuing efforts to reduce technology, design libraries, and the design process itself,
their impact on local water supplies through a variety of continuing on to chiplet fabrication, integration and packaging,
different approaches such as extensive water recycling deployment and use, and eventual recycling.
programs, particularly in water-scarce regions, and the use
of enhanced wastewater treatment processes. Improving New and novel chemicals and materials are introduced to
the quality of wastewater effluent can be challenging, and the semiconductor industry by chemical and tool suppliers
technology is limited. Many chemicals of concern (e.g., PFAS, at a rapid rate that must not be outpaced by the rate at
PAG cations, azoles, and TMAH, among others) are present which the suppliers provide fundamental information on the
at low concentrations in waste streams that have high flow physicochemical properties, toxicity, and environmental fate
rates, so conventional destructive treatment of the targeted and behavior characteristics of the purchased chemicals, and/

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 55
or the reactive products that are created within manufacturing processes for safer or environmentally more-benign operation.
processes. The introduction of new materials and processes In the absence of proactive chemical management, unexpected
without proper vetting presents a risk of unanticipated regulatory actions on chemicals used in critical applications can
hazardous conditions, and/or the need to retroactively modify be anticipated. Emphasis should be placed on:

Table 2.6: Sustainability checklist

Category Sustainability information needs, methods, and controls

Knowledge of what materials are used in manufacturing processes; how each relates to the
process performance; what the process conditions and reactions are; what transformation
and/or byproducts are produced, including reaction hazards; associated materials and
energy balances
Chemical properties, usage, Knowledge of the physicochemical properties, behavior, reactions, and hazardous
processes, and safety properties of chemicals
Knowledge of the toxicological characteristics and applicable routes of exposure for human
and ecotoxicity

Inherently safe chemical handling procedures that are protective against exposure

Are there more benign alternatives that would be effective for the application?

Are the chemical-using processes well-characterized and optimized for minimal chemical
and resource usage, with minimum byproducts, effluents, and wastes?
Green chemistry and recycling Is there a more benign, less resource-intensive process that could be used as an alternative
to fabricate the wafer device and/or an alternative device structure that could be
fabricated more efficiently with lower impact?
Is there opportunity to shift from a linear model of materials use to a circular model with
designed-in opportunity for recycling and reuse?

Analytical methods for relevant exposure routes

Availability of defined exposure-threshold values that are protective of human health and
can be used as criteria to engineer safe systems
Occupational exposures and Knowledge of potential exposure routes so that effective monitoring and control measures
controls can be put into place
Well-defined and specified engineering controls and procedures for tools and
infrastructure

Knowledge of which PPE (gloves, etc.) are protective for the chemicals in use

Availability of validated analytical methods for air, water, and waste measurements

Availability of specified threshold-limit concentration values that can be used to engineer

and operate systems to protect and are protective of human health and the environment
Environmental discharges and Knowledge of relevant discharge/emissions routes so that monitoring and controls can be
controls put into place and managed
Availability of cost-effective technology for effluent and emission control with known
capital and operating costs

Knowledge of transport, behavior, and fate in the environment

Analytical methods for waste characterization

Waste handling Characterized waste streams

Validated technology for effective destruction or, ideally, recycling of materials

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 56
• Integrating environmental metrics into the design and Figure 2.4 highlights the lifecycle properties of the electronics
development phase of microelectronics. system, and the sustainability characteristics of this phase
are very much a function of enabling characteristics from the
• Develop faster methods and accurate models to identify
process and design phases (CoDesign) and can enable more
potential EHS risks of new chemicals.
efficient and effective end-of-life management.
• Developing more benign chemistries, including reducing
or eliminating the use of chemicals of concern (e.g., PFAS, Electronic waste (e-waste) is one of the fastest growing
NMP, TMAH, onium PAGs, indium, gallium, arsenide) and waste streams in the world (Awasthi et al., 201832). According
their degradation products. to the International Solid Waste Association’s (ISWA) global
e-waste monitoring report33, in 2019 the world generated 53.6
• New innovations in analytical and synthesis techniques and
million metric tons (Mt) of e-waste, and only 17.4% of this was
use of AI/ML methods to help design chemical and materials
officially documented as properly collected and recycled. In
may accelerate the discovery of new materials with minimal
addition, e-waste is sometimes shipped to other countries for
toxicity and decreased environmental impact.
extraction of precious metals, leading to both energy costs
• Investigating the availability of more benign or easily and long-term environmental hazards. Printed circuit bords
treatable biocides. (PCBs), which are challenging to recycle efficiently and in an
environmentally friendly manner, account for ~8% (by weight) of
• Process optimization to minimize chemical and resource
e-waste. Proper recycling is critical because PCBs contain several
consumption in new processes.
hazardous substances that must be managed properly at end
• Investigating material formulations that enable circular waste of life, including mercury, brominated flame retardants (BFR),
streams by using natural fillers or biodegradable formulations chlorofluorocarbons (CFCs), and/or hydrochlorofluorocarbons
and/or increasing the reuse and recyclability of waste. (HCFCs). PCBs also contain a number of valuable substances
such as gold, silver, copper, palladium, gallium, and tantalum,
• Developing cost effective, environmentally benign additive
which can be recycled to become potential new sources of raw
processes, including the potential use of print technologies
materials. Therefore, recycling PCBs have the potential for
versus the more traditional subtractive processes enabled
both a positive environmental and economic impact.
through current photolithography applications.

• Increasing the overall functionality of a chip through In general, e-waste can roughly be broken into four broad
heterogeneous integration (i.e., integrating CPUs, GPUs, and categories:
accelerators on a single chip), thereby reducing the need for
• Consumer Electronics (53%, product life of 18-24 months):
multiple chips.
Over half of the microelectronics produced annually (by
• Designing smaller chips while still focusing on developing volume) go into phones, personal computers, displays, and
processes that are more resource efficient and minimizing other consumer devices with relatively short life spans.
emissions and waste generation. A recent study Eeckhout A large challenge for consumer electronics is efficient
(2022)31 concluded that smaller chip designs could collection methods. In addition, cost-efficient disassembly
appreciably reduce overall emissions by reducing the and ability to upgrade and reuse are also opportunities for
number of wafers needed each year to produce the same improvement. Enabling innovations to help with economic
number of chips—smaller chips equal higher yield. disassembly and reuse at the semiconductor process level
and design level are critical to any success. Concepts such as
2.3.9. End-of-Life Management certified used parts may well make sense as an alternative
to the dark reuse market which exists today.
Figure 2.4 refers to the environmental sustainability levers at
the level of electronics design (IC/Package). At its core, this is • Infrastructure Electronics (24%, product life of up to 60
about the operational characteristics of the electronics in-field months): Large communication centers and data centers
operation, with function, power, and reliability being very utilize a great deal of electronics. At an operational
important considerations. All the design considerations are level, Data Centers provide an opportunity for improved
supported by enabling functionality from Figure 2.3 (process). environmental sustainability through system-level
Figure 2.3 refers to the various environmental sustainability optimization (virtualization, smart infrastructure, etc.). With
levers in the context of process development/manufacturing, respect to end-of-life management, unlike the consumer
which is primarily the operational characteristics of a fab. electronics segment, there has already been a great deal of

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 57
 optimization around architectural reuse (rack-mountable much larger system with other significant costs and
systems, provisioning/reservation/rental cloud models, often connect to critical infrastructure. For most of these
heterogeneous scaling). This segment could benefit from systems, hardware lifecycle requirements are long, and the
enabling innovations on power optimization and advancing cost of updating electronics is expensive. Again, reliability,
tools for failure diagnostics, as well as developing models obsolescence, and future function malleability are critical
to facilitate an improved feed mechanism between systems, concerns, along with hardware and software cybersecurity.
boards, and microelectronics to better characterize factors
that impact chip reliability. As noted, there is a need for innovation and optimization
of the recycling process to shift the economics toward
• Automotive (10%, product life of 80-120 months): The
recycling and reuse.
automotive market is simultaneously accelerating its
use of electronics in three dimensions: electrification,
Critical research questions
infotainment/data services, and autonomy. The warranty
and expected lifetimes of automotive systems can easily • System reuse: How can one accelerate the reuse of
stretch into 10 years. Reliability and obsolescence are critical functional devices?
issues for the automotive industry from an electronics point
• Disassembly: What standards and robotics innovation can
of view, and for electronics end-of-life management, reuse
be used to radically reduce the cost of safe disassembly and
of microelectronics is a large issue. Reliability, obsolescence,
sorting of devices and subcomponents? What innovations
and future function malleability issues are also very
are needed in the packaging and PCB domains to help
important considerations. Given that automotive systems
facilitate easier disassembly? How can the use of epoxies and
are cyber-physical, a great deal of the semiconductor
adhesives be reduced? Are there alternative chemistries that
research has to focus on edge sensor/analog/AI systems.
could be used in place of chemically crossed-linked organic
• Other (12%, product life of over 120 months): Aerospace materials or thermal-set polymers and composite materials?
and Defense (A&D), Medical, Industrial, and Embedded Alternatively, can processes be developed that dissolve
Infrastructure (IOT) markets are increasingly consuming adhesives and epoxies facilitating easier disassembly of
electronics. In this context, electronics are part of a electrical components from the circuit boards?

Figure 2.4: System design for the environment (Statista34).

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 58
• Reuse chips subsystems and certification: What subsystems • Designing efficient and environmentally sound extraction
or chips can be reused? Can these be certified? How can this and recycling methods to recover rare earth metals
be determined with minimal cost? Can this flow also reduce and other precious metals from microelectronics. Up to
the black market for chips, which currently introduces 69 elements34 can be found in electrical and electronic
security concerns? equipment (EEE), including precious metals (e.g., gold, silver,
copper, platinum, palladium, ruthenium, rhodium, iridium,
• Materials processing: How can the cost of materials
and osmium), Critical Raw Materials (CRM) (e.g., cobalt,
processing be reduced? How can elemental recovery
palladium, indium, germanium, bismuth, and antimony),
processes be improved to increase extraction efficiency and
and non-critical metals, such as aluminum and iron. Thus,
reduce the environmental impact of the extraction process?
improving e-waste collection and developing more efficient
• Materials handling and disposal: Can recycling and recovery extraction and recycling methods could have a positive
be conducted closer to where chips are manufactured and impact on the environment and supply chains by providing
assembled to reduce transportation? Is there an opportunity to an important source of secondary raw materials.
use fully depreciated fabs to safely handle all the critical steps
of electronic systems decomposition? Since fabs already have
the infrastructure to handle semiconductor chips, can products
2.4. System-level
be designed with circularity in mind to enable recycling and Sustainability Challenges
recovery of product materials and end-of-life management?
The Office of Energy Efficiency & Renewable Energy35 reports
• What are the key steps in system and component design that that U.S. data center energy usage is roughly 2% of total U.S.
require reimagination to promote reusability and circularity? electricity usage, and data center growth is anticipated to be
20% annually due36 to increasing computing demands as noted
Future industry efforts should focus on:
above. Data centers utilize cooling towers which consume 1.7
• Designing microelectronics and PCBs to enable recovery billion liters of water per day,37 competing with residential
and reuse of materials and eliminate scrap and waste. and agricultural needs. Therefore, the path to reducing both
energy and water usage requires advancement in both
• Developing a solution at the systems levels (snap in/out)
computation efficiency and infrastructure.
that enables the reuse of certain parts components.

• Designing innovative package architectures for heterogenous The majority of data centers use compressor-based chilled air
integration. Can chiplets be designed like Lego blocks that cooling, which consumes 25-35% of the total data center energy
can be snapped together and broken apart? Right now, that is and requires cooling towers which consume water. A solution to
very challenging because of the bonded interfaces. reduce data center cooling energy and water consumption is the
implementation of direct-liquid cooling within computer servers
• Identifying opportunities and applications for chip reuse.
using recirculated above-ambient warm water.

Table 2.7: Key environmental, health, and safety needs for semiconductor fabs, processes, materials, and chemistries.

Attribute Current Challenge 1-5 years 5-10 years 10-15 years

Environmental No universally accepted Develop a common set Becomes part of the
metrics & environmental metrics of environmental metrics design methodology
software tools or approach/framework and open-source tools for
to assess the potential comparing technology nodes, as
environmental impacts well as material, chemical and
of process and material process choices
choices across a
technology lifecycle
No holistic, agreed-upon Develop integrated Becomes part of the
assessment strategy or computational tools for design methodology
framework for picking predictions and/or optimization
less impactful materials of key environmental, health,
while still considering and safety metrics against key
performance needs performance metrics

Additional development work needed. Significant development effort needed for HVM. Information only.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 59
 Table 2.7: Key environmental, health, and safety needs for semiconductor fabs, processes, materials, and chemistries. (cont.)

Attribute Current Challenge 1-5 years 5-10 years 10-15 years

Sustainable Factory operation and tool Develop equipment capabilities Becomes part of
manufacturing design to measure resource equipment design and
consumption and environmental development
releases (e.g., wastewater
effluent, air emissions)
Develop and deploy fully digital Utilize AI and/or digital Becomes part
and autonomous tools twins for optimization of factory
of capacity and volume operations
allocation to tools
Chemical PFAS Continue to develop a
management comprehensive understanding
of the industry’s use of PFAS
and PFAS-containing items (such
as equipment, collaterals, spare
parts, etc.)

Develop, validate, and

implement analytical tools
for occupational exposure
monitoring
Develop, validate, and
implement analytical methods
capable of speciating and
quantifying PFAS, total organic
fluorine, and fluoropolymers in
low concentrations in complex
matrices (e.g., water, air, soil,
finished articles)
Generate information on the Develop and implement
potential degradation pathways treatment and
for PFAS abatement solutions to
prevent environmental
releases (e.g.,
wastewater effluent, air
emissions) for essential
PFAS uses
Develop information regarding Use the data to Becomes part
the environmental behavior develop and validate of the design
and toxicity of PFAS and their predictive toxicology, methodology
potential degradation products environmental fate, and
behavior tools for PFAS
used in semiconductor
manufacturing and to
aid in the development/
identification of more
benign substitutes.

Additional development work needed. Significant development effort needed for HVM. Information only.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 60
 Table 2.7: Key environmental, health, and safety needs for semiconductor fabs, processes, materials, and chemistries. (cont.)

Attribute Current Challenge 1-5 years 5-10 years 10-15 years

Chemical PFAS (cont.) Identify all uses of PFAS Develop and qualify Develop
management and transition to PFAS-free PFAS-free alternatives and qualify
(cont.) alternatives where available where viable alternatives PFAS-free
do not currently exist alternatives
and new
materials that
would enable
the transition
to PFAS-free
alternatives
III-V material (e.g., Develop and qualify more
arsenic, gallium, indium, benign alternatives where
phosphorus) possible
Solvents Enhance process efficiency to Develop and qualify
reduce solvent use more benign alternatives
for solvents such as NMP
Persistent, Supply-chain engagement to Knowledge of Develop
bioaccumulative, toxic, develop comprehensive EHS exposure routes and and qualify
mutagenic, or endocrine data for new and/or proprietary characterization of air, more benign
disrupting chemicals chemicals to identify potential water, and waste effluent alternatives
concerns early in the R&D phase for chemicals of concern where possible

Cost-effective effluent
and discharge controls
are in place
Natural resource Drastically reduce water Develop more efficient recovery Improve the efficiency Becomes
conservation consumption and purification processes to of wastewater part of the
and pollution increase the reuse of water treatment processes by design and
prevention developing cost-effective development
Balance water use and energy concentrating methods methodology
needs to provide the most for separation of water/
optimum manufacturing solvent
equipment water use for new
equipment designs, including Transition to more
cooling, rinsing, etc. benign and/or easily
treatable surfactants,
Evaluate more benign and/or chelating agents,
easily treatable surfactants, biocides, and metal
chelating agents, biocides, and passivating agents where
metal passivating agents possible

Cost-effective designs
are in place and standard
offerings

Additional development work needed. Significant development effort needed for HVM. Information only.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 61
 Table 2.7: Key environmental, health, and safety needs for semiconductor fabs, processes, materials, and chemistries. (cont.)

Attribute Current Challenge 1-5 years 5-10 years 10-15 years

Natural resource Drastically reduce scopes Optimize process recipes and Becomes part of the
conservation 1 and 2 GHG emissions38 combine steps and processes to design methodology
and pollution across the semiconductor reduce energy consumption
prevention supply chain to Develop gas-abatement and Becomes part of
(cont.) meet the scientific destruction technologies equipment design and
recommendations from development and/or fab
the UN Intergovernmental operations
Panel on Climate Change
Better control the leakage Becomes part of
(IPCC) that is necessary to
of heat transfer fluids and equipment design and
limit earth’s warming to
refrigerants development
1.5 °C above pre-industrial
levels Work with suppliers to Continuous supplier Continuous
align targets with IPCC engagement supplier
recommendations and monitor engagement
progress

Work to build supplier

capabilities where needed
Cobalt, Tungsten, Design and develop efficient Implement recovery
Tantalum and environmentally sound methods
extraction methods to recover
rare earth metals and other
precious metals
Process optimization Improve processes and Becomes part of the
systems to increase reuse and design methodology
recyclability of materials and
minimize waste and emissions
End-of-life management Design microelectronics and Becomes part of the
PCBs to enable recovery and design methodology
reuse of materials and eliminate
scrap and waste

Additional development work needed. Significant development effort needed for HVM. Information only.

The technology has demonstrated a reduction in cooling • Innovations in convection heat transfer. Novel coolants or
energy usage by > 90% and elimination of water consumption high-pressure gas systems could be of interest but would
compared to compressor-based chilled air cooling. 39
need to have a global warming potential (GWP) < 10 and an
ozone depletion potential (ODP) of zero.
Immersion cooling liquids have high GWP and contain PFAS.
• PFAS elimination from immersion fluids.
Additionally, power delivery from the wall to the processor
has multiple inefficiencies and energy loss. So, data transfer
With regard to data transfer between systems, enabling smart
between packages, systems, and outside system efficiency can
sensing meters and distributed monitoring can help better
be improved.
match supply and demand from heterogeneous decentralized
sources for improved efficiency. The interconnects between
Some of the thermal opportunities directly applicable to the
server components can consume a significant amount of
semiconductor industry include40:
power, so implementing power-efficient interconnects, such
• Innovations in materials and interface solutions. Innovations as silicon photonics, can reduce energy consumption and
in conduction and thermal interface systems include the use improve sustainability.
of novel materials that are coefficient of thermal expansion
matched to semiconductors.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 62
Server power delivery inefficiencies can be addressed by 2.5.1 Challenges, Future Needs, and Possible
improving the energy efficiency of processors to reduce Solutions
the amount of power required to run data center servers.
Emphasis should be placed on developing a skilled workforce
Improving the energy efficiency of memory chips can help
to create sustainable electronics from R&D and technology
reduce the amount of power consumed by servers. Innovations
development through chip and system design, materials
in voltage regulators and passives can also be potential
selection, manufacturing, packaging, assembly, and test.
solutions spaces. However, it’s important to keep in mind that
Co-design and integrating environmental considerations into
using energy-efficient processing, communication, and storage
these course classes is a challenge that must be overcome.
infrastructures together with automated load-dependent
management techniques that avoid overprovisioning of IT and
cooling capacities will only reduce losses in the power-delivery
network. Inefficiencies in the overall power-delivery system can
2.6. Acknowledgements
be addressed in a variety of ways. For example, AC-powered The MAPT authors are grateful to adopt and include the
data centers can be addressed by using high-voltage power high level energy efficient computing technology roadmap
delivery to server aisles and local conversion at the aisles that is part of the DOE AMMTO efforts underway for their
and by ensuring the power phases remain balanced. Another Energy Efficient Scaling for 2 decades (EES2) initiative. This
alternative is to convert incoming AC power to high-voltage computing R&D roadmap is included here as Table 2.1. The
DC power and deliver this directly to servers that use power EES2 Working Group Chairs are, M. Ahmed, J. Atulasimha, J.
supplies that do DC-to-DC conversions to chip-level voltages. Ballard, J. Baniecki, A. Bhavnagarwala, J. Booth, B. Hirano,
C. Green, N. Johnson, T. Kaarsberg, D. Lu, N. Li, P. Fischer, R.
Jones, T. McDonald, S. Misra, P. Nagapurkar, E. Salman, T. Shah,
2.5. Workforce Development P. Sharps, K. Shimizu, E. Taylor, and S. Shankar. As noted in
Section 2.2.1, the full EES2 R&D Roadmap will be available
A resilient workforce with the right knowledge, skills, and
in the first half of 2024. The efforts of these working group
abilities (KSA) will be needed to create a future of energy-
chairs and the MAPT authors will help ensure these two
efficient computing and sustainable technologies, materials, and
roadmap documents are synchronized at the high level.
manufacturing. For all the energy efficiency and sustainability
challenges described above, teams of people with rich
combinations of KSA are needed to solve them. Depending on
the specific problem and scope identified above, the disciplines
needed will include engineers of all types (automation, biological,
chemical, civil, electrical, environmental, industrial, maintenance,
manufacturing, materials, and mechanical), toxicologists,
ecologists, chemists, physicists, mathematicians, statisticians,
data scientists, economists, climate scientists, and others. A key
result of the roadmap is the recognition that, for all of these
disciplines, sharing a baseline of sustainability knowledge and
practice will be critical to solving these problems, including
discovering and creating sustainable materials, processes,
technologies, and systems. This knowledge must be integrated
into disciplinary coursework while students are first becoming
subject-matter experts as undergraduates, or else it will never
become part of the working-level KSA of the MAPT workforce.
The KSA must then be deepened and put into practice in more
advanced courses, MS degrees, research, on-the-job training, and
industrial practice. For example, ABET could include a student
outcome related to energy and sustainability so that eventually
all future engineers have this awareness and basic skillset.
Looking ahead, multidisciplinary teams are needed to identify
and fill the gaps and create optimal sustainability solutions.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 63
Contributors
Brooke Tvermoes (IBM) – Chair Bob Leet (Intel) David Speed (GlobalFoundries)

James Ang (PNNL) – Vice Chair Nathan Marchak (IBM) Sarah Wallace (Texas Instruments)

Henning Braunisch (Intel) Matt Marinella (Arizona State University) Kevin Wolfe (Intel)

Emily Gallagher (imec) Mitul Modi (Intel) Chuck Woychik (Skywater Technology)

Kanad Ghose (SUNY-Binghamton) Mark Poliks (Binghamton University) Tim Yeakly (Texas Instruments)

Brett Goldsmith (Paragraf) Rahul Razdan (Razdan Research Institute) Kashyap Yellai (SRC)

Carol Handwerker (Purdue University) Dave Robertson (Analog Devices) Todd Younkin (SRC)

Tengfei Jiang (University of Central Florida) Sadasivan Shankar (SLAC)

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The green transition of the IC industry, Vision Paper, IMEC 2022

Osakpolo Isowamwen, Nathan Marchack, Devi Koty, Qingyun Yang, Hien Nguyen, Steve Molis, Scott LeFevre, Marco Hopstaken, Andy Metz,
29

Jeff Shearer, Robert L. Bruce, “Characterization of TSV etch from a sustainability standpoint,” Proc. SPIE 12499, Advanced Etch Technology and
Process Integration for Nanopatterning XII, 124990H (1 May 2023); https://doi.org/10.1117/12.2658564

C. Hotvedt, “Energy Consumption Reduction Using Low Temperature Solder Alloys”, IPC APEX EXPO 2023, Jan 21 - 26, 2023, San Diego
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S. Sahasrabudhe et al., “Low Temperature Solder - A Breakthrough Technology for Surface Mounted Devices,” 2018 IEEE 68th Electronic
Components and Technology Conference (ECTC), San Diego, CA, USA, 2018, pp. 1455-1464, doi: 10.1109/ECTC.2018.00222.
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10.1109/MM.2022.3218034.

Awasthi, A.K., Cucchiella, F., D’Adamo, I., Li, J., Rosa, P., Terzi, S., Wei, G., Zeng, X., 2018. Modelling the correlations of e-waste quantity with
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33
https://www.itu.int/en/ITU-D/Environment/Documents/Toolbox/GEM_2020_def.pdf
34
https://www.statista.com/statistics/498265/cagr-main-semiconductor-target-markets/
35
Office of Energy Efficiency & Renewable Energy, https://www.energy.gov/eere/buildings/data-centers-and-servers

Shankar, S. and Reuther, A., “Trends in Energy Estimates for Computing in AI/Machine Learning Accelerators, Supercomputers, and Compute-
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The Greenhouse Gas (GHG) emissions Protocol Corporate Standard, which is a private sector initiative, classifies a company’s GHG emissions
38

into three ‘scopes’. Scope 1 emissions indicate direct greenhouse gas (GHG) emissions that are from sources owned or controlled by the
reporting entity. Scope 2 indicates indirect GHG emissions associated with the production of electricity, heat, or steam purchased by the
reporting entity. ‘Scope 3’ indicates all other indirect emissions, i. e., emissions associated with the extraction and production of purchased
materials, fuels, and services, including transport in vehicles not owned or controlled by the reporting entity, outsourced activities, waste
disposal, etc. Scope 3 emissions occur in the value chain of the reporting company, including both upstream and downstream emissions. It is
important to note that Scope 3 emissions of a reporting entity are Scope 1 and 2 emissions of another company. Thus to make a true and last
impacting, each company needs to continue to build their capabilities to reduce their emissions through improved energy efficiency efforts
and greater reliance on renewable sources of energy.

Chainer T.J, Schultz M. D., Parida P.R. , Gaynes M. A., “ Improving Data Center Energy Efficiency With Advanced Thermal Management”, IEEE
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Transactions on Components, Packaging and Manufacturing Technology 2017, Vol 7, Issue 8

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https://arpa-e-foa.energy.gov/Default.aspx#FoaId14cbba61-e007-42b7-8cef-3724d1e66387

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 65
Chapter 3

Security and Privacy

3.1. Introduction • From the security perspective, describe attack scenarios
defense mechanisms within specific applications.
The future of advanced manufacturing and packaging
technologies is bright, but new technologies bring new attack • Describe the security implications of the movement towards
vectors and novel approaches to subverting existing systems. multi-tenant applications in software and hardware, especially
This chapter identifies some of the emerging security and with regard to heterogeneous integration in packages.
privacy challenges and outlines research areas that address
• Describe security analysis of analog and MEMS sensors,
them. The analysis is systems-driven but emphasizes implications
including their use in modern applications and threat models.
for manufacturing and packaging technologies. This chapter
builds upon existing roadmaps, such as the security chapter of
the Heterogeneous Integration Roadmap (HIR) (https://eps.
ieee.org/images/files/HIR_2021/ch19_security1.pdf). Additions
3.2. Application Drivers
include emphasizing a manufacturing and supply-chain view, as This chapter examines a sample of critical system application
well as analyzing the impact of emerging applications. areas pushing performance, energy, security, and privacy needs,
including data centers, IoT, smart mobile, autonomous vehicles,
General goals wearables and health, aerospace and defense, and networking.
In order to intelligently design this hardware, threat models,
• Comprehensively identify potential hardware security
end-user security and privacy requirements for these areas
vulnerabilities in heterogeneous integration.
need to be explicit and considered from the beginning. The
• Outline feasible strategies to identify security assets table of threats that follows is far from exhaustive but meant
and detect or avoid security vulnerabilities for system- to motivate the vision, emphasizing opportunities for hardware
in-package; define fair metrics evaluating the security mitigations to address these threats.
resilience of implementations.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 66
 Table 3.1: Motivational threats

Threats Descriptions

Exploitation of insecure The difficulty of writing secure software has plagued the industry for decades and will continue
software implementations to be a problem. Many software and hardware architectures and defense-in-depth approaches
depend on reducing the attack surface with trusted hardware.
Exploitation of insecure or Secure update of devices in the field requires authentication of the update.
nonexistent updates
Counterfeiting in Data The ever-increasing demand for computing power motivates Data Centers to pursue HI-based SiPs
Centers to gain better power efficiency and performance. Counterfeiting attacks are a major concern since
the performance and reliability of counterfeit devices, e.g., recycled ones, have been significantly
degraded because of the previous excessive usage, leading to unexpected failures of the complex
infrastructure or service.
Counterfeiting in Due to their sensitive nature, aerospace and defense infrastructure cannot allow devices that are
aerospace and defense potentially under adversarial control. Also, reliability is of utmost importance, especially in the
aerospace segment, e.g., spacecraft and satellites.
Counterfeiting in Wearables and health devices can be exposed to risks from tampering attacks via unauthorized
wearables and health backdoor access. Adversaries could remotely manipulate settings or function in life-critical devices
or could deplete implant battery power to require premature surgical replacement.
Loss of privacy from smart Smart home or wearables data can reveal personal information. Device users should have control
homes or wearables of their data, and privacy policies of these devices should be transparent and understandable.
Attestability of hardware and software may give end users more confidence that privacy policies
are being followed. Software/firmware mechanisms have to be trustworthy.
Privacy risks of Mobile devices, such as personal or health wearables, may connect to healthcare and other service
smartphone-connected providers via a user’s smartphone. On the smartphone the combination of health and geolocation
devices or social media data could lead to unique new privacy risks.
Data integrity attacks Performance and reliability of autonomous vehicles stem from processing incoming data from
for autonomous vehicle numerous sensors and supporting the artificial intelligence algorithms. Data spoofing attacks can
sensor data cause autonomous systems to misperceive the environment.
Real-time requirements There is a need to extend the space of the technologies and accelerators to be robust in real-time,
for applications, e.g., for instance, systems like fire alarms with real-time requirements similar to avionics.
automotive AI, industrial
IoT, and home automation
Attacks against AI-based AI deployments are revolutionizing several domains, including education, finance, healthcare,
systems at the training industrial automation, autonomous vehicles, and cybersecurity. There is a need to protect these
and deployment stages deployments against a myriad of threats. These threats include poisoning the training data,
adding backdoors to the models, leaking sensitive data through data extraction attacks, stealing
model IP through model extraction attacks, and changing model outputs through evasion attacks.
Protection of custom Several contemporary applications rely on AI accelerators for performance. The accelerators are
AI accelerators, and being optimized and customized for performance for each application, often resulting in more
prevention of sensitive data leakage.
data leakage
Piracy of hardware IP As the number of stakeholders in the supply chain increases, so do the potential adversaries.
along hardware supply Modern fabrication systems are globalized, and different untrusted players get access to the
chain critical hardware IP of the manufacturer, which opens the potential to commit piracy. They may
fabricate extra copies of the received golden design and sell it in the open market, and they may
even add malicious designs like hardware trojans that cause Denial of Service (DoS) attacks during
critical operations or create a path for data leakage.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 67
 Table 3.1: Motivational threats (cont.)

Threats Descriptions

Tampering transducer Sensors can be tampered with by applying physical stimuli to the transducer element, addressing
elements of (MEMS) the wanted signal or taking advantage of cross sensitivity. Depending on the magnitude, the
sensors sensor will provide false data or get permanently disabled (e.g., via enforced stiction in MEMS
sensors).
Side-channel and fault- Increasingly lightweight embedded devices can be further boosted with heterogeneous
injection attacks for IoT integration solutions. However, physical attacks like side-channel attacks and fault-injection
devices attacks are problematic because of their relatively simple architecture, resulting in an information-
bearing side channel of low noise and less resilience against external interference with physical
disturbance. The goal would be to mitigate these threats without significant increase in cost,
energy, and performance.
Reverse-engineering of Interposer-based solutions for performance and power density enhancement are becoming
smart mobile processors more popular, such as M1 Ultra20. Processors in smart mobiles are the most profitable type of
microelectronics, and there is concern about reverse-engineering attacks since the IPs are valuable
and sensitive.
Attack analog chiplets An attacker can monitor the temporal power consumption pattern to guess ADC input. Then, an
within SiPs using power overwrite to ADC config registers causes incorrect conversion, affecting ADCs in control systems,
side channels involving sensors, and analog AI accelerators. DoS attacks via injection of noise on shared power supply are
attacker and ADC chiplet/ also a potential concern.
block, specifically in 3D
stacks; ADC configuration
register tampering
Threats to quantum Given the variety of quantum systems, threats here are currently hard to foresee.
computers

3.3. Analog and MEMS with 3D designs. Mitigating PSAs will require not sharing
power rails or power converters with other chiplets. An
Analog
inherently secure technique involves obfuscating the power-
Many IoT SiPs incorporate chiplets that primarily include consumption trace by using internal logic, such as integral
one or more Analog-to-Digital Converters (ADCs) and their power equalizers for critical ADC blocks within ADCs using
support circuitry. ADCs are also used in analog multiply and successive approximation registers1. Similar power equalizers
accumulate blocks within an analog AI accelerator chiplet. can also be used to avoid PSAs in encryption chiplets.
ADCs are vulnerable to a variety of exploits that include power Unintended electromagnetic coupling for PSAs can be avoided
side-channel attacks (PSAs) that reveal the analog input value by using multiphysics analysis tools to detect their presence,
to the attacker, attacks on ADC configuration registers that and the coupling can be avoided through alternative chiplet
can lead to incorrect conversions and disrupt a control system placements on the interposer. The sophisticated analysis tools
that uses the ADCs to sense data used in the control, and DoS for detecting electromagnetic coupling across chiplets do not
attacks that incorrectly disable the ADC. exist today or are, at best, in their infancy. However, a strong
basis for building these tools exists2.
Power side-channel attacks are set up when the ADC
chiplet shares common power rails and/or common power To reduce the attack surface in analog memory accelerators
converters with another chiplet that can be compromised. The using ADCs, retrain the analog AI model to account for process
compromised chiplet can monitor the power consumption variation-induced ADC errors in an analog AI accelerator
waveform (trace) of the ADC chiplet and infer the input value instead of recalibrating the ADC offset directly. This makes it
to the ADC. Electromagnetic coupling can also be the basis difficult to use a generic attack tool. Another similar approach
for getting the ADC power trace in real-time. This is a very is to use the chiplet-specific noise signatures in the resistive
likely possibility with close chiplet placements and particularly RAM memory arrays in retraining the AI model3.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 68
Other ADC attacks can be prevented through techniques such Entire monolithic silicon dies containing the transducer
as limiting access or explicit access control mechanisms to ADC element and the readout on the same silicon die are
configuration registers, the use of anti-aliasing techniques, uncommon, primarily due to process incompatibilities between
consistency checking and many other well-known mechanisms. the transducer and the ASIC process, low flexibility, limitations
to specific process nodes, and yield. A typical MEMS has one
MEMS or more transducer dies, as well as one or more ASICs dies
in one package (see Figure 3.1 below). Interconnections are
During daily life, people are surrounded by tens of MEMS
made through an interposer substrate and bond wires, through
(Micro-Electro-Mechanical-Systems) sensors. All modern
silicon vias, or (in the future), by so-called ASIC caps, which are
smartphones, smartwatches, fitness trackers, or advanced
bonded to the transducer as an integrated component.
earphones contain a large number of MEMS sensors, as
do many forms of transportation (e.g., cars, trucks, two-
The trend is to add more and more intelligence to the MEMS
wheelers, and e-bikes). MEMS are also present in the
sensor itself. Until a few years ago, the ASIC contained a
medical and industrial world. Accessing or altering these
front-end sensor and rudimentary signal pre-processing
sensor data is a tremendous privacy and security concern.
(i.e., filters). Intelligence was added to the MEMS via an
Personal information like health data or location must be
application processor or even via the cloud (intelligence on
protected at all times. MEMS also plays a vital role in private
the edge/edge compute), which reduces energy consumption
transportation as part of safety features, including airbags
and latency. At the same time, privacy is increased and the
and rollover detection, as well as within the electric stability
potential security risks of tampering with data outside the
program for personal and commercial cars and trucks.
MEMS are reduced. Tampering with signals inside a molded
Changing the sensor data can lead to accidents and deaths,
package is significantly harder than signals routed on a PCB
for instance, by simulating a crash to activate an airbag. In the
board. However, this increased computation capability and
industrial environment, MEMS are used for process control
complexity combined with programmability options opens
and monitoring. Changing the output signal of a pressure
new paths to system tamper.
sensor, for example, can lead to catastrophic events in the
chemical industry.
Also on the horizon is integration of RF components (e.g.,
BLE radio) into the same package to partly replace wired
The same attack vectors for pure electronic heterogeneous
connects, which must be considered from a security point of
systems based on ASICS (interface leakage, supply chain
view. An RF component adds the risks of tampering without
attacks, side-channel attacks, chip counterfeiting, physical
the need for physical access to the device.
tampering, fault-injection attacks, and reverse-engineering
attacks) exist in MEMS. However, the transducer element can
In the following section, the MEMS is broken down into four
be attacked or compromised in additional ways and requires
parts: ASIC, transducer, RF, and integration. Specific risks
special attention to ensure full functionality.
regarding security and privacy are briefly discussed for each.

Figure 3.1: Comparison of the chip and package configurations of Bosch

Sensortec BMI055, BMI160, and BMI260 (left to right). Source: Robert Bosch

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 69
ASIC protocols—like BLE—or proprietary. Both have different pros
and cons regarding security and will not be addressed in detail
The same attack vectors as for digital or analog/mixed-signal
here, but they must be considered. Over-the-air (OTA) updates
ASICs apply to the MEMS ASICs. The IP of the ASIC must be
provide the possibility of bug fixing in the field. However, at
protected, and all kinds of HW alterations must be avoided or
the same time, they offer new ways to attack a MEMS system
detected. Reverse engineering must also be avoided to keep
without physical access.
the core knowledge and IP within the country of origin.

Integration
Altering the software and firmware must be avoided or
be detected in current and upcoming programmable and Physical access to a completely molded interposer is complex
intelligent sensors. A program interface is the easiest way and requires very high effort—but it is not impossible. So-
to attack the sensor and its proposed function. The frontend called ASIC cap solutions are even more secure are, where the
circuit connecting the MEMS transducer to the ASIC is usually ASIC becomes an integrated part of the MEMS (for instance
highly customized to reduce unwanted ASIC-transducer via anodic bonding). Removal of the ASIC from the transducer
interference and feedback. This customized design makes is seen as impossible without permanently damaging the ASIC,
it difficult to replace the intended ASIC with a tampered the transducer, or both.
ASIC. However, it is not impossible and must be considered a
potential security risk. A potential security risk is adding a hardware Trojan ASIC
between the transducer and the ASIC, or between the output
Transducer pads of the ASIC and the contact pads of the MEMS, in order
to alternate the signals. The first approach would mean
Opposite to ASIC nodes, MEMS processes are generally
significant design effort to develop such an ASIC. The ASIC
tailored to the specific transducer produced, with extensive
front end influences the behavior of the transducer and must
design loops between the manufacturing fab and the
perfectly match the initially intended design specifications.
designers. Here, there is a very high risk of unwanted
The second approach is more straightforward since standard
knowledge transfer, which can only be avoided by in-house
wire-based communication protocols like I2C are used. These
manufacturing. Furthermore, state-of-the-art MEMS are highly
kinds of alterations can be easily detected using X-ray imaging
complex systems, and just providing GDSII files for the mask
technology. However, since automated x-ray scanning is only
production already leaks significant amount of know-how. Any
done with indicators of malfunction or low production yield,
kind of hardware alterations can be misused to disable the
the likelihood of detection during high-volume manufacturing
sensor completely, such as applying a voltage to permanently
(millions per day) is low.
stick the sensor element, or to introduce incorrect sensor
data, such as adding a bias to the output signal. Different
A multi-sensor package (e.g., accelerometer, gyroscope, and
sensor principles have different cross-sensitivities that need
magnetometer) typically includes more than one transducer
to be understood. A MEMS accelerometer, for example,
die and more than one ASIC. With an increasing number of
is not only sensitive to mechanical accelerations, but also
connections and the likelihood of a weak component, the risk
to acoustic waves. These sensors can be misused as very
increases with the number of dies.
primitive microphones to spy on conversations if, for example,
a smartphone is placed on a table and picks up the pressure
In summary, the core know-how needed to design and
waves of the human voice. Inertial sensors are usually
manufacture all resources must be protected, including
accessible on Android without explicit permission from the
sensors and transducers based on MEMS, analog, or RF
user. Design-for-security standards for MEMS must be developed
components. Novel methods to detect or avoid any kind of
to secure this crucial element.
alterations must be developed for all primary components
constituting assets of the system. Approaches to increasing
RF
ASICs’ security can be adapted and applied. Transducer-
In order to push the integration level continuously higher, specific security methods must be developed without
more computation power/intelligence and new ways of sacrificing the main advantage of these components including
communication must be added. Besides wire-based protocols smaller size, less power, and cost efficiency. All must be
like I2C/I3C or SPI, wireless communication via an RF interface covered under a holistic design-for-security approach.
will be added to specific sensors. These can be standard

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 70
3.4. Digital Processing It will enable full and rapid migration to post-quantum
crypto (PQC). This can be quite challenging since PQC
Traditional isolation and virtualization technologies differs widely in architecture, key distribution, and state
(like hypervisors and OSes) have served the industry management. Developing the science of Crypto Agility will
well on digital processing components capable of answer questions like, “How can systems be designed to be
supporting them. These have recently been extended crypto agnostic and support transparent exchange of the
to provide some assurances around privacy of the data crypto-in-use without any need to re-architect?”; “How can
and applications being run on confidential computing different types of cryptosystems coexist and switchover
architectural extensions. These extensions provide at runtime without compromising security or impacting
stronger isolation and privacy by better isolating the traditional metrics like performance, power, and circuit
applications from the underlying system software size?”; or “How can we support hybrid PQC schemes (i.e., the
and treat layers underneath the end-user customer combination of two or more PQC families)?”.
software stack as untrusted (for example, not trusting
• Post-Quantum Privacy encompasses current privacy-
the hypervisor layer of a cloud provider). Some proposed
enhancing technologies and exploration of replacement
solutions are based purely on cryptographic primitives,
mechanisms that are post-quantum secure. Examples include
others rely on strong security and isolation guarantees
Fully Homomorphic Encryption (FHE), Secure Multi-Party
through the use of formal methods and verification, and
Computation (MPC), Functional Encryption (FE), and Zero-
yet others are enabled by remotely attestable hardware-
Knowledge Proof (ZKP). NIST started the PQC competition,
backed strong isolation mechanisms.
inviting candidate algorithm proposals from around the
world. The candidates can be divided into two categories:
The concern with heterogenous integration is that
Key Encapsulation Mechanism (KEM)/Public-key Encryption,
while these mechanisms have evolved to isolate
and Key-establishment Algorithm and Digital-signature
and protect applications and their data on general
algorithms (DSA). Several alternative candidates were also
purpose processing elements, those mechanisms
announced, and NIST has recently selected candidates (KEM:
could be compromised by other elements of the
Crystals Kyber; DSA: Crystals Dilithium, Falcon, Sphincs+).
system if the mechanisms don’t extend to the other
Crystals Kyber, Crystals Dilithium, and Falcon are based on
components. This problem isn’t unique to heterogenous
lattices, while Sphincs+ is based on hash-based signatures.
integration, and likely similar approaches could be taken
The draft PQC standards with specific algorithm parameters
for traditional SoCs and disaggregated systems where
are planned for 2023, inviting public comment, and these
application functionality may be spread across many
standards will be finalized in 2024. FHE is also based on the
nodes in a distributed system. The challenge is further
building blocks of lattice-based PQC algorithms, such as the
complicated by the lack of isolation mechanisms on many
Ring Learning with Errors (R-LWE).
types of peripheral processing units like GPUs, DPUs, or
microcontrollers. Even in monolithic SoCs, the variety • Low-Latency Crypto fosters research in the development
of operating systems and firmware present a threat to of new cryptography circuits with minimum latency. While
integrity and privacy (https://people.inf.ethz.ch/troscoe/ the circuit size and power consumption are key factors, the
pubs/2021-07-16-OSDIKeyNote-Handout.pdf). latency is very relevant for high-performance computing
(HPC) where crypto is often in the critical path for
Cryptography entering the quantum era performance. Low-latency cryptography is also an important
building block for total memory encryption with minimal
Cryptography continues to be a foundational research
overhead. Example questions are, “What are encryption and
theme. The advent of quantum computers brings new
authentication approaches with optimal trade-off between
threats to classical cryptography, and these emerging use
low latency, area, and energy?” and “How do we design low-
cases require new types of algorithms. The four new sub-
latency block-ciphers with flexible block sizes?”
areas in this domain include Crypto Agility, Post-Quantum
Privacy, Low-Latency Crypto, and Lightweight Cryptography. • Lightweight Cryptography (LWC) can be used for link-layer
(PCIe/CXL/IDE) encryption/authentication based on the
• Crypto Agility encourages research on new paradigms
Integrity and Data Encryption (IDE) standard. Most of the
that allow IT systems to select and update their
lightweight cryptographic algorithms being recommended
cryptography deployments on short notice at run-time to
by NIST are authenticated encryption ciphers, but algorithms
address evolving requirements, regulations, or threats.
suitable for short messages may be useful for interchiplet

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 71
 communication in heterogeneous integration scenarios. NIST • Verifiable trust: Data use requires bilateral trust about how
has announced ASCON as the selected candidate from the the data will be used, as well as its appropriateness and
10 Finalist LWC algorithms. ASCON is a family of lightweight integrity for a particular use.
cryptographic algorithms consisting of the following:
• Data use controls: Data must become self-sovereign,
• Authenticated encryption schemes with associated data persistently enforcing right-to-use policies no matter where
(AEAD) the data resides.

• Hash functions (HASH) and extendible output functions

For a secure data economy, research must encompass several
(XOF)
technologies:
• Pseudo-random functions (PRF) and message
1. Trusted computing: End-to-end protection via decentralized
authentication codes (MAC)
policy enforcement for data and bundled services

One of the advantages of ASCON is that it provides some 2. Distributed ledgers: Decentralized policy, distribution, and
inherent side-channel protection, including an efficient bit- ownership management
sliced implementation of the S-boxes, which prevents timing
3. Expressive usage control: Constrained usage of data that is
attacks since it requires no lookup tables. Furthermore, the
being shared.
low algebraic degree of the S-box (5-bit S-box) facilitates both
first- and higher-order protection using masking or sharing-
Trustworthy enforcement and audit of hardware
based side-channel countermeasures. ASCON has some good
and software compliance
characteristics, such as support for all the modes above, that
might make it suitable for link encryption and authentication. Major cyberattacks and data breaches, such as SolarWinds
https://csrc.nist.gov/projects/lightweight-cryptography or the Sony data leak of 77 million users, have magnified
the need for data protection. Compliance-based techniques
Confidential Computing enable stricter cybersecurity via assurance, regulations,
verification, and auditing of entire hardware (HW) and
Today’s economy is increasingly data driven. For example,
software (SW) ecosystems from development to deployment.
industrial processes optimize manufacturing performance
Current compliance solutions rely on institutional trust
based on data collected, weather models sample massive
coupled with manual inspection and certification. Automation
amounts of data to predict long-term climate change, and
is key to increase trustworthiness of compliance. This will
online services mine our digital footprint to push appealing
require techniques to record evidence of trustworthiness of
products. For all the data collected and processed, much of
supply chains, verify security guarantees, or enforce runtime
it remains siloed. Regulatory controls intended to protect
compliance. Trust can be rooted in evidence from secure HW
individuals from misuse create barriers for data sharing, and
(i.e., confidential computing), so steps in development and
fear of misuse tends to outweigh any potential social or fiscal
deployment lifecycle should become traceable and verifiable.
benefit that might be derived from the data.

To realize this vision, research is needed to build the

To release data for a wide spectrum of use/reuse in a vibrant
foundations and tools that record evidence about HW and SW
and open data economy, we must address both the real
supply chains, as well as runtime environments. To further
and perceived problems of sharing data. The emergence of
improve security guarantees, HW and SW attestation evidence
confidential computing provides a technological starting
can be combined with endorsements from verification and
point, but fundamental research questions must be addressed
analysis tools or audits. This allows for the association of
to enable the free exchange of data through value-based
security guarantees such as “no data leaked to network” with
services. An ecosystem for shared data and the corresponding
entire HW and SW systems. Underpinned by confidential
services will require radical improvement in data economies,
computing, the combination of attestation evidence, trusted
verifiable trust, and related technology.
supply chain, attested runtimes, and security endorsements
• Data economies: How is value ascribed to data where has the potential to transform how compliance is automated,
ownership of data is less about possession than about right- enforced, and reasoned. The goal is to obtain sufficient and
to-use or control? Can the value of data with increasing levels well-defined guarantees from a compute system prior to use.
of verifiable provenance be better qualified, quantified, and
conveyed upon the results of sharing this data?

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 72
Research questions Figure 3.2 presents the threat model of a heterogeneous
integration supply chain, which is critical to analyze the possible
• How can we efficiently integrate attestation of HW
security vulnerabilities. There are four main phases in the
and SW?
supply chain, including pre-integration chiplet development
• How can we validate end-to-end security and privacy and fabrication, heterogeneous integration and assembly,
over distributed heterogeneous compute resources? device packaging, and in-field operations (represented by
the bidirectional arrows above). The roles and corresponding
• What is the most efficient granularity of enforcing
assumptions of each phase are elaborated below.
certain security guarantees?

• How can we understand, validate, and reason about • Pre-integration chiplet development and fabrication:
security and privacy guarantees of a supply chain? In this phase, chiplets are designed by third-party teams
and likely fabricated by offshore (rouge) foundries before
• How can we compose secure systems from components
arriving at the market or integrators. Chiplets might not
with well-defined security guarantees?
be trustworthy as third-party designers/semiconductor
foundries can intentionally inject malicious logic to

3.5. Advanced Packaging and compromise the integrity/confidentiality of security

assets located in chiplets within the same package. The
Heterogeneous Integration interposer layers interconnecting all the chiplets (horizontally
and/or vertically to create a SiP) cannot be trusted either,
The plentiful security assets within heterogeneous
since they are also fabricated by untrusted foundries.
integrated systems present formidable challenges to
ensuring security during integration and in-field usage. • Heterogeneous integration and assembly: Prefabricated
Although microelectronics security threats at individual silicon dies are purchased by integrator entities and then
intellectual property (IP) and system-on-chip (SoC) levels have assembled in a specific topology. Generally, the integrator
gained tremendous importance over the past decades, it is entity and assembly house are considered trusted because
imperative to change the conventional mindset to consider they are stakeholders of final SiP products if they rely
those threats in the context of heterogeneous integration on in-house facilities. However, to reduce the cost, the
due to the paradigm shift of manufacturing and packaging heterogeneous integration might be outsourced to untrusted
of semiconductor devices. contractors, introducing additional security risks at this stage.

Figure 3.2: Heterogeneous integration supply chain and threat model

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 73
• Device packaging: Packaging facilities get stacked dies and chiplet OCMs. Therefore, hardware Trojans can be inserted
encapsulate them in packaging, protecting them against by altering (a) the design-in-design houses or (b) masks in
environmental factors such as moisture and physical damage. untrusted foundries. To detect Trojans in chiplets, statistical
To taint the reputation of system integrators, the facilities methodology can be used to derive a set of test patterns and
may alter the parameters to result in reliability issues and new verification methodologies (pre- and post-silicon) for
even denial-of-service problems on the final SiP products. the excitation of rare conditions at internal signals, as these
are typically chosen as Trojan triggers for stealthy behaviors.
• Untrusted in-field operations: The SiPs suffer from a
variety of in-field threats from adversarial end-users, such • Reverse engineering: When the fabricated chiplets flow
as passive side-channel attacks and active fault-injection throughout the convoluted supply chain, distributors/
attacks, aiming to compromise the confidentiality or intermediate entities with advanced technical potency
integrity of embedded security assets. might reverse-engineer the silicon dies to retrieve design
descriptions, such as layouts, by delayering the chiplets
Security Threats and Mitigations and imaging the structure (interconnects and transistors)
to extract their netlist. Such information can be valuable to
To address mitigation, the potential security vulnerabilities in
competitor companies that can copy the reverse-engineered
each phase and potential design-for-security techniques must
design without spending costly research and development
be identified. Some of the vulnerabilities discussed below
cycles. Because the original functionality has been
have been well studied for conventional single-die SoCs but
corrupted and cannot be easily reused without the correct
not for HI-based systems, which manifest themselves through
unlocking keys, design obfuscation can come to the rescue.
a variety of security applications compromising confidentiality,
integrity, and/or availability of the systems. • Counterfeit chiplets: Because of their potential defects,
insufficient performance, and poor reliability, counterfeit
Chiplet security and trust
chiplets (like overproduced chiplets) from rogue
Chiplet development is similar to conventional integrated foundries or remarked ones (e.g., claiming higher grade
circuits. However, more security risks are becoming possible, or performance) likely induce unexpected failures if they
considering the black-box characteristics of chiplet silicon are integrated into final SiP products. Physical unclonable
to integrators and subsequent chiplet integration. Chiplet function (PUF) primitives or other security primitives can
security and trust solutions aim to mitigate security threats at generate responses by leveraging device process variations,
the chiplet level. thus uniquely fingerprinting every silicon die, serving as an
indication against counterfeit chiplets.
• IP piracy: Some chiplet original component manufacturers
(OCMs) design the hardware and rely on the offshore Real-world attack instances: One of the most prevalent
foundries to fabricate the silicon, which introduces the risks IP piracy techniques is reverse-engineering de-packaged
of IP piracy, since a rogue foundry can extract high-level ICs to extract the physical layout, which can be applied to
design information from the physical layouts for future individual chiplets and SiP systems. For instance, companies
IP infringement. The countermeasures can be passive like Chipworks Inc., which located in Canada, provide
watermarking and active design obfuscation. Watermarking reverse-engineering services that cover microprocessors
embeds a unique identifier (e.g., a sequence of bits stored in and memory devices4. Another form of reverse engineering
dedicated registers) into the chiplet to enable IP authenticity targets FPGA bitstreams by cracking their proprietary formats
verification as proof of ownership. Alternatively, another and recovering high-level abstractions from the binary
popular solution is actively locking the circuitry such that the configuration data5. Although the existence of actual Trojan
original functionality is available only when the correct key implants has not been definitively confirmed, industry and
is applied. Although foundries have access to the details of academia are actively investigating this issue and reporting
obfuscated circuit designs, the unlocking key is unknown and advancements in this field. Microsemi FPGAs are reported to
thus effectively prevents IP piracy. have malicious backdoors, allowing for circumvention of built-
in security features6, while7 recently leveraging a “Blue team
• Hardware Trojan and malicious alterations: Hardware
vs. Red team” approach to implement Trojans in four chips and
Trojan threats can originate from either chiplet OCMs that
demonstrate the effectiveness of their detection solutions.
want to compromise other chiplets at the post-integration
Counterfeit devices have been witnessed in every corner
phase or rogue foundries for tainting the reputations of
of the world—and their quantity is surging given the chip

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 74
shortages and high-tech tension between China and United (FEOL) layers can be fabricated at an untrusted high-end
States. In 2011, for example, counterfeit chips made their foundry, while back-end-of-line (BEOL) higher metal layers
way into the supply chain of military equipment, including are manufactured at a trusted low-end foundry. Also,
helicopters and aircraft .8
physical sensors are suggested for SiP devices to monitor
any potential anomalies in terms of power, temperature,
Design for secure integration
and electromagnetic (EM).
Given the potential threats of malicious chiplets, as well as
Real-world attack instances: None of the above integration-
the hidden interconnects or logic in active interposer layers
time threats have been specifically identified in SiP systems.
from untrusted foundries, the SiP integrators always expect
However, conventional system-level integration, which shares
to enhance the system-level security by integrating more
similarities with SiP integration, has already raised security
components employing design for security. Apart from the
and trust concerns. A prominent case is the “Big Hack”
chip-level security risks, the inter-chiplet communication from
allegation9 reported by Bloomberg. The article claimed that
potentially untrusted interposer layers becomes the major
Chinese hackers inserted small, malicious microchips into
concern in this phase. Design for secure integration targets
computer servers produced in China and utilized by numerous
system-level threats at the time of integration.
major technology firms, affecting industry leaders such as
• Information leakage: The rogue foundry can effectively Apple and Amazon.
cause information leakage problems on plaintext
Design for lifecycle assurance
communication through the covert channels built on top
of stealthy hardware Trojans in the interposers. Also, it is After being fabricated and assembled, individual chiplets need
possible to implant tiny wireless antennas on the interposer to be stacked on the interposer and packaged to be SiP devices.
to create an information-bearing channel carrying sensitive In addition to malicious alteration at the design level, material
information. Moreover, the malicious interposer has the attacks can pose threats at the packaging stage as well.
chance to alter the traffic on the fly to induce functional
• Composition alteration: The silicon interposer is the key
failures or intentional errors. A security patch can be
infrastructure for high-bandwidth on-chip communication.
deployed during the integration time to monitor the inter-
Adversaries can attempt to make the interposer more
chiplet data transaction to avoid unintended data transfer.
vulnerable to unexpected failures by purposefully
Also, given the complexity of in-system communication,
modifying the material composition.
network-on-chip (NoC) infrastructure is getting popular in
large-scale SiP. Securing NoC infrastructure by thwarting • Structure alteration: The rogue facility can modify/replace
attacks, such as redirection of sensitive packets and fake the original mask for interposer fabrication to undermine
packet flooding for denial-of-service, is critical for reliability or directly introduce malicious functionality.
SiP security.
• Process parameter alteration: Intentional manipulation
• Confidentiality and integrity violations: The confidentiality/ of process parameters of the fabrication procedure can
integrity issues should be handled by proper on-chip/ also create reliability and security concerns. For instance,
chiplet cryptographic infrastructure, including encrypted deposition and oxidation need to be very precise in the
communication between chiplets and calling for dedicated order of nanometers for the seed layer and insulation. Once
interfaces of chiplets/interposers. For example, PCIe/CXL/ the parameters are altered, it could result in unexpected
Integrity and Data Encryption (IDE), which is encryption/ insulation, redistribution layers cracking, and through-silicon
authentication based on the IDE standard, can be used for vias (TSVs) breakdown.
secure chiplet communication.
A major category of mitigation solutions against these
• Compromise of security policies: Security policies need threats mainly focuses on security inspection using advanced
to be well designed and enforced in hardware to preserve physical equipment, which entails a variety of characterization
the confidentiality and integrity of sensitive information. methodologies. Using solutions like X-ray photoelectron
However, deliberately implanted Trojans in active spectroscopy (XPS), scanning electron microscopy energy-
interposers—and even external physical disturbance— dispersive spectroscopy (SEM-EDS), and X-ray fluorescence
might compromise or disable them entirely. To this end, the (XRF), the composition information of the selected samples can
active interposer can be protected by utilizing the advanced be obtained for security analysis and assurance certification.
split-manufacturing solution, where its front end-of-line

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 75
SiP devices typically need to serve excessive and long-time making physical attacks such as side channel and fault
in-field operations that require effective solutions against injection feasible options to compromise the integrity and
various threats at in-field phase coming from untrusted confidentiality of security assets. Side-channel attacks
components and external adversaries. leverage the physical properties of a running hardware
implementation, such as power consumption and EM
• Firmware/data tampering: Firmware is a vital security asset
emanations, to non-invasively extract the underlying
to guarantee compliant system boots. For instance, probing
security assets (e.g., the private key of an AES cryptographic
attacks based on focused ion beam (FIB) at the post-
engine). The holistic physical emissions of HI-based SiPs
silicon phase can compromise the integrity of firmware
might become noisier due to more irrelevant switching
and other data, bypassing hardware security protections
activities occurring simultaneously. Side-channel attacks
with negligible footprints and even nullifying tamper-
can still be effective, however, with more measurements
detection measures like active shields. Besides, many
to establish the statistical correlation between the correct
categories of chiplets, e.g., CPU cores and eFPGAs, rely on
(sub)key guess and captured physical emissions (e.g.,
firmware stored in read-only memories to operate correctly.
power/EM traces). Even worse, side-channel attacks can be
Through FIB or other physical attacks, adversaries might
launched in the package of a HI-based system where, for
tamper with the chiplet firmware to provide hackers a
example, a malicious chiplet can tap into the power supply
foothold into the entire infrastructure, evade operating
of the victim, sensing and analyzing the power fluctuations
system-level detection, and disable the underlying
of the target implementation for adversarial purposes.
mechanisms like secure boot or firmware authentication, all
A common observation for both power/EM side-channel
resulting in unauthorized software running stealthily on the
attacks is that the leakage originates from the current
SiP. Moreover, due to the long lifecycle, SiPs need to serve
fluctuations in the power supply lines. Applying power line
in-field (typically > 10 years), and some chiplets should be
conditioning/filtering can effectively alleviate the risks and
upgraded through remote firmware or software updates
make successful key recovery much more difficult.
to address functional bugs and security vulnerabilities.
If a secure channel is not available, man-in-the-middle or • Fault injection attacks: Fault injection attacks physically
impersonation attacks are likely to spoof the software cause glitches to the running implementation, compromising
updates traffic by replacing the software/firmware with the control flow and data integrity to bypass built-in security
malicious binaries. Therefore, a root-of-trust-based firmware mechanisms and/or deduce the security asset according to
authenticity verification needs to be activated to check the faulty outcome (e.g., differential fault analysis (DFA) on
firmware integrity and ensure secure firmware updates AES). In SiP, a larger set of security assets inevitably extend
against attacks such as replay. the attack surface of fault-injection attacks compared to
the monolithic SoC scenarios. Besides, the speed and supply
An extensible root-of-trust (RoT) can be implemented as
voltage of heterogeneous chiplets at various technology
a trusted security microcontroller chiplet that is designed
nodes can be different, increasing the chance of successful
to be verifiable and inherently secure and can run well-
fault injection. Finally, a malicious chiplet from an untrusted
vetted firmware to implement a variety of security policies
facility can suddenly draw a huge amount of current to pull
and associated functions. For example, the OpenTitan
down the power supply of its target when the power rail is
specifications will provide an open standard for such a “Silicon
not decoupled, launching fault-injection attacks inside the
RoT.” Such Silicon RoT chiplets can be extended through
package. Therefore, run-time fault-injection detection is
trusted software and deployed in scale to support larger SiPs.
preferred to continuously detect drastic physical changes
like sudden voltage glitches, EM disturbance, or thermal hot
• Supply chain attacks: As for the supply chain integrity, SiPs
spots, and erase security assets when necessary.
always carry a high price tag because of their great power
density and thus become profitable victims of recycling Real-world attack instances
counterfeits. By establishing integrity throughout the
One of the most well-known instances of firmware tampering
globalized supply chain in a zero-trust assumption, the
attacks is the Stuxnet malware, a highly sophisticated cyber
counterfeit threats regarding SiPs can be mitigated.
weapon discovered in 2010. It exploits multiple zero-day
• Side-channel vulnerabilities: Different from the previous vulnerabilities to infect industrial infrastructure, such as
stages, the in-field phase allows for the physical access nuclear facilities. Specifically, Stuxnet can tamper with
of adversarial end-users to the deployed systems, the firmware of programmable logic controllers (PLCs)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 76
to manipulate their behavior without raising suspicion10. business: the need for safer products manufactured with
Regarding side-channel vulnerabilities, there has been a uncompromised quality.
growing number of reported timing side-channel exploits
in market-leading processors. Spectre11 and Meltdown12 Security Engineering for Safety
pioneered this attack class by misusing the speculative
The FDA’s efforts in cybersecurity were historically informed
execution feature available in Intel, AMD, and ARM processors
solely by guidance documents15, which are recommendations
to access the sensitive data or contents of kernel memory
(not requirements) for how Medical Device Manufacturers
from unprivileged user space. Fault-injection attacks have also
(MDMs) are expected to ensure safety and effectiveness of
grown to be a major security concerns with the emergence
their medical devices. With the enactment of the Consolidated
of the Rowhammer13 vulnerability in dynamic random-access
Appropriations Act of 2023, the Food, Drug, and Cosmetics
memory (DRAM) modules. By rapidly accessing specific rows
(FD&C) Act has been amended and, effective March 29, 2023,
of memory, attackers induce electrical interference that can
Section 524B lays out explicit requirements for submission of
cause bit flips in neighboring rows. This can be exploited to
“cyber devices”.
gain unauthorized access to data or execute malicious code.

FDA guidance on cybersecurity has largely been focused on

3.6. Medical Device software aspects, with less focus on hardware risks. In fact,

Regulatory Approach the FDA’s initial nine-page 2014 guidance entitled “Content of
Premarket Submissions for Management of Cybersecurity in
to Cybersecurity Medical Devices”16 did not discuss hardware at all. Subsequent
FDA draft guidance documents in 201817 attempted to
In recognition of the risks to our national critical infrastructure
include the concept of a “Cybersecurity Bill of Materials
in general, as well as the specific risks of patient harm and
(CBOM)”, with the intention to include hardware cyber risks.
the disruption of care delivery, the regulated medical device
The idea was rejected in a subsequent draft update in 202218
industry is managing cybersecurity with the implementation of
in favor of focusing on Software Bill of Materials (SBOM),
new laws and regulations.
demonstrating both industry’s resistance to tracking hardware
for cybersecurity and FDA’s primary focus on software risk.
In the United States, the Food and Drug Administration (FDA)
is the gatekeeper for market entry for medical devices and has
Yet, the FDA’s 2022 draft guidance, “Cybersecurity in
started to refine its approach to cybersecurity–but not without
Medical Devices: Quality System Considerations and Content
challenges. Regulators need to walk a fine line, however, as too
of Premarket Submissions”, is 49 pages long, mentions
little regulation will lead to poor adoption while too much and
“hardware” 15 times, and specifically includes hardware in its
too rapid regulation will impact the availability of critical and
definition of “updatability and patchability” with reference to
life-saving technologies. This was recently demonstrated in the
“hardware replacement”.
EU with the Medical Device Directive (MDD) to Medical Device
Regulation (MDR) transition14.
The cybersecurity efforts and the supporting documentation
needed for submissions are based on the technical characteristics
Today’s regulatory efforts focus on security engineering
and intended use of devices. The FDA recommends that the
practices and a risk-based approach to cyber risk and
security architecture diagrams should contain details for
vulnerability management. Examining the role of hardware
manufacturer and network assets, including, but not limited
security in a regulated industry like healthcare requires the
to, the device hardware; applications, hardware, and/or other
understanding of two scenarios:
supporting assets that directly interact with the targeted
1. How regulation is being used to improve security and the device; communications/networking assets; and manufacturer-
practical challenges of including hardware. controlled assets.

2. How manufacturers look at security risks that could

Most recently, the FDA has expressed its intention, beginning
compromise their hardware supply chain and, consequently,
October 1, 2023, to reject premarket submissions for medical
lead to compromised or sub-standard products.
devices that lack adequate information regarding cybersecurity19.

Both of these are aspects of a larger security issue that

has the potential to harm patients and negatively impact

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 77
Lastly, cybersecurity is never static, nor is it ever finished or The larger device ecosystem must also be considered, because
“good enough”, leading to regulators’ approach of ensuring devices might represent a point of compromise for their
that security be maintained throughout the useful life of operating environment or may be compromised during service
a product. For example, this is emphasized in the FDA’s or maintenance activities by compromised equipment. The
“Postmarket Management of Cybersecurity in Medical spectrum of risks that need to be considered is wide and can
Devices” (2016) , which requires device manufacturers to
16
include power drainage from a patient-worn device or impact
monitor “cybersecurity signals” and to mitigate vulnerabilities on data privacy and/or integrity due to lack of protection of
discovered in their devices (e.g., by providing patches). data and configuration parameters.

High-reliability Hardware Security MDMs must consider three factors when thinking about
device security: human, hardware, and software. Each
Medical device manufacturers invest considerably to build
component, sub-assembly/chiplet, control system, process,
environments that enable them to create patient-safe devices.
and final assembly has to be evaluated from the perspective
Those investments include the use of materials and assembly
of how a device could be compromised either accidentally or
practices that reduce patient risks and protect company
intentionally. Those efforts might require time and money
intellectual property (IP).
to ensure that data are secure and the device is safe, but
consider the alternative. For instance, what happens if one
MDMs should ensure that a device can’t be compromised,
patient dies because a pacemaker failed due to an exploitable
neither during production nor during operation. For example,
vulnerability? The loss of life is the primary concern, of course,
a manufacturer should ask if and how a discrete hardware
but this event also damages a company’s credibility, elevates
component might cause a device to fail or be exposed to
regulatory and legal risks, and potentially impacts the overall
exploitation, including considerations for how a vendor-
business brand and finances.
supplied sub-assembly or chiplet might expose the final device
to unintentional data leakage or functional disruption.
It is also important to examine the means by which a company
might have their processes and IP compromised. For example,
This establishes the need to consider device protection earlier in
could a heterogeneous device assembly environment be
the design and development of that device. Of course, nothing
accessed from the outside, such as through vendor access
is 100% safe, but establishing safety measurements and a
(e.g., during support and maintenance activities), through
defined acceptance threshold allows for maximum security
unauthorized employee access, through the backdoor
within the given engineering and economical constraints.
of seemingly innocent devices (e.g., printers, USB ports,
routers, access points, unshielded communications, etc.), or
With all those points considered, what should MDMs do to
through unprotected employee devices? The easiest ways
safeguard medical devices, and at what stage in the device
to compromise the safety of a medical device might be via a
lifecycle should they start considering how to safeguard a device?
subassembly, which may go undetected due to inadequate
The answer is that safety needs to be a priority from initial
training, lax process validation, or insufficient quality control
concept, architecture and design, and development through
and supply chain management. Thus, there is a clear need
integration, testing, manufacturing transfer, and production.
to consider device safety from the beginning by creating
formalized and standardized best practices, establishing
Device manufacturers must continually analyze how
risk-based controls and sampling, training employees,
individual discrete components might expose a device to
validating processes, and forensic analysis.
risks, including consideration of sub-assemblies, chiplets,
final assemblies, heterogeneous manufacturing lines/
Taking a holistic view of a device’s development and
processes, control systems, networked systems, manual
production lifecycle allows for the visualization of risks the
assemblers, testing equipment, and packaging processes,
device might be exposed to, even starting at the discrete
as well as systems and processes used for device servicing
component level. As a result, the tangible and intangible
and repair. Consider, for example, how the integration of a
risks to the device (and ultimately the patient) can be
Bluetooth circuit (i.e., a sub-assembly or chiplet) or a faulty
comprehensively identified, and controls and protective
antenna might lead to wireless communications being
measures implemented. Such an approach will guide MDMs as
disrupted or intercepted.
they populate circuit boards, aggregate sub-assemblies and

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 78
chiplets, test and inspect the devices, select suppliers, engage should guide engineering teams along a path that promotes
quality and regulatory resources, train specialists, educate the highest level of security for patients and protects the
healthcare professionals, and monitor patients. That level of business of the manufacturer.
understanding will promote improved practices associated
with vendor selection and management, remote access, use of
employee devices, and even the practices/methods associated 3.7. Challenges and Future
with a device’s decommissioning.
Needs
It is also important to consider the packaging and tracking Table 3.2 provides on overview of the current state of security
methods/technology used to manage devices and technology technologies relevant to microelectronics and advanced
in the field. As manufacturers evolve from using passive packaging. Outlined are the near-term threats and mitigations,
tracking technology such as 1D, 2D, and human readable trace with an emphasis on areas requiring research to mitigate long-
elements, they must examine the risks associated with using term and upcoming threats.
labels and tags that support multiple tracking methods—even
an innocent-looking label on a device package. For instance, Finally, educational resources are still lacking in the areas of
a 30-micron thick label is now capable of being interrogated advanced packaging and security measures, including the latest
by devices that can visually decode passive symbology and inspection methods, characterization, physical attack modalities,
communicate synchronously using RFID and Bluetooth and their associated countermeasure strategies. To ensure
methods. Consider the risk of incorrectly pairing an insulin a continuous pipeline of future workforce in this area, the
vial with a patient’s pump or trying to avoid loss of revenue community will need to develop training materials and resources
because devices cannot be accounted for. aligned with the need of the future generation (Gen Z), as
well as various groups of K-12, undergraduate, and graduate
There are numerous ways that a medical device’s security, and students using virtual-reality-based modules and gamification*.
consequently its safety, can be compromised. These insights

Table 3.2: Security technologies

Near-term threats and Long-term threats and

Technologies Current
mitigations mitigations
Safety mechanisms Bespoke circuits enforcing Hardware-based safety rails;
safety, position monitoring, standardization would be
and hardware interlocks beneficial
Tamper-resistant and tamper- Tamper-evident seals with Packaging with sensors to Tamper-proof packages
proof packaging visible evidence of tampering; disable chip functionality using nano-mechanical
tamper-proofing that when opened systems as vibration sensors;
destroys chip when accessed semiconductor sensors to
detect light or temperature
changes
Anti-reverse engineering and Security mechanisms such No security measures Logic locking, obfuscation,
counterfeiting as logic locking, obfuscation, available to protect against and camouflaging that are
and camouflaging adversaries utilizing hardware considered secure and stable
reconfigurations in the must be analyzed in the
package new advanced packaging
model; taking advantage
of hybrid methods to use
both materials and design
capabilities to secure package
is a promising approach

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 79
 Table 3.2: Security technologies

Near-term threats and Long-term threats and

Technologies Current
mitigations mitigations
EDA tools for 3D Security tools for HI and Secure placement of chiplets,
covert channels; optimizes minimizing side-channels in
power, area, security 3D stacks
Resource-constrained Crypto NIST standard ASCON has Post-quantum attacks; higher Better algorithms (size,
been chosen bits needed capabilities) needed
Post-quantum Cryptography NIST standardization process Fully Homomorphic Development of non-lattice-
(PQC) completing Encryption (FHE); Functional based key encapsulation
Encryption and digital signature PQC
algorithms to deal with
potential security issues with
lattice-based algorithms
Chiplet root-of-trust Systems for single chiplet Adapting standards such as a Architectural solutions/
(including monitoring chiplet root-of-trust to multi-chiplet standards for easy integration
security) systems of chiplets into a secure
system and its validation
Chiplet link security Ongoing work in UCIe based Enhanced link security based New standards could be
on PCIe; can offer Compute on CXL or other upcoming developed for inter-chiplet
Express Link (CXL) security standards communication security
Supply chain security Process management; Progressing towards Mature standards to support
technology available for using manufacturing standards to supply chain security
PUF to track parts support supply chain security
MEMS sensors Rudimentary MEMS sensor MEMS sensors can benefit Additional intelligence and
self-tests in place; no industry from mitigation techniques connectivity will be available
standard for anti-tampering of HI; transducer-specific in sensors and needs to be
mitigation needs to be addressed
developed as industry
standard

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Contributors
Richard Chow (Intel) – Chair Amitabh Das (AMD) Christian Peters (Bosch)

Farimah Farahmandi (University of Kassem Fawaz (University of Wisconsin) Umit Sami (Memcus)
Florida) – Vice Chair
Kanad Ghose (SUNY Binghamton) Naomi Schwartz (MedCrypt)
Sohrab Aftabjahani (Intel)
Brett Goldsmith (Paragraf) Mark Tehranipoor (University of Florida)
Navid Asadi (University of Florida)
Ahmed Hussein (University of Guelph) Eric Van Hensbergen (Arm)
Asif Bhatti (America’s Frontier Fund)
Farinaz Koushanfar (UCSD) Axel Wirth (MedCrypt)
Krishnendu Chakrabarty (Arizona State
University) Prabhat Mishra (University of Florida) Tao Zhang (University of Florida)

Subhasish Mitra (Stanford University)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 80
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Lipp, Moritz, et al. “Meltdown: Reading kernel memory from user space.” Communications of the ACM63.6 (2020): 46-56.
13
 im, Yoongu, et al. “Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.” ACM SIGARCH
K
Computer Architecture News 42.3 (2014): 361-372.
14
 edTech Dive, “EU Health Commissioner proposes MDR delay to prevent medical device shortages”, Dec. 12, 2022, https://www.medtechdive.
M
com/news/eu-mdr-delay-device-shortage/638491/
15
 005’s Cybersecurity for Networked Medical Devices Containing Off-the-Shelf (OTS) Software, 2014’s Final Guidance: Content of Premarket
2
Submissions for Management of Cybersecurity in Medical Devices, and 2016’s Final Guidance: Postmarket Management of Cybersecurity in
Medical Devices, and the most recent (2022) Draft Guidance: Cybersecurity in Medical Devices: Quality System Considerations and Content of
Premarket Submissions
16
 ttps://www.fda.gov/regulatory-information/search-fda-guidance-documents/content-premarket-submissions-management-cybersecurity-
h
medical-devices
17
 DA, “Content of Premarket Submissions for Management of Cybersecurity in Medical Devices”, Draft Guidance for Industry and Food and
F
Drug Administration Staff, October 18, 2018. (no longer available online).
18
https://www.fda.gov/regulatory-information/search-fda-guidance-documents/cybersecurity-medical-devices-quality-system-considerations-
and-content-premarket-submissions
19
 ttps://www.fda.gov/regulatory-information/search-fda-guidance-documents/cybersecurity-medical-devices-refuse-accept-policy-cyber-
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devices-and-related-systems-under-section
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https://www.apple.com/newsroom/2022/03/apple-unveils-m1-ultra-the-worlds-most-powerful-chip-for-a-personal-computer/

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 81
 Modified on 18 Mar 2024
Chapter 4 See the update log for details

Digital Processing
Scope Major Impediments and
The roadmap for digital processing examines the current Challenges
and emerging drivers for digital processing and the required
Several impediments/challenges have to be addressed in
innovations in the processing paradigms. These requirements
realizing heterogeneously integrated digital processing
dictate the necessary technologies and architectures for
systems, including the need to:
digital processing, memory, support chiplets, interconnection,
and the overall system architecture. In turn, the chiplet and • Address the cost of data movement in terms of
interconnect architectures define the requirements for the performance (latency and bandwidth), end-to-end energy
device, interconnects, in addition to the chemicals and chemical expended per bit transported as the volume and rate of
processing technologies. Chemical processing requires a deep data increase exponentially.
knowledge of the physical and chemical reaction mechanisms
• Limit the overall energy consumption at the system level and
to enable integration into the product. The digital processing
to dramatically improve the energy efficiency of the digital
chapter also specifies ancillary requirements and solutions that
processing system as a whole to deal with the data deluge
are needed for system-level integration of digital processing
and the necessary processing of such data.
systems, as well as related system-level considerations for
overall security, power conversion/delivery, system reliability, • Address the scaling limitations inherent in the architectures
and run-time management needs, which are discussed in other in current use and for Systems-in-a-Package (SiPs) imposed
chapters of the roadmap. Figure 4.1 depicts the overall theme by total power, power distribution, interposers, and
of this chapter. interconnections.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 82
• Improve fundamental understanding of physical and chemical challenges, implementations, and technology needs. Section
processes for future device manufacturing, including advanced 4.3 translates the system-level architectural needs to device,
patterning, atomic-scale thin film deposition, etching, area- interconnections, materials and chemical processing challenges,
selective deposition and other selective materials processing. as well as promising solutions. The roadmaps for the digital
processing paradigms, system-level architecture, and devices/
• Address the increasing need for security and reliability of
materials for digital processing are shown in Table 4.1.
the heterogeneously integrated digital processing systems,
including the need to monitor and interpret all required
information to ensure both secure and reliable operations.
4.1 Applications, Digital
• Address and improve end-to-end sustainability, encompassing
pre-design, design, manufacturing, use, and eventual disposal/
Processing Paradigms, and
recycling. HW-SW Co-Design
• Provide high-level design tools that permit function This section identifies the most demanding and prominent
disaggregation into a multi-chiplet architecture, optimizing application and market-driven design requirements. Some
simultaneously across several parameters; optimizations of the application requirements also point to shortcomings
in the large design space that needs to be explored poses in current data processing architectures, so this section also
challenges that require ML-based solutions. covers the evolution in digital processing paradigms. Lastly
HW-SW co-design highlights the need for a coordinated effort
Section 4.1 discusses how application needs drive the data
at different levels of system design for addressing power and
processing paradigms, while Section 4.2 discusses the resulting
performance requirements.
architectural implications at the system level, the related

Figure 4.1: Overall theme of this chapter

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 83
 Table 4.1: Roadmap for digital HI systems and devices.

Period Current 5 years 10 years

Digitial Processing Paradigm Roadmap: Development and Maturation Periods

Compute-centric SiPs Scaleup takes advantage of chiplets with Systems scaleup takes increasing High core-counts exploited with mature
(CCS) interconnections in interposer; HBM advantage of logic-to-logic stacking and programming library standards; CCS
integration remains limited; traditional new memory technologies; IoT products continues use for its universality;
accelerators use continues see increasing use of accelerators, sensors, increasing use of security and reliability
and communication chiplets in CCS features
Memory-centric Permeates gradually into mainstream; Analog accelerators deployment Sees wider deployment in IoT products
architectures, SiPs analog accelerators mature; initial IoT increases: new memory technologies
for AI, and ML deployment in image processing see use in in-memory computing
applications
Programming models and software evolve; unified virtual memory (UVM) standards Software and UVM “standards” in place
evolve
Neuromorphic Remains in formative stage; new memory technologies incorporated into Human brain simulation becomes more
computing neuromorphic systems complete
Quantum annealing & Quantum systems continue to remain diverse; deployment increases but remains confined to a few sectors; cybersecurity
quantum computing applications increase; smaller form factors remain elusive

Heterogeneous Integration Roadmap for SiP Architectures for Digital Processing

Integrated chiplet High-end: Multi-core chiplets, GPU, High/Medium-end: Analog AI Serious challengers to DRAM memory
types & count HBM, small NVM, co-packaged ML chiplets in production SiPs; emerge; co-packed photonics chiplets
photonics at high end, wider use of neuromorphic and PIM chiplets appear; for IO; NVM memory chiplets see wide
interconnection standards, 3D SiPs with use of NVM in memory hierarchy; UVM use in memory hierarchies; analog ML
2 or 3 layers + HBM2/HBM3, and SRAM standards emerge; increasing use of accelerators permeate along with other
stacks; liquid cooling use with package 3D design; package TDPs near 1KW specialized chiplets; chiplet counts
TDPs to 500+ W. Medium-end: Like mark. Embedded/IoT: Scale-up with continue to increase but stabilize
above but with GDDR6+ DRAM, low-end specialized chiplets; 5G/6G chiplets for
GPUs. Embedded/IoT: Larger NVM, IoTs; data consumption at edge goes
SRAM, with RF chiplets; chiplet count/ beyond automotive/specialized markets;
package: 4 to 10 chiplet count: 10 to 30
Accelerator chiplets GPU (full and variable precision); early Analog NN accelerators with NVM and Neuromorphic accelerators or SiPs;
and specialized SiPs memory-centric chiplets; early analog analog memory technologies with low- smaller form factor, general quantum
accelerators — low lifetime built with power ADCs; tight photonics integration computing chips integrating qubits,
memristors; SiPs supporting quantum for quantum and mature accelerators gates, and measurement and control logic
annealing and quantum computing appear for data-centric computing in use
Memory technologies, HBMs, stacked SRAM caches; cache NVRAMs across memory hierarchy New memory chiplet competing
memory hierarchy, chiplet on logic; conventional and with non-traditional uses; open UVM with DRAMs; energy-efficient NVMs
and memory extended hierarchy with large L4 cache; architectures and standards; advanced competing with SRAM in speed and
coherence in SiPs standard coherence protocols, some HBM generations; new memory comparable to DRAM densities; multi-
based on CXL, proprietary UVMs in use technologies become affordable and granular UVMs appear
reliable
SiP interconnections Silicon bridges with ~1000 to 2000 Silicon bridges with up to 4000 lines; Silicon bridges with up to 8000 wires;
lines; limited face-to-face bonded 3D via and bump pitch down to 5 to 10um PAM8 encoding appears at high-end;
connections; interposer with 2 to 3 in large volume production 3D SiPs; nano-scale face-to-face bonding at high-
metal layers; co-packed photonics IO interposers with up to 5 layers; PAM 4 end; up to 7 layers in interposer; dense
with 2 to 8 wavelength WDM links encoding use increases; PAM8 encoding WDM and package-internal photonics
at high end; back-end vias for power appears at high-end; small form factor chiplets for IO in production for high-
delivery; PAM4 encoding at high-end photonics IO in production; dense WDM end
in wider use for SiP IO

Transistor density*
2.00E+10 4.02E+10 8.09E+10
(count/cm2)
Transistor power* For digital processing applications, the average (across the chip) transistor power density is projected to stay flat at ~50 W/cm2
density (W/cm2) for server chips and 1 W/cm2 for mobile chips

*Calculations are from Synopsys TCAD using 3nm tech as the

baseline in 2023. For details see Chapter 4 Supplemental Materials

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 84
 Table 4.2: System requirements dictated by current and emerging applications.

Application Performance Energy Memory/ Scalability Co-design Reliability Packaging Security

Efficiency Storage
AI Critical Major Energy Critical Important Critical Important 2.5D / 3D Important
Consumer for energy
efficiency
Communication Important Critical Important Critical Critical

Edge Compute Important Critical Small Important / Important Critical Important

footprint Critical
HPC Critical Important Critical Critical Critical for Important 2.5D / 3D Important
Perf & power
Automotive Important Important Important Critical Critical

Health Critical Small Important Special Important

footprint Materials
EDA Critical Important Critical Critical Important Important Important

Defense Critical Important Important Important Critical Critical

Harsh Important Critical Special

Environment Materials
Quantum Important Critical Critical Important Important Important
Computing

4.1.1 Applications 4.1.2 Digital Processing Paradigms

As detailed in Chapter 1, a wide range of applications will drive When the CPU-based processing platforms are unable to meet
the semiconductor roadmap with diverse set of requirements compute/energy/storage efficiency requirements for specific
for performance, energy efficiency, security, reliability, applications, the typical response is to go from standard
scalability, storage, and interconnects. For example, while compute to custom compute solutions, either as custom
HPC and AI emphasize large-scale compute and storage, processors or hardware accelerators.
IoT applications focus on resource-constrained operations
in terms of energy, compute, and storage. Table 4.2 above To improve the energy efficiency and performance of the
captures the critical and important requirements for these compute for these applications, there is a need to explore
diverse range of applications. alternative compute paradigms beyond the prevalent
compute-centric paradigm.
It is to be noted that AI applications encompass the important
subclass of generative AI applications where very large data The following compute paradigms are expected to grow and
sets drive the learning step to enable synthetic data to be influence specific types of applications.
generated based on patterns learned from the training data
• Compute-centric: Most current compute architectures are
set. Specifically, generative AI applications exacerbate the need
built focusing on computation units, the memory hierarchy,
for storage capacity, energy used, and processing capabilities.
and interconnects designed to support the compute
fabric. Efficiency in application processing is addressed
This chapter focuses on digital technologies addressing
by exploiting characteristics of compute in terms of
some of the core requirements for these applications from
instructions (CPU, DSP, ASIP), instruction-level parallelism
system architectures to devices, including digital processing
(scalar, super-scalar, VLIW), and task-level parallelism (multi-
paradigms, HW-SW co-design, energy-efficient and high-
cores, heterogenous architectures).
performance compute and memory architectures, and
device and material process technologies. Some of the other • Data-driven architectures: A large number of applications
application requirements like reliability, packaging, and involve massive amounts of data processing which is
security are covered in other chapters.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 85
 beginning to move focus from compute to memory, as parallel processor (MPP) architectures three decades
evident by significant amounts of energy spent on memory ago, HPC shifted to a strategy of leveraging commercial
and interconnect. New memory devices and architectures off-the-shelf (COTS) computing technologies, e.g., X86
are evolving for overall efficiency in performance and microprocessors and commodity DRAM memories. This
energy for these applications. marked the end of custom-designed Cray Vector HPC
systems1. With the end of Dennard scaling and slowing of
• Memory-centric: As the relative cost (performance and
Moore’s law, the MPP strategy still holds, but the focus
power) of compute versus memory for data-intensive
shifted nearly 20 years ago to the use of compute nodes
applications continue to lean toward memory (called
with COTS CPUs augmented with graphics accelerators that
“memory wall”), there is a growing trend toward
perform the majority of double-precision floating-point
architectures that place compute resources closer to the
operations. The Exascale Computing Project2 established
data as compute-in-memory and compute-near-memory.
architecture R&D projects with processor and system
• Stochastic computing: The prevailing compute paradigms companies to support the co-design collaborations
process and store information as numbers with precision (8, that led to new hardware and software capabilities for
32, 64 bits). Processing of numeric data has its associated heterogeneous CPU-GPU HPC, as well as extensions
arithmetic computation cost in performance and energy. In to support scientific machine learning. As described in
a large number of applications that do not impose stringent Section 4.2.2, performance is the primary goal for the HPC
numeric accuracy requirements, stochastic computing that community. While the 2.8x increase in power consumption
stores information as probabilistic data and associated for the performance increase from TeraFlop and PetaFlop
simplified compute can provide significant energy- was acceptable, and the recent 9.0x increase in power
efficiency improvements. consumption for the latest performance increase from
PetaFlop and ExaFlop is accepted, it is not sustainable.
• Cognitive computing: Similar to stochastic computing,
information can also be stored and processed with • Future progress in HPC and computing performance will
large random vectors in place of numeric data. This is require a holistic co-design approach to achieve dramatic
exploited by hyper-dimensional computing, which offers a increases in energy-efficient computing performance on real
variety of advantages for AI systems in terms of network workloads. The shift towards real application performance
architectures, energy efficiency for learning, as well measurement provides a motivation and driver for
as inference and noise/error tolerance. Symbolic data heterogeneous processors that integrate domain-specialized
representation with large random vectors also enables accelerators with COTS processors, advanced memory, and
multiple layers of cognitive computing. network interfaces3–7. The confluence of these HPC drivers
aligns with the CHIPS and Science Act goals to create an
• Neuromorphic computing: This is the brain-inspired compute
infrastructure and ecosystem for hardware prototyping,
paradigm including integrated memory and compute
advanced packaging of chiplets and 3D heterogeneous
architecture with neurons and synapses. Energy efficiency is
integration. The development of a microelectronics
also improved through event-driven/asynchronous compute
commons to democratize access to ASIC design tools and
and communication, as in spiking-neural networks.
the emerging chiplet integration standards both support
• Quantum annealing and quantum computing: While the development of a growing chiplet marketplace. These
traditional computing stores information as bits and continuing demands and market trends will necessitate a
computes with arithmetic, quantum computing stores broader and deeper ability to concurrently consider the system
information in multi-dimensional states (qubits), software stack and hardware. This is deep co-design in which
and quantum processing exploits superposition and algorithms and architectures are designed together to develop
interference of the qubits to provide exponential growth in an optimal solution.
compute capabilities for large complex problems.
• Over the next decade, the energy-efficient performance
drivers for HPC will align with common needs for many
4.1.3 HW-SW Codesign
computing areas and require an ability to customize
• This description of hardware-software co-design focuses on processors, memory technologies, accelerators, and discrete
the high-performance computing (HPC) use case because functional units into heterogeneous computing designs5,6.
the HPC community is open to investments to develop The advent of advanced packaging and 3D integration
both hardware and software. Since the advent of massively with chiplet technology standards, e.g., Universal Chiplet

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 86
 Interconnect Express (UCIe), will support their integration • Coarse-grained reconfigurable architectures (CGRAs) and
into heterogeneous processors. Tools to integrate these the ability to dynamically compose discrete components
tailored chiplet technologies will be critical components in disaggregated architectures will further expand the
to this capability and will span from circuit design to floor possible co-design space. This will necessitate tooling
planning and all the way up to full-system simulation. These that is capable of optimization at application runtime, and
hardware design tools will need to be applied in tandem which incorporates optimization criteria across concurrently
with profiling tools to better understand applications and running workloads. While some cloud computing
their algorithms. This will enable rapid exploration and environments are currently faced with aspects of this
assessment of hardware technology designs and changes in complexity, the next decade will see reconfigurability along
applications to achieve an optimized solution across complex a much larger set of dimensions and application workloads.
tradeoffs (performance, power efficiency, ease of porting,
• Research and development of technologies that enable
design and fabrication cost, and total cost of ownership). AI
this deeper level of co-design holds the key to continued
will undoubtedly play a role in this space, as witnessed by
exponential gains in performance and power efficiency
multiple academic and industry initiatives that have already
for our nation’s strategic computing workloads. In April
incorporated AI into their design and optimization cycles.
2023, the National Academies issued a report that outlines
• Alongside these tools for reasoning about the integrated the importance of HPC, technology disruptions, market
design space, there is the need to efficiently shape ecosystem disruptions, and the need to rethink innovations
future technologies from software to integrated circuits. in hardware and architecture, software, system acquisition,
Heterogeneous computing system software will necessitate and the role of cloud computing7.
continued advancements in software frameworks, compiler
technologies, runtime, and operating systems5. From the
perspective of hardware technologies, this will necessitate 4.2 System-level Architectures
higher productivity tools for ASIC design, SoC design,
The SRC Decadal Plan8 notes that data volume and data
memory subsystem design, and the ability for compositions
movement costs are dominant in processing systems. At the
of multiple heterogeneous chiplets to interoperate.
chip scale, the fraction of the total chiplet energy spent in the
Individual components manufactured with different digital
interconnections has grown tremendously at advanced nodes, as
process technologies will need to be seamlessly integrated at
seen in Figure 4.2. Systems-in-a-package have to address the cost
low cost, low power, and high yield, necessitating significant
advances in heterogeneous packaging technologies.

Figure 4.2: Chiplet-scale power trend18

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 87
of data movement at all scales, both in terms of absolute power rates, the overall trend in system power will exceed the
and energy expended per bit in the data transport process. total energy generated globally. This grand challenge for
improving energy efficiency has to be addressed using a
The system-scale architectural techniques addressed in variety of solutions, including the following:
this chapter that appear promising in mitigating the data
• Innovations in memory technologies including non-volatile
movement costs are summarized below:
memory devices, analog memory devices, and others.
• Processing near memory.
• Making general-purpose multicore architectures more
• Processing in memory, which encompasses development of energy efficient.
suitable memory devices with embedded logic.
• Replacing or augmenting general-purpose processing
• Processing at the interconnection interface, within the solutions with more energy-efficient specialized function
interconnection (for example, within on-chip routers as data is accelerators.
moved).
• Preferred processing engines for AI/ML shifting from
• 3D chiplet stacking architectures, which dramatically reduce conventional digital ML accelerators like GPU and GPUs to
the reach of inter-chiplet interconnections. alternatives that are significantly more energy-efficient, in
particular analog AI/ML accelerators.
• Architectural solutions that avoid system-scale data
movements, such as in broadcasting. • Neuromorphic computing to provide extreme performance
per unit energy, exceeding the capabilities of conventional
• Since clock signals are distributed globally, the associated
transistor-based s olutions by several orders of magnitude.
interconnection power (using H-trees or similar
interconnection topologies) needs to be addressed. • System architecture innovations that reduce the cost of data
movement.
At the level of the interconnections themselves, several
solutions, enumerated below, offer the potential of reducing 4.2.1. Memory Technologies
interconnection energy.
Goals/Needs: Standalone memory materials and
• Use of redistribution layers (RDLs) offered in many chiplet devices
integration technologies, such as CoWoS.
Methods are needed to extend current incumbent, standalone
• Use of clock-forwarded links for short reaches in 2D and 3D memory and DRAM and NAND flash technologies, as well as
configurations, which avoid the need for area- and energy- enabling “emerging” memory and invention/discovery of new/
hogging PLLs and DLLs for clock/data recovery. novel memory possibilities.

• Use of advanced symbol encoding going beyond PAM 4, the

Roadblocks/Challenges
current state-of-the-art.
Further DRAM scaling is hampered by the large relative area
• Use of energy-managed links, supporting the analog of DVFS
needed for the capacitor, so 3D device stacking through
and other techniques.
layering (homogenous integration), similar to what has
• Use of photonics for package-level IO. In the longer term, been done for 3D NAND, is attractive for continued density
this could be a solution for interposer-scale connections, but improvement. A major hurdle for 3D homogeneous DRAM
significant developments are needed for non-IO deployment. is that it requires BEOL-compatible select devices with
appropriate drive characteristics and very low leakage, which
Certainly, the evolution of interconnection standards to ease are yet to be realized. Continued layer stacking in 3D NAND
chiplet integration and achieve the full potential of HI is a requires etch technology advances and thinner materials
necessity. Standards are evolving (BoW and other ODSA efforts, (toward 2D), especially for the channel. For both DRAM and
UCIe, etc.), and others are likely to evolve or be built on the NAND, new packaging architectural schemes and supporting
dominant standards, including standards for power distribution, technology for chip stacking (3D HI) beyond current HBM
reliability monitoring, security monitoring, and test. methods are needed.

The SRC Decadal Plan showed that, if the current trend of Emerging memory is still “emerging,” with nothing currently
chip/system designs continued with projected deployment available with a combined set of properties necessary to

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 88
supplant the mainstream, incumbent technologies of DRAM 3D deposition technique (ALD) compatible with BEOL
and NAND Flash in large-scale, stand-alone implementations. material processing window; very high k through the use
Emerging memories must overcome their known, respective of ferroelectrics.
shortcomings to rival these incumbents in cost, scaling, reliability,
• 3D DRAM: Stacking requires BEOL compatible select device
variability, repeatability, cyclability, and other metrics. Much has
with high drive current (>10 MA/cm2) at ~+/-2V, and extremely
been done to address the deficiencies of emerging memories
low leakage (<<10-15 A). Toward 2D, as well.
(e.g., the various flavors of ReRAM, PCRAM MRAM, and
FERAM), but a collective win has not been forthcoming. Without • Enabling 3D heterogeneous packaging architectures and
such overall device competitiveness, these technologies will methodologies with supporting technologies for DRAM and
be relegated to smaller-scale, niche implementations, such as NAND, and any emerging memory applications of interest.
MRAM as a non-volatile SRAM replacement and FERAM as a
relatively fast and low voltage, non-volatile memory. Emerging memory

• ReRAM: Toward deterministic control of resistance states for

For the whole memory space, revolutionary new application
low device variability and cycling repeatability, with minimal
platforms yet to be established or even envisioned, like new
drift and high stability.
AI architectures, novel consumer devices, or even DRAM and/
or NAND in a new space, could enable emerging memories. • PCRAM: Drift and atomic segregation-resistant material with
So, new technology opportunities and overlaps should lower drive-current requirement.
continue receiving attention. Unforeseen opportunities in the
• MRAM: MTJ device or analog with 10-100x lower critical
standalone memory space may unfold through the evolution
current or voltage-switching and 10-100x higher resistance
of new architectures that go toward mitigating the power-
ratio.
sapping, compute-to-memory interconnect bottleneck (the
so-called “memory wall”) by enabling widespread near- and • FERAM (incl FeFET & FTJ): High and uniform remnant
in-memory compute. polarization at scale in X-Y and Z with high retention and
resistance to imprint and fatigue.
Possible solutions
New memory
Material and device solutions for any memory and/or select
device must be approached with an overall knowledge of the • Analog-like: Deterministic control of a multitude memory
many target performance metrics and integration challenges states (>10) having near linear response, large dynamic range,
required for success, including those that enable the device low variability, and high cycling and reliability at scale.
as a possible replacement or supplement to current memory.
• Novel concept(s) with rival set(s) of inherent properties.
Materials and device developments must go in lockstep with
modeling (first principles, transport, multi-physics, etc.) to guide
4.2.2. Conventional Digital Processing
development and implementation. New architectures and
technology space that help eliminate current roadmap issues Challenges and needs
may open new opportunities for established and/or emerging
General purpose computing ICs will continue to remain a
memory technologies.
workhorse. These systems have been optimized and used in
applications ranging from HPC to embedded/IoT applications.
The needs for scaling-up the performance and energy efficiency
The challenges to be addressed are:
of incumbent memory technologies (3D NAND memory and 3D
DRAM) and the needs for the adoption of emergent memory • Low yield and high cost of single-chip implementation of high
technologies (ReRAM, PCRAM, MRAM and FERAM (including core counts, effectively limiting upscaling.
FeFET and FTJ memory) are listed below. Desirable properties
• Upscaling being impeded by the need to maintain cache
and trends of novel memory technologies, particularly analog-
coherency in high core-count systems.
like memory devices and other memory are also listed.
• Poor energy efficiency resulting from core idling or low-
Incumbent mainstream memory utilization cores when workload is offloaded to accelerators.

• 3D NAND: Scaling requires thinner channel material (2D) • Increased pressure on the conventional memory hierarchy and
with reasonably high mobility (>20 cm /Vs) and concurrent
2
package IO.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 89
• The need to checkpoint the computation state of long- will permit significant connectivity improvements through
running applications (typical in the HPC domain). parallelism in the network.

• Inefficiencies stemming from the lack of unified virtual

The memory hierarchy limitations can be addressed in a
memory due to memory copying, coherence activities and
variety of ways, including via the use of additional cache levels
virtual memory exception handling.
implemented in separate chiplets within a common package;
stacked SRAM lower-level caches; incorporation of new
In general, like any other multi-chiplet realization of a
memory technologies; use of co-resident HBM chiplets within
system-in-a-package, a conventional digital processing
a common package; and using memory-centric computing
system will initially rely on 2.5D integration, with dense, low-
paradigms and accelerators.
latency interconnections within the package, and dedicated
chiplet-to-chiplet connections. Limited forms of 3D
An obvious scaleup strategy for general-purpose computing
integration will emerge in production quantities in the near
system will be to integrate multi-core processor chiplets,
future. The development of chiplet interconnection standards
accelerator and other chiplets along, IO chiplets and memory
(such as UCIe, BoW of the ODSA set of standards) and
chiplets, but this requires shared memory coherence mechanisms
chiplet scale cache coherency standards, such as CXL (which
that operate at the scale of the system-in-a-package. Techniques
essentially implements the well-known MESI protocol), are
for cache coherence scaling to hundreds of large caches with
helpful in paving the way for multi-chiplet implementations of
increasing distance between them have to be used, leading
conventional processing systems that incorporate additional
to the concept of dynamically partitionable NUMA domains.
chiplets for acceleration, memory, and IO.
Checkpointing solutions will rely on non-volatile memory
technologies, both inside and outside the package. Promising
Possible solutions
non-volatile memory technologies for these applications were
Solving for system upscaling challenges may include multi- discussed earlier in this chapter.
chiplet implementation of large core counts, which will
become a standard to address low yield and high cost of Package IO limitations can be circumvented by integrating
single-chip implementations. Heterogeneous multicore chiplets representing system components that communicate
chiplets or chiplets with Heterogeneous cores (called the often or communicate with high data rates. Co-packaged
“big-little” configuration) offer a way to mitigate the power photonics can also circumvent the package IO bottleneck, but
wasted at low utilization levels; the system governor and the deployment at scale with low cost will remain a challenge.
OS scheduler can make effective use of the Heterogeneous The development of photonics transceivers that are immune
cores. Additionally, idling, or low-utilization of cores need to to larger temperature excursions and have low overall cost
be avoided through scheduling techniques to improve overall is critical for widescale deployments. The lack of a unified
energy efficiency when workload is offloaded to accelerator virtual memory mechanism needs to be addressed via
chiplets. Appropriate software and OS infrastructures the development of standards that permit the seamless
need to be developed for this. In general, the improved integration of multicore and accelerator chiplets with a
energy efficiency of accelerator chiplets will result in common view of the shared virtual memory.
deeper penetration of different acceleration technologies
in general-purpose computing solutions at parts of the 4.2.3. Data Processing in Memory
product spectrum.
Goals/Needs

Upscaling is also enabled via in-network acceleration for Applications such as Deep Neural Networks (DNN)9 and
multicast, collectives, barriers, and other synchronization Homomorphic Encryption (HE)10 require frequent data
features to mitigate the increasing core-to-core movement among different levels of the memory hierarchy.
communication latency. Adaptive routing will reduce The limited bandwidth and high data movement cost in terms
congestion and unlock the available bisection bandwidth of of delay and energy degenerate the system performance and
the interconnections. Interconnection bottlenecks can be increase the energy consumption of the processing. However,
alleviated in many ways in SiPs. These include the use of wide one of the operands of such operations is stationary, e.g., the
bridges in 2.5 D configurations, stacking of low-power cores neural network weights in the DNN. Processing-in-memory
and/or IO processors, or SRAM caches on high-power chiplet (PIM) is a promising solution for accelerating such data-
cores. Finally, having multiple metal layers within the interposer intensive workloads as it enables in-situ computation directly

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 90
in the memory component. With processing capability at the memory hierarchy is also enabled by this, but appropriate
cache, main memory, and/or storage devices, system-level APIs need to be provided to permit workload scheduling, data
performance and energy-efficiency improvements are enabled staging, and other needs.
for applications from data-center scale to edge devices.
Algorithm-hardware co-design is needed to architect and exploit
PIM approaches must be extended to support applications the full potential of PIM-based systems. Trace-driven, high-
such as transaction processing, database, and search level simulation tools are needed to identify the hardware
applications, as well as to accelerate bit-level operations and primitives to establish a basis for designing the associated
accelerate specific bioinformatics applications. software stack, libraries, and run-time system. Without a
software base, large-scale deployment is necessary.
Roadblocks/Challenges
4.2.4 Analog AI Accelerators
PIM chiplet realizations for SiPs face several challenges,
including: Goals/Needs

• The architecture design and computational precision of The dominance of AI/ML applications, which is expected to
PIM accelerators often rely on overidealized device/circuit continue in the coming five to 10 years, will see deployment at
parameters, which is difficult to achieve in the actual multiple scales, from edge devices and mobile platforms (such
material manufacturing process . 11
as autonomous vehicles) to large data centers. A significant
set of these applications have relied on neural network variants
• Due to the limited internal bus bandwidth, the workload
(CNNs, DNNs etc.), and current product offerings testify to
requiring flexible data access patterns (e.g., non-local
the wide variety of existing and future needs. In any of these
access or collective operations) still suffers from the
systems, timely response and high throughput are critical. The
data-movement bottleneck12.
data sets used for training the AI/ML accelerators have also
• Due to the limited on-chip memory capacity with fast- grown significantly. So, it is imperative to dramatically improve
growing size of the models, the performance of a PIM- the energy efficiency of AI/ML acceleration subsystems to scale
based accelerator is degraded by the data movement up with the data sets and application size.
incurred due to data replacement of the PIM12.
Roadblocks/Challenges
• There is a lack of support in the software stack. Most
compilers/libraries are not aware of the special dataflow Conventional NN-based accelerators are implemented with
in the PIM accelerator or between the PIM accelerator and digital logic, relying on an array of multiply-and-accumulate
the host. Hence, they cannot fully utilize the full potential (MAC) logic. Improved device technologies, the use of variable
of PIM design13. precision support, etc., have been traditionally used to scale
up the capacities and improve the energy efficiency of these
• Existing PIM designs lack flexibility for the implementation
accelerators. Recent years have also seen the emergence of
of an entire application. This requires memory sharing
analog multiplier-based MACs that have relied on memristors,
or fine-grained synchronization with the processor, which
PCM and other technologies, which are particularly suited
could lead to performance degradation compared with that
for low-power applications where some lack of precision
demonstrated in the isolated evaluation13.
can be tolerated. Several challenges remain in scaling up
• There is no complete solution to integrate PIM into the accelerators, such as addressing the data transport
the existing system. No solution has been verified overhead, significantly reducing the power dissipation
to be compatible with cache coherency, OS memory of the combined systems to avoid thermal challenges
management, existing memory models in programming and focusing on associated reliability issues to permit
languages, etc. .
13
deployment at scale across all application classes.

Possible solutions Possible solutions

Heterogeneous integration allows for specialized PIM • Dense analog AI accelerator chiplet with long lifetimes and
chiplets to be integrated with other chiplets, high-speed extended precision that can support dynamic or configurable
interconnections, and IO chiplets in general for useful precision adjustment. This can improve existing technologies,
deployments . PIM integration at different levels of the
14
which tend to have lower lifetimes. These, in turn, translate

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 91
 to needs for innovations in materials, low-noise and stable deal with the issue of heat dissipation, power delivery, and
analog voltage regulators, low-power and low footprint yield issues. These issues are addressed elsewhere in the
ADCs, etc. Examples of candidate analog AI accelerators roadmap. In the short term and at present, 3D DRAM (such
include the Phase Change Memory (PCM)-based crossbar as HBM), and one-layer of high-power logic in a stack with
array analog neural network accelerators and analog NN low-power chiplets offer a practical solution to memory
accelerators based on other in-memory architectures. scaling and system scaling. Long-term scaling of the system
size requires the overall energy efficiency of the system to
• Alternative MAC designs implemented with new device
scaleup through one or more of the following: innovations in
technologies that are inherently energy efficient (such
system architecture; device and interconnection innovations; and
as carbon nanotube transistors), but reliability/lifetime
dramatic innovations in cooling technologies.
improvement is a necessity.

• SONOS Flash Analog memory or MTJ memory devices Other possible solutions to support SiP scaleup
that have SRAM-like performance and high endurance for
These solutions complement and expand upon the ones
weights, etc.
discussed in Section 4.2.2.

These solutions can be combined in a 3D chiplet stack, which, • QoS-aware routing and congestion management of
in turn, demands high nanobump/microbump densities, new bandwidth-sensitive (e.g., GPUs) vs latency-sensitive (e.g.,
power delivery/conversion strategies, etc. CPUs) PEs.

• Fine-grained (for example, router-level) DVFS support for

4.2.5. Other Aspects of SiP Scaleup
power management.
Scaling system configurations to support further
• Data compression techniques to increase bandwidth and
performance improvements through higher degree of
allow narrower interconnect links.
component integration introduces multiple architectural
and microarchitectural challenges, beyond the physical and • Integrated photonics for chiplet-to-chiplet links.
thermal challenges discussed for far. Many operations that
• Hardware support for sparsity to improve utilization of large
take place across cores involve broadcast and multicast
3D caches and vast compute resources within the package.
operations, which incur increasing completion latency as
core-to-core communication distance increases. Also, despite • Co-designed interconnect topologies tailored to the data
2.5D and 3D integration allowing a significant increase in the movement patterns.
bi-section BW of future on-chip interconnects, congestion
on large-sale Network-on-Chips (NoC) may introduce The architectural studies of such large systems will also
bottlenecks that limit effective BW improvements. NoC require novel simulation techniques that allow simulations at
bottlenecks can be especially severe when data flows from/ multiple levels of abstraction while being able to reason about
to PE across the SiP towards IO and memory controllers in microarchitectural details within a chiplet. This is necessary to
the SiP periphery. Furthermore, NoC area currently accounts permit overall performance, power, and thermal implications of
for 20%-30% of the total SiP area and is responsible for 5%- the whole system to be analyzed across chiplets, different types
10% of the TDP, so further increasing interconnect density to of data processing elements, and chiplet/interposer layers.
address bandwidth issues would require expensive tradeoffs.
In addition to chiplet integration on an interposer in two or
A fundamental limitation in system scaleup is the power three dimensions, larger wafer-scale systems for customized
wall. Since interconnection power in a chiplet forms a applications can also enable system scaleup, but widespread
major component of its power dissipation, heterogeneous deployments of such products are unlikely.
integration offers a way to reduce the overall power by
integrating chiplets inside a package with wide and short 4.2.6. Neuromorphic Computing
interconnections to reduce the IO power that would have
Goals/Needs
otherwise been needed in traversing across package
boundaries. This is true with 2.5D integration with bridge- AI applications predominantly use Deep Neural Network
connected chiplets and particularly with 3D stacked chiplet architectures with very high resource requirements on
architectures. Unfortunately, 3D chiplet integration has to compute, memory, and energy for training and inference. Brain-

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 92
inspired Neuromorphic computing has emerged as a highly effectively get rid of the superpositions). Quantum systems
energy-efficient paradigm offering orders of improvement in use the non-intuitive and unexplained property of quantum
energy efficiency compared to neural networks. Neuromorphic entanglement phenomenon to retain state during readouts.
systems are characterized by integrated compute and memory Quantum entanglement ties the quantum state of two
(neurons and synapses), as well as asynchronous and analog/ physically coupled qubits in a way that makes a state change
digital operations (Spiking Neural Networks, SNNS). The made to one qubit affect the state of the qubit with which
compute-memory integrated architecture allows for scaling it is entangled. During measurements, the entangled qubits
and concurrency, and asynchronous operation enables highly are temporarily decoupled to preserve the state in one qubit
energy-efficient operation. while the other is read. Multiple entangled qubits make up
a single logical qubit, and the number of qubits in a system
Roadblocks/Challenges determines the size of the problem space handled. But scaling
up this number remains a challenge. There are many different
Adoption of new compute paradigms often come with
implementations of qubits and quantum logic gates. Qubit
challenges in software infrastructure. Porting of prevailing
implementations include the following:
AI applications as well as new cognitive applications will
require new abstractions layers and algorithms. The scaling of • Superconducting qubits, where the qubit is a resonant tank
these architectures with analog/mixed-signal processing also with a Josephson junction implementing inductor.
requires error-resilient devices and architectures.
• Cold atom qubits, implemented as supercooled and isolated
(“trapped “) atoms.
Possible solutions
• Trapped ion qubit, similar to cold atoms, but using ions
• New memory and compute devices specifically suited for
instead of atoms.
neuromorphic computing.
• Photonic qubits implemented as isolated photon particle or
• Large-scale networks integrated with chiplets and 3D
a light bean of superimposed “squeezed” photons.
integration.
• Isolated electron qubit trapped and manipulated with the
• Application domain-specific software abstraction layers.
channel of a modified CMOS transistor.
• SNNs used as custom accelerators in a heterogenous system.
• Emergent FinFET-based trapped carrier qubit.

4.2.7. Quantum Annealing and General-purpose

HI enables many critical parts of a quantum system to be
Quantum Computing
implemented within a package, and these will vary from
Quantum systems come in two major flavors, quantum system to system. Some potential integration candidates
annealing systems, which target high-complexity optimizations, include the chiplets that collectively form a scaled-up qubit
and general-purpose quantum computing systems that use ensemble, chiplets used for measurement and excitation,
analog or “digital” quantum gates. Qubits represent the chiplets used for photon beam-forming or photon isolation,
basic unit of information storage in all quantum systems. and chiplets that implement quantum gates in systems that
All the quantum systems rely on the principle of quantum use photonic qubits. In general, a multi-chiplet qubit ensemble
superposition and quantum entanglement. Unlike a traditional requires the use of coherent interconnections, imposing
bit, which could be in either one of two states, a qubit associated challenges. The primary needs for quantum systems
actually is in multiple states with different probabilities include developing new architectures that scale down the
due to quantum superposition. This enables significantly physical size and reduce operation cost. The search for a
more information to be held in a single qubit compared to a truly general-purpose quantum computer remains elusive
traditional bit. Operations on qubits are thus essentially vector and there has been no general convergence, nor is one
operations. So, quantum systems can deal with large problem expected in the medium term. In general, quantum systems
spaces and benefit significantly from the vector operations. are physically bulky, requiring sizeable multi-stage dilution
refrigeration units for maintaining all or some core parts
Qubits are prone to decoherence, where the stored at very low temperatures. A few quantum systems require
information deteriorates due to noise. Storing qubits at very compact tabletop refrigeration units to only cool the qubits,
low temperatures (close to milli Kelvins) delays decoherence. the measurement/excitation circuit and quantum gates. From
Moreover, measurements of qubit states are destructive (and a packaging perspective, quantum system IO will remain a

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 93
challenge and will likely use photonics links and co-packed 4.2.8.2 Security
photonics. Further, packaging solutions need to withstand large
Many of the traditional security threats applicable to
temperature excursions.
packaged single chiplet solutions are multiplied in HI
systems, such as chiplet tampering, chiplet probing for
4.2.8. Crosscutting Considerations
reverse engineering and information leaks (physically
4.2.8.1 Power Conversion and Power Management or using X-rays), and side-channel, covert-channel, and
firmware compromises. This is due to the close proximity
Power distribution for SiPs introduce some unique challenges
of the chiplets, particularly in 3D chiplet stacks, as well as
that include routing considerations for power, line drops
the use of wider and low-latency interconnections, common
(sags) introduced by large currents in high-end systems, the
power converters, and power distribution networks. Security
need for power quality in SiPs that integrate digital and analog
solutions to address side and covert channels in 3D
chiplet, and noise and crosstalk issues in general. 3D chiplet
configurations remain a particular challenge, and the
stacks have unique challenges of their own associated with
development of appropriate methodologies and EDA tools to
power-routing layout constraints, crosstalk, and noise due to
detect and avoid the potential channels at design time for attack-
the closer proximity of chiplets.
surface elimination or reduction will be a de-facto requirement.
A threat unique to HI is the integrity of the interposer itself,
Some potential solutions addressing these challenges that
which can be potentially tampered. Analog accelerators used
exist (and will continue to be used) include:
in digital SiPs present new attack surfaces centered on
• Backside power delivery, which delivers power in a analog-to-digital converters and analog memory components.
distributed fashion directly to the point of use via Finally, another threat comes from run-time firmware
connections at the backside of the chiplet to avoid or application software compromises that can lead to
contention that would otherwise be there between information leakage and denial-of-service attacks.
the signal-routing layers and power-routing layers.
Redistribution layers in the interposer can ease the power Chiplet authentication solutions have been investigated
routing to appropriate points in this solution. and technologies have matured quite a bit. Techniques like
watermarking, logic locking, and design obfuscation are
• Interposer-embedded power converters can reduce the
examples. In general, chiplet and interposer authentications
problems associated with Ohmic (i.e., I2R) losses at high
are necessary solutions to some of the possible attacks on
current and powerline sags in general.
SiPs. This requires using clearinghouse facilities for registration,
• With high-end SiPs, the high current needs and associated securing accesses to authenticate chiplet, firmware, and systems
Ohmic losses can be avoided by using higher voltage supply software at boot or at run-time using a local root-of-trust
to the package and the use of point-of-load (POL) power inside the package. To this end, a complete security-conscious
converter chiplets inside the package to convert the higher ecosystem must be developed. SiPs for high-availability
voltage to chiplet-level voltages in a distributed fashion. systems can also incorporate hardware-centric isolation
mechanisms to isolate bad actors once they are detected
To accommodate package internal converters, it is necessary to (including an entire chiplet that has been compromised),
pursue aggressive converter designs that use advanced magnetics allowing the rest of the SiP to continue providing services
(and the associated materials development) to reduce the overall with graceful performance degradation. Reliable and
height and enable a higher volumetric power conversion density. trustworthy sensors deployed within the chiplet are a must
Accompanying these should be the pursuit of advanced dielectrics for supporting run-time monitoring and graceful degradation.
for small-form-factor capacitors. For 3D systems, solutions need Machine learning techniques are certainly usable in detecting
to be developed for power routing within the 3D stacks. These anomalous behavior across multiple chiplets. In general,
solutions also need to avoid the setup of unintended covert important needs include the technologies for run-time
channels via the power network and shared power converters. monitoring, mechanisms to detect anomalous behavior, and
Prospective solutions include extensions of what is used in mechanisms to handle detected attacks at run-time. All of
the industry today for HBMs and in recent 3D logic chiplet these require significant methodology development, none
stacks, power delivery at the edge, and the use of local power of which are in place today. Security issues and solutions for
regulation within chiplet. Appropriate soft-IP development SiPs are detailed in Chapter 3.
and standards are needed in this respect to specify physical
parameters of the power connections.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 94
4.2.8.3 Reliability Issues management is a must. Finally, the sustainability impact
in the end-of-life disposal phase remains unquantified and
Techniques for assuring chiplet reliability, including device,
significant developments are needed here to eventually make
material and packaging process technologies, have been well-
this phase sustainable. Sustainability considerations, needs,
developed and are not unique to HI, as are soft-errors and
and some potential solutions are detailed in Chapter 2.
their handling techniques. However, chiplet faults and soft
errors can have a cascading effect on the SiP, so system-level
techniques for fault-tolerance need to be developed. These
may include the use of redundancy and facilities for isolating
4.3 Devices, Materials,
failed chiplets, as used in some security solutions alluded to Chemical Processes,
in Section 4.2.8 and in Chapter 3. In SiPs designed for mission-
critical applications, fault-handling techniques need to be
Characterization and Metrology
more aggressive, but these invariably come at a cost that This chapter will discuss logic and memory devices,
needs to be justified. In general, system-scale architectural interconnects, 2D and other new materials, monolithic 3D
solutions have to be used in SiPs for high-assurance systems. integration, advanced patterning, including hyper-NA and
DSA, atomic-scale chemical processes such as ALD and ALE,
HI systems present unique reliability challenges in as well as characterization and metrology techniques.
the integration phase. Redundancy and error-resilient
interconnections are required. At the system scale, faults 4.3.1 Logic and Memory Devices
introduced due to thermally induced mechanical stresses on
4.3.1.1 Logic Devices
the interposer and interconnections pose a threat. Co-design
techniques are critical for early reliability assessment using Goals/Needs
multiphysics-based compact models for thermally induced
The number of connected devices and the amount of digital
stresses during assembly and use. The development of
data transferred during computation continue to grow
reliable assembly and packaging processes and appropriate
exponentially. Simultaneously, the total fraction of available
metrology, as well as materials characterization is also critical
power consumed by electronics is increasing at an exponential
(see Section 4.3.5). Finally, testing during assembly and during
rate. To maintain pace, energy consumed per computation will
the deployed run-time poses a significant challenge.
demand that device area and volume continue to decrease,
and that new materials, device designs, chemical processes,
Reliability issues, their implications, test techniques and
and equipment be realized for novel energy-efficient CMOS
materials, and relevant metrology needs are discussed
logic that is more than 1,000,000 x more energy efficient
elsewhere in this Roadmap.
than current systems15. CMOS is aggressively moving to 3D
stacking to reduce power consumption, increase functionality,
4.2.8.4 Sustainability
and enable further scaling. New strategies must be pursued
HI SiP design flows and design paradigms must evolve to to deliver power and dissipate unwanted heat. Chemical
incorporate sustainability-centered choices. Sustainable processing and new integration schemes are needed to
material process and technology development is critical in provide new pathways to efficient and effective 3D scaling.
providing these choices. The need for deep co-design EDA
tools that embody sustainability consideration remains a high Roadblocks/Challenges
need, becoming important over the coming years. Multi-
Computational power consumption in traditional CMOS logic is
chiplet solutions using smaller, more sustainable, energy-
determined by the supply voltage, the extent of gate current
efficient, and high-yield chiplets help, with smaller chiplet
leakage, off-state leakage, device capacitance (including gate,
size ensuring higher yield and reduced waste. However, the
interconnect, and parasitic capacitance), and clock frequency.
tradeoff between waste introduced in the assembly step
Increasing frequency puts immense demands on reducing
must be compared to the need to assemble the increased
voltage, capacitance, and leakage, which are determined
number of chiplets. Metrics, methodologies, and guidelines
by: device materials (i.e., gate dielectric permittivity and
need to be developed in promoting sustainable design and
thickness, N-P abruptness and isolation, and interconnect
manufacturing. For the operational phase, good system scale
metal conductivity); physical device size and design (i.e., gate-
power management techniques and the use of packaging
to-contact capacitance, cell height, interconnect capacitance,
techniques supporting sustainability-friendly thermal
source/drain overlap, etc.); and device integration and

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 95
 Figure 4.3: Schematic representation of technologies involved in 3D heterogeneous integration.

Figure 4.4: Projection of progress in CMOS transistor density and corresponding switching energy15.

packaging (i.e., 2D planar vs. 3D stacking). New techniques Possible solutions

will be needed to realize high aspect ratio and asymmetric
• Device structure and design: The evolution of device
architectures, particularly when feature alignment requirements
structure from FinFET to Ribbon FET and Stacked Ribbon
are very small, relative to element thickness. New understanding
FET will be helpful but may not be sufficient to achieve
is needed to create and integrate new materials using
target efficiency needs. Vertical FET, Tunnel FET, and any
low-temperature processes. Backside power delivery
alternate device architectures or structures must also be
needs attention to be compatible with 3D integration while
aggressively pursued. Cryo-FETs operating at very low
minimizing deleterious capacitances. In addition to reducing
temperatures can also be considered, but feasibility is
parasitic capacitance and resistance, thermal dissipation
limited for most applications. These structures can promote
properties of the materials may need to be considered to
low power by reducing short-channel effects and minimizing
minimize heat buildup in scaled and stacked devices.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 96
 deleterious contact-to-gate capacitance and via and contact and low leakage can be deposited at low temperatures,
resistance. Improving gate control by any means (negative but integration requires improved thermal stability and
capacitance or higher effective k) reduces power by means to avoid unwanted H2 doping effects and interaction
improving the gate control and enabling gate-length scaling. with oxygen. There are also some exploratory contact
The addition of ferroelectric materials to the gate stack, and material options for novel FETs, such as spin-FET and
Tunnel FETs, and FETs that can filter the thermionic emission topological transistors, which could potentially provide
over the source-drain barrier can overcome the 60mV/ either improved performance or more functionality.
decade subthreshold swing limit in conventional CMOS
• Interconnect materials: Interconnect materials also need
transistors. The overall reliability of many of these device
to be improved. Copper, which is currently used, requires
schemes has yet to be verified, and for each approach,
a thin TaN diffusion barrier and, in small vias, the barrier
consistent long-term performance is expected to depend on
layer (with a large resistance) can occupy a large fraction
materials choice and fabrication methodology.
of the via volume. Ruthenium, cobalt, and molybdenum are
• Feature size scaling: Very aggressive area scaling can be potential candidates, but attention to other materials could
achieved in 3D architectures by making use of advances have substantial impact.
in Design Technology Co-Optimization (DTCO) to evaluate
• New materials to enable reduction of parasitic resistance,
and optimize power, performance, and area (PPA) at the
capacitance, and device self-heating: Realizing highly scaled
block level. Layout-dependent effects are also important
and 3D architectures in manufacturing will require improved
to consider and may be addressed by, for example, the
accuracy of feature size and alignment (e.g., smaller Edge
transition from double-diffusion break to single-diffusion
Placement Error and uniform gate length control), as well as
break and developing contact over active gate FinFET
sub-nm uniformity in vertical structures where aspect ratio
designs. To reduce device volume and thermal mass,
exceeds 50-100:1. For vertical device schemes, the power
innovation is needed for low thermal budget 3D conformal
consumed per device is reduced but power-per-unit volume
metal and gap-fill processes, budget-stacking methods
becomes very large, demanding new schemes for heat
that are low thermal budget and low cost, and new thinner
dissipation. Vertical device fabrication also requires advances
channel structures. Advanced 2D semiconductors and
in materials synthesis at low temperatures. Advances in
insulators that are conformally deposited and etched in
new materials, including porous metal organic frameworks
desired geometries may provide better electrostatic control
(MOFs) and other organic and inorganic structures are
over the channel and reduce power consumption with
needed. High-quality, low-defect materials are generally
smaller channel resistance and low parasitic capacitance.
achieved at high temperatures where thermodynamic
Chiplet design and integration will also benefit from
driving forces promote crystallization and defect reduction,
emerging System Technology Co-Optimization (STCO)
but high-thermal budgets can damage underlying materials
methodologies.
and material junctions. Better understanding of chemical
• Channel materials: Channel materials will continue to surface processes is needed to enable low-temperature
evolve, from strained Si to SiGe and further to Ge, as kinetic control of material assembly at the atomic scale.
well as to low-D materials, such as 1D carbon nanotubes With highly scaled devices, any material advances that lower
(CNTs) and 2D Transition Metal Dichalcogenides (TMDs). dielectric constant outside of the active device, improve
Low-D materials are promising candidates for extremely variation, reduce self-heating, reduce contact resistance,
scaled devices since they preserve high carrier mobility and reduce interconnect resistance and capacitance will help
with thin body thickness (i.e., ~ 1 nm), critical for superior enable further logic scaling and performance.
electrostatic control. For example, 1D CNT FETs (CNFETs),
consisting of multiple CNTs, are projected to show up to 4.3.1.2 Memory Devices
7x energy-delay product (EDP) benefits compared to 2 nm
Goals/Needs
Si Nanosheets. Other low-D FETs, such as high-effective-
mass 2D TMDs, are promising for low-power applications New memory technologies are—and will continue to be—in
due to reduced tunneling. Channels must be robust with high demand, particularly for applications like Data Centers,
few defects, be highly reliable, enable low resistance ohmic image and sensor processing, and AI. The desire for electronic
contact, and be compatible with low-temperature gate memory is growing at such a fast pace that the silicon needed
dielectric and gate metal with tunable work function. Oxide for memory will soon exceed the amount that is globally
semiconductors with reasonable mobility (~100 cm2/Vsec) available8. Additionally, the energy efficiency of memory

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 97
access, particularly CPU querying of DRAM, has not kept pace Possible solutions
with the advance of computing power (the “memory wall,” as
• Emerging memory: Emerging memory, including Resistive
referenced earlier in the text), which is prompting the need
RAM (ReRAM), Phase Change RAM (PCRAM), Magnetic RAM
for radical new technologies. To meet the growing memory
(MRAM), Ferroelectric RAM (FERAM), Compressed RAM
demand and help quell rising system-energy requirements,
(Z-RAM), and Thyristor RAM (T-RAM), is still “emerging”,
memory density needs to achieve 100X or more of present
with nothing recognized as having the combined set of
levels, with concurrent reductions in power, through
properties that can supplant incumbent SRAM, DRAM,
architectures with superlative bandwidth and those whereby
and NAND Flash technologies, which are firmly rooted in
compute is brought nearer or even into memory.
storing electrons. Emerging memories must overcome
their known shortcomings in cost, scaling, device variability,
Roadblocks/Challenges
repeatability, cyclability, reliability, and other metrics. Early
Improving cache-level memory density (SRAM replacement) applications may be niche uses. For instance, MRAM as a
would directly mitigate the power issue due to data transfer nonvolatile SRAM replacement, and FERAM as a relatively
between CPU and DRAM. However, strict device-level fast, nonvolatile memory that works well for low-power,
requirements must be met which include read/write time low-cycling applications like smart cards. Unlike devices that
close to 10 ns for last-level cache or embedded DRAM utilize electron storage, atomistic motion in ReRAM—and
(eDRAM), and even faster read/write times (about 2 to 3 ns) to a lesser extent in PCRAM—is inherently stochastic (i.e.,
for L2/L3-level cache. Endurance needs to approach 10 to 15
uncontrollable and potentially non-deterministic), leading to
10 read/write cycles, and the operation voltage needs to be
18
substantial variation that limit s current implementation and/
low enough so that the competing memory devices can be or requires very fault-tolerant systems. New architectures
embedded with advanced logic transistors. Hence, significant that make memory more central to digital processing could
improvements in the leading memory options are required to point to and enable memory solutions with properties
enable next-generation energy-efficient, high-speed dense inherent to one or more of the already-emerging memories.
embedded memory.
• Ferroelectric memory: Several forms of ferroelectric
memory can be considered including Ferroelectric random-
As current standalone memory-feature geometries get
access memory, Ferroelectric transistors, and Ferroelectric
squeezed to enable continued 2D generational scaling, there
tunnel junctions or diodes. Ferroelectrics for memory
inevitably comes a point where the next shrink becomes
systems can be fluorite-based materials, including doped
nonviable, such as what has happened with NAND Flash
hafnia, perovskites (e.g., BaTiO3), and wurtzite (e.g.,
where floating gate lengths near 20 nm did not permit
doped AlN, ZnTe, and BeS). There is substantial need for
requisite electron charge storage. NAND’s traditional lateral
deeper understanding of materials, including how defects
strings of cells have now transitioned to vertical designs
impact switching dynamics, wakeup, fatigue, and dielectric
taking advantage of the 3rd dimension—the first true 3D
breakdown, particularly for allowing scaling to sub-1V
homogenous integration. DRAM scaling could also benefit
operation to be compatible with advanced-logic technology
a similar transition to 3D, but it is more difficult because the
nodes. Improved analytical techniques are also needed to
capacitor cells are larger (in both X and Y) than NAND Flash
characterize defect type and density and to identify phase
gates. Vertical memory device stacking will also require
composition. Devices require advances in interfacial metal
new BEOL-compatible select devices with appropriate drive
engineering to enable abrupt polarization switching with
characteristics and very low leakage. For all new integration
applied field to disturb immunity, as well as endurance
methods, there is need for new materials and new chemical
to 1015 to 1018 read/write cycles for cache-level memory
processes, especially deposition and etch control through
replacement. For enablement of ferroelectric transistors,
ALD and ALE, respectively. Relief for this continued scaling
reduction of trap-charging/discharging effects are required
approach may be possible through new architectural schemes
through modulation of the ferroelectric polarization and
that bring memory closer to compute—so-called in- and near-
carrier density, as well as gate stack and source/drain
memory data processing. Additionally, novel architectural
engineering to reduce defects and enable low-voltage
schemes will drive new hybrid and heterogeneous 3D
operation. Tunnel junctions will likely require ultra-thin
integration technologies that require innovations in
(< 3 nm) ferroelectric layer (sub-3nm) with ultra-low defects
chip-level and wafer-level stacking beyond current High
to achieve high Ion with high on/off ratio through high
Bandwidth Memory (HBM) implementations.
tunneling electroresistance (TER).

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 98
 It is still unclear whether this can be reliably achieved in of materials (conductors and dielectrics), new integration
scaled ferroelectric devices, but partial FE polarization, innovations, and new patterning schemes to achieve better
dependent on programming pulse voltage and duration, overlay and reduction in LER are required.
leads to a multitude of analog-like resistance states
suggesting possibilities for use in multi-bit storage. Roadblocks/Challenges
Achieving 3D crossbar arrays of analog-like memory devices
Copper interconnects require a diffusion barrier and metal
could achieve memory densities that enable efficient
fill of small features with both barrier and Cu without voids,
neuromorphic computing. Comprehensive understanding
which is a significant challenge. Furthermore, Cu barriers
in variations of multi-current levels and endurance in scaled
and liners have not scaled as fast as the minimum pitch,
FeFETs is required for these high-density configurations,
which results in smaller Cu conduction cross-sectional areas,
while FTJs with diode-like current-voltage characteristics
increased Cu resistivity, and intrinsic reliability concerns
could potentially provide selector-free, two-terminal, multi-
(Biased Thermal Stress and Electromigration).
level memory cells in a stacked crossbar array.

• Spintronic memory: Options for spintronic memory Possible solutions

include Spin-Transfer Torque MRAM (STT MRAM) and
Novel barrier and liner materials that can be aggressively
Spin-orbit torque MRAM (SOT MRAM). STT MRAM requires
thinned to enable gap fill and improved line resistance while
ferromagnetic material engineering that enables lower
still meeting reliability targets via resistance can be improved
switching current for magnetization reversals, as well as
with the use of organic blocking molecules for selective
device designs that enable lower switching current due
barrier deposition. New Integration approaches, such as
to larger effective spin-transfer torque at the same time
hybrid metallization and semi-damascene subtractive metal
without impacting tunneling magnetoresistance (TMR). To
etch methodology, could also be used to reduce interconnect
enable magnetic reversal with low switching current, in SOT
resistance17. Additionally, Cu replacement candidates that
MRAM, new materials are needed with larger spin-orbit
require no barrier layers (e.g., Ruthenium, Cobalt, Tungsten,
effects. Also, high density configurations will require new;
and Molybdenum) could be explored18. Advanced low-k
device designs that integrate other phenomena, such as
materials can be introduced to decrease line capacitance, but
voltage-controlled magnetic anisotropy, or magnetoelectric
this requires materials process approaches to maintain pattern
and antiferromagnetic effects.
fidelity and avoid dielectric-constant degradation during
• New memory: Devices that can rival incumbent technologies etch and cleans. An alternative to achieve low interconnect
and even emerging technologies have a high bar. The capacitance is to implement highly porous materials, such as
ultimate device would have a deterministic, analog-like, MOFs, as well as processes for controlled airgaps. Adoption
and linear progression of memory states achievable at low of backside power delivery19 will enable reverse-scaling of the
voltage and/or low current with low nsec or psec switching. minimum pitch, as well as independent optimization of signal
Barring achievement of such an ultimate memory, cracking interconnects (front side of devices) and power wires (back-
the inherent issues with current emerging memories, side of devices).
discussed in this section and 4.2.1, could help win adoption
in the memory hierarchy in niche applications or enable new 4.3.3 Two-Dimensional (2D) Materials
architectural schemes like neuromorphic.
Goals/Needs

4.3.2 On-die Interconnects Low-dimensional materials (LDMs), which include mainly 2D

materials and arrays of aligned 1D carbon nanotubes (CNTs), are
Goals/Needs
promising candidates for extremely scaled devices, due to their
On-die interconnects are responsible for carrying signals ultra-thin body, excellent electronic, and thermal and chemical
and power to devices. Power interconnects require low properties20,21. 2D conductors (e.g., graphene and MXenes)
resistance, while signal lines benefit from low capacitance could decrease sheet resistance, dissipate heat, and avoid
and/or low Resistance-Capacitance product. Area scaling has electromigration. Semiconducting 2D materials (e.g., MoS2 and
been driving an exponential decrease of the minimum metal WS2) are promising for low-power applications due to enhanced
pitch, which is expected to cross the 20 nm barrier by the end electrostatic control over the channel, reduced tunneling, and
of this decade16. As the minimum metal pitch scales to attain lower projected variability. Insulating 2D materials like hBN may
performance and reliability targets, continuous improvement be used as dielectric in FETs with 2D semiconducting channels

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 99
(to form a clean van der Waals interface) and in other memory of other materials on them. Low temperature processes are
devices. FETs with channels made of multiple aligned CNTs needed for BEOL applications, but are not a requirement for
(CNFETs) are promising candidates for energy-efficient digital FEOL. Potential pathways for minimization of defects in 2D
logic, achieving 7× energy-delay product (EDP) vs. Si FETs. materials include low-temperature synthesis using reactors
with different temperature zones; improved transfer using
LDM-based commercial products have been demonstrated. wafer de-bonding and involving thicker 2D-layered materials
CNFETs have been integrated into Si industrial facilities (which are more mechanically stable than monolayers);
(e.g., SkyWater Technology) and are used for R&D of future employing atomic layer etching; and tuning the energy
commercial products at ADI). Graphene, a 2D semimetal, delivered during metal evaporation. Discovering new 2D
is present in commercial sensors and specialty cameras. materials that overcome the limits of high-temperature
Moreover, low-temperature fabrication enables monolithic chemical processing and optimizing the synthesis of materials
3D integration of logic and memory layers, unlocking 1,000x compatible with 2D semiconductors, possibly including CaF2,
EDP benefits. Even a single CNFET layer integrated on Si CMOS PTCDA, BiSO5, SrTiO3, and others, could provide new options.
achieves 5-10x benefits (physical-design-proven using SkyWater For CNFETs, CNT band gap uniformity (e.g., chiral enrichment)
CNFET experimental data). However, new chemical processes and deposition methods (e.g., dimension-limited self-alignment)
are needed that can integrate high-performance LDMs into are critical to ensure highly dense aligned CNTs. Furthermore,
extremely scaled devices. For 2D, the focus is on wafer-scale development of theoretical models for LDM-based FETs are
synthesis and low-temperature, low-defect material deposition. critical to focus the experimental effort.
For 1D, the focus is on uniform and controlled assembly.
4.3.4 3D Monolithic Integration
Roadblocks/Challenges
Goals/Needs
Improved materials and processes are needed for ohmic contact
As the limits of physical and equivalent scaling are getting closer
and for gate-insulator integration in LDM FETs. Depositing
to reality, one key opportunity is in 3D monolithic approaches,
LDMs on Si microchips with suitable (low) densities of defects
where chemical processing proceeds in third dimension at the
is the main challenge. Most 2D material synthesis methods
wafer-level. To some extent, this is natural extension and builds
require high temperatures (>800ºC) incompatible with
on recent advances in backside power delivery19. There is a
BEOL CMOS processes and scaling of transfer processes
huge range of possibilities in this space, including: significant
is particularly difficult due to the formation of cracks and
increases in logic density by having two or more devices on top
impurities. Coating 2D materials with metals or insulators,
of each other; significant performance benefit, both at block
or etching patterns or vias, can generate additional defects.
level and at transistor level, as materials and structures can
The presence of high densities of defects in the 2D materials
be decoupled in stacking approach; and integration of other
reduce performance and yield while increasing variability.
functionalities on the same logic chip, including memory, RF,
In 2D semiconductors, while n-type contact resistances (RC)
and power delivery, to name a few. The goals should be to
close to the quantum limit have been demonstrated, scaled
better understand the benefits of these approaches from the
p- and n-type low-RC contacts (<15 nm) must be determined.
product perspective, via DTCO or STCO, as well as challenges
An integration milestone for scaled p-type CNFETs (i.e.,
in processing and co-integration of all the ingredients.
including dense CNT, scaled low-RC contacts, and self-aligned
extension doping) has been demonstrated21. Advances in CNT
Roadblocks/Challenges
purification (i.e., metallic CNT removal) and design techniques
(e.g., designing resiliency against metallic CNTs - DREAM) 3D monolithic integration has many clear opportunities and
have enabled imperfection-immune VLSI circuits. However, many difficult challenges that require both creative innovation
the critical challenges to enable benefits are the stringent and disciplined execution. Key system-level challenges
targets for wafer-scale uniform CNT orientation, as well reside in understanding and defining all the key process
as controlled and uniform pitch in range 2-10 nm, which ingredients that will enable 3D monolithic integration to
cannot be achieved by any known methods today. scale for implementation. In the technology space, the key
concern is the construction and processing of tall, high-aspect
Possible solutions ratio features necessary for these implementations. While this
is something that is commonplace in DRAM, it is something
For 2D materials, the most important need is for improved low-
that logic technology must learn and adopt for their specific
temperature synthesis and/or transfer, etching, and deposition
needs and applications.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 100
Possible solutions Figure 4.5: DOF inversely proportional to NA2

Most urgently needed for 3D monolithic integration to become

a viable option for scaling of logic and added functionalities
is careful and detailed DTCO analysis of key options and
technology definition to develop required deposition and
etch process techniques. One such specific item in stacked
transistor implementation is the need for what is called “split • EUV + DSA: Resist materials are analyzed by quantifying
gate”, where the gates of top and bottom transistors can be resolution [R], line-width roughness [L], and sensitivity [S],
addressed separately and independently . Questions that
22
but optimizing one degrades at least one of the others. This
must be vetted and understood revolve around the need for “RLS tradeoff” is a dominant problem that needs significant
such a feature, which is a given in current technologies, as well attention to resolve resists at acceptable doses. One way to
as areas required for such connection, the process approaches, break the RLS trade-off is using Directed Self-Assembly (DSA),
etc. This simple example proliferates to thinking about every a complementary technology to EUV. Block co-polymer (BCP)
aspect that may be taken for granted in current technologies, rectification of EUV resist uses lithographically defined guide
but ones that may impact the ability to deliver value-added 3D patterns to leverage phase separation of the BCP to create
monolithic integration approaches to bear. well-defined line/space structures and hexagonal contact
holes (CH) that commensurate to the EUV design layout. BCP
Similarly, chemical process technologists are already working has built-in dimension to extend scaling and is tolerant to
diligently on identifying and addressing process challenges resist defects, improving overall pattern uniformity (LER, LWR
related to 3D monolithic integration23. Thankfully, combining and CDU) compared to optical lithography alone.
many of the ideas from other sections of this chapter will be
Challenges
key possible solutions. For example, to address challenges of
height stack in 3D monolithic integration, one can consider • EUV: Most current EUV resists in production are polymer-
switching from thicker Si nanoribbon channels to 2D materials. based, chemically amplified resists (CARs), while metal
In addition, ALD and ALE technologies will be key to overcome oxide resists (MORs) are a new platform. Entering the
aspect ratio in these structures. hyper-NA realm, resist thickness scaling (10nm expected for
hyper-NA) is introducing limitations and challenges that will
4.3.5 Patterning, Chemical Processes and amplify line-edge roughness and defects25.
Manufacturing
Thin polymer resist challenges26
4.3.5.1 High NA Lithography and Directed Self-
• Stochastics (thinner resists that have more molecular
Assembly
inhomogeneity due to molecular size, aggregation/
Goals/Needs segregation, and multiple components).

• EUV: Lithography has enabled chipmakers to develop smaller • High photon shot noise effect.
and faster devices at advanced nodes. Utilizing the 13.5 nm
• Etch transfer limitations.
wavelength, ASML’s 0.33 NA EUV scanners are being used by
major companies for advanced chip production. However, below • High underlayer effect.
32 nm pitch it will become difficult to pattern future chips with
• Secondary-electron effect (blur of ~4 nm becomes part of
direct print EUV at 0.33 NA and low defects. This problem can
the resolution).
be addressed with double patterning using low NA, but it brings
process complexity, increased cost and imposes design rule Metal oxide resist challenges26
restrictions. Once 0.55 high-NA EUV scanners become available,
• Are exclusively negative tone-resists. To print contact
the industry will learn if line/space patterns can be printed
holes, one would need a bright-field mask which is prone
directly with one exposure below 20 nm pitch24.
to mask defects.
Looking forward to the next technology, hyper-NA (>0.7
• Instability due to interactions with underlayers
NA) is a novel area that will enable transistor scaling with
(Mechanism is poorly understood.)
a single pass. For hyper-NA, the minimum projected pitch
resolution is ~12nm and since depth of focus (DOF) scales • Instability due to interaction with atmosphere
with NA2, 10nm resist thickness is expected (Figure 4.5). (Mechanism is poorly understood.)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 101
 • Need to improve quantum efficiency of the resist/ and segregation. New design structures will require ultra-thin
absorption (Dose is inversely proportional to pitch^2 and resist and underlayer combinations. The impact of polymer
can inadvertently result in a dose penalty. Only method to size and conformation on LER needs to be understood. And
compensate for this is by improving resist sensitivity while future resist design needs to consider the range and stochastics
maintaining good atmospheric stability. This will help impact of photoelectrons and secondary electrons.
keep the EUV source power under control.)
• Power source: Higher power light sources are needed
• Secondary electron effect (Blur is less than polymer because of how dose scales over pitch.
resists but will further limit pitch resolution.)
• New resist materials and resist processing: Dry deposition
• New resist materials and chemical processes for and dry development (i.e., by Atomic Layer/Molecular Layer
deposition and dry development are needed Deposition and chemically selective dry etching, respectively)
are important directions for enhanced study. Modifying
Polymer resists are less prone to interaction with the wafer deposited and/or developed resists with further chemical
stack and atmosphere compared to MOR. processing are directions for study, such as polymer
addition via vapor phase infiltration, resist shaping by
• EUV + DSA: EUV resist pattern rectification for line/space
atomic layer deposition, and atomic layer etching. New
(L/S) and contact holes (CH) will need new material invention
material compositions, including metal organic frameworks
for guide patterns, BCP material, and BCP etch development
and related materials may also prove useful.
that meet stringent roughness and defectivity requirements.
LS and CH are formed by chemo-epitaxy, and CH rectification EUV + DSA
does not work for layout used in logic applications .
27,28
To scale with hyper-NA, both L/S and CH applications need
L/S challenges 28,29
Gen2 high-chi BCP materials <20nm pitch with line-edge
roughness and line-width roughness <1.7nm. Diblock systems
• Limited to single pitch and unable to use in applications
are ubiquitous, however, new tri-block A-B-C copolymers
that require variability (multiple pitches, varying spaces,
with high-etch selectivity will broaden application of DSA.
and large depopulated areas)
Etch selectivity and roughness values can be enhanced by
• Sensitive to double-patterning CD variability (small CD block copolymer processing using sequential infiltration
variations needed) (SIS) of a single BCP block relative to another, as well as dry
development rinse material to aid with pattern collapse. New
CH challenges30
BCP annealing techniques, such as solvent vapour annealing of
• Difficult to print with tight pitch (Need to break into BCP, will allow for thermally unstable BCP molecules.
multiple passes, printing every other CH and then doing a
second pass. Hyper NA will enable single print CH.) Moonshot ideas for EUV and EUV+DSA

• Strategies to control pattern placement error (PPE) and 1. The trend to ultra-thin resist is going toward a single
defectivity (partially closed and missing holes) monolayer, how can the monolayer,

• CH rectification pattern, limited to hexagonal symmetry. a. be turned into an etch mask?

b. be used to build a resist layer?

Challenges and limitations common to both EUV and DSA
are metrology techniques to map chemical location and 2. How can we pattern a thin resist that no longer can be
characterize and quantify chemical composition on used as an etch mask, in combination with complementary
patterned substrates. technology like DSA for pattern transfer?

3. Photon patterning is capped after hyper-NA, so what are

Possible solutions
other creative patterning strategies that do not use photons
EUV (e.g., helium ion beam lithography)?

• Scaling resists to ultra-thin (≤10nm): As feature sizes shrink, 4. Today, DSA is pitch limited. Moonshot needs for DSA
resist molecular components become a substantial fraction of include a guide pattern and BCP material design for pitch-
the feature size. The molecules comprising resists need to be independent self-assembly. Moreover, invention is required
single-component, small building blocks to prevent aggregation to break hexagonal symmetry to normal CH rectification.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 102
4.3.5.2 Atomic Scale Processing, including Atomic challenge is to create new viable and scalable low-temperature
Layer Deposition and Atomic Layer Etching processes with atomic precision to solid films and material
junctions. In backend applications, maintaining low temperature
Goals/Needs
(<400°C) is critical to avoid dopant and metal diffusion in
Novel device structures and materials will require new underlying layers. Therefore, unlike high-temperature processes
understanding and improved control of materials synthesis and like epitaxial growth, low temperature imposes limits on the
processing at the atomic scale. Atomic Layer Deposition (ALD), extent to which equilibrium thermodynamics can be employed
using a controlled sequence of self-limiting surface reactions, to drive desired outcomes. During ALE, diffusion of etchant
is a current workhorse method, and quasi-self-limiting Atomic species into regions not being etched must also be avoided.
Layer Etching (ALE) is quickly gaining speed toward full-scale Moreover, ALD and ALE are inherently random, so that steric
manufacturing. Area-selective Deposition (ASD) 31, often hindrance and other molecular effects lead to intrinsic non-
achieved using combined deposition and etching, is also of uniformities at the atomic scale. Understanding molecular-scale
substantial interest. Other Atomic Scale Processes, such as stochastic phenomena during ALD and ALE will be important as
Atomic Layer Annealing, are also being explored. However, feature sizes continue to approach molecular dimensions.
these methods do not yet realize the full potential for control
of atomic placement and bonding configuration that is desired Possible solutions
for targeted device designs. New advances in molecular
• Chemical selectivity: Means to identify, promote, analyze,
engineering are needed, including precursor molecule design
and quantify chemical selectivity in both ALD and ALE is a
and synthesis, development of novel passivation chemistries,
high priority for future processing. Advances in selectivity,
atomistic and AI-based modeling, and directed chemical
including ASD and selective etching, will require a balance
synthesis based on self-limiting principles of ALD and new ML
of underlying thermodynamic driving forces and chemical
control strategies yet to be realized.
reaction rates. Surface passivation may block an undesired,
energetically favorable reaction. But surface control to
Roadblocks/Challenges
attain intrinsic selectivity, where molecular passivation is
The extent of film growth during an individual self-limiting ALD not needed, may be more favorable if the rate of a desired
cycle depends on the structure of the reactive precursors and process can be increased to limit the extent of ancillary
the nature of the surface reactive sites. This means that a better unwanted nucleation. While ALD allows the thickness of
understanding of mechanisms during ALD nucleation, and how uniform films to be controlled on high-aspect ratio surfaces
they transition to continuous growth, is needed. Understanding with sub-monolayer or atomic-scale precision, the chemical
this transition in reaction mechanism becomes more critical selectivity achieved in ASD may also provide a pathway
when ultra-thin films are being formed. Similarly, many to control lateral “mushroom” growth. Researchers are
mechanisms in ALE are described, but it is still unknown how beginning to understand how precursor interactions on non-
ALE mechanisms evolve as etching proceeds or how they apply reactive surfaces are influencing the shape and extent of
to ultrathin film. Reliable tools to analyze and quantify surface lateral overgrowth of resulting ASD patterns. Better means
reactions, and metrology methods to monitor reactions in real- to quantify pattern shape, such as analysis of vertical
time during manufacturing also remain a significant challenge. selectivity, could lead to new understanding to address
the fundamental limits of stochastic surface reactions
New devices need to be constructed using many different during ALD and ALE. Moreover, most studies of ASD focus
materials exposed on the surface during fabrication. This on “two-color” processes, where the starting surface has
poses a challenge for Atomic Scale Processing where desired two exposed materials (i.e., two colors), and one new
reactions on one exposed material may cause detrimental material is deposited on one color and not the other. New
results or unwanted damage to adjacent materials. The advent approaches are needed for more complex “multi-material
of 2D materials, for example, provides additional challenges, ASD” to combine multiple ASD processes and materials, and
since the 2D structure is defined by built-in chemical anisotropy “multi-color ASD” involving more intricate starting patterns.
with reactive edges and relatively passive exposed surfaces. Also, “color-addition ASD” schemes using ASD and photo-
patterning could build-up complex 3D circuitry with fewer
The reactants used during ALD and ALE are molecules with built- steps and improved alignment.
in atomic scale precision, and ALD uses this precision to achieve
• Precursor and process co-design: Synergistic design of
average uniformity and conformality over large areas. A key
precursors and processes is an important direction for

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 103
 expanded research. New understanding of precursor important to improve manufacturing reliability and cost, as
stability, lability, and reactivity, including, for example, the well as minimize energy use and environmental impact.
development of novel Hf compounds, has led to substantial
advances in ALD processes and ALD integration into 4.3.6 Characterization and Metrology
semiconductor manufacturing. For instance, precursors
Over the next decade, characterization and metrology
specifically designed for selective reaction on a desired surface
methods will be challenged by the increasingly critical
would be of high value. Precursor/process co-design could
measurement needs for new materials, structures, devices,
also lead to reactants that follow desired predetermined
and materials processes. Meeting these challenges requires
reaction pathways when specific co-reactants are used
increasing the connections between process/structure and
under predesigned reaction conditions. This could allow for
metrology. A notable change in measurement requirements
low-temperature deposition of stable, low-defect crystalline
comes from the shift to, and the increase in complexity of, 3D
materials for advanced device systems.
structures. Two prominent examples of considerable importance
• Process intensification: Atomic scale processing may also to metrology equipment suppliers are the vertical stacking of n
benefit from new synergistic approaches where deposition and and p MOS transistors, which is predicted to occur sometime in
etching are integrated, either as a repeated cyclic sequence, the next 10+ years, as well as increased stacking of multilayer
or as simultaneous co-localized or adjacent reactions. The films in memory with remarkably high aspect ratio holes. The
importance of coupling multiple synthesis steps into a spatial resolution of microcopy and associated characterization,
single intensified process is well recognized in the chemical such as electron diffraction and X-Ray characterization, requires
industry, and analogous advances in process intensification are advances in data analysis to enable routine use. Another key
important to pursue in electronics manufacturing. Deposition and aspect to characterization and metrology for these structures
etching can be balanced by adjusting temperature to control is the need to provide fundamental materials property
equilibrium product distributions, but this balance typically information for the nano-scale structures at a much wider range
requires high temperatures where unwanted dopant and metal of wavelengths (from the IR to EUV to X-ray), including other
diffusion often set in. New techniques combining process properties such as thermal mechanical and electrical. Defect
reactions at low temperature may hold promise to guide detection is challenged by the need to provide statistically
reaction pathways needed for future device structures. significant information from devices with decreased feature
dimensions and higher aspect ratios. Machine learning and AI
• Chemical process modeling and control: Emerging
will be required to help enable metrology equipment control,
capabilities in AI and machine learning may provide new
data analysis, and recipe creation. NIST has unique capabilities
avenues to understand, design, and optimize individual
that enable new measurement method R&D and provide critical
elementary reaction steps, as well as means to couple
standards and reference materials. Key institutions and partners
reactions and complex process sequences into full
can help drive the development of an ecosystem that enables
manufacturing design. New tools for in-situ reaction analysis
rapid scaling and concepts like hybrid metrology. This would be
combined with directed AI analysis and modeling will be
further enhanced through infrastructure development.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 104
Contributors
Tayseer Mahdi (Intel) – Chair Jason Kawasaki (UW-Madison) Shaloo Rakheja (University of Illinois)

Kanad Ghose (SUNY Binghamton) – Vice Chair Jiyoung Kim (University of Texas/Dallas) Antonio L.P. Rotondaro (TEL)

Ramesh Chauhan (Qualcomm) – Vice Chair Steve Kramer (Micron Technology) Shubham Sahay (IIT/Kanpur)

Kostas Adam (Siemens EDA) Markus Kuhn (Rigaku) Seunghee Shin (SUNY Binghamton)

Kaveh Ahadi (NCSU) Mario Lanza (KAUST) Galen Shipman (LANL)

James Ang (PNNL) Rinus Lee (TEL) Yulim Son (SK hynix)

Kirk Bresniker (Hewlett Packard Enterprise) Timothy Lee (Boeing) Min Tsao (Siemens EDA)

Sou-Chi Chang (Intel) Wei Lu (University of Michigan) Brooke Tvermoes (IBM)

Gary Chen (TSMC) Matt Marinella (ASU) Eric Van Hensbergen (Arm)

Yiran Chen (Duke University) Prabhat Mishra (University of Florida) Jian-Ping Wang (University of Minnesota)

Amitabh Das (AMD) Subhasish Mitra (Stanford) Ying Wang (UW-Madison)

Alain Diebold (SUNY Poly) Tiago Muck (Arm) Glen Wilk (ASM)

Swaroop Ghosh (Penn State) Shashank Nemawarkar (GlobalFoundries) Jun Xiao (UW-Madison)

Dinesh Gupta (IBM) Andreas Olofsson (Zero Asic) Tenko Yamashita (IBM)

Steve Hoover (Redwood EDA) Gregory Parsons (NCSU) Kashyap Yellai (SRC)

Jamil Kawa (Synopsys) Marko Radosavljevic (Intel) Zongfu Yu (UW-Madison)

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(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 106
Chapter 5

Analog and Mixed-Signal

Semiconductors
5.1. Introduction Analog electronics deals with real-world continuously variable
signals of multiple shapes. The analog electronics domain
The recently published SRC Decadal Plan articulated several encompasses multiple dimensions, including sensing, analog and
major challenges and seismic shifts with direct implications digital/mixed signal processing, data conversion, communication,
for analog and mixed-signal (AMS) semiconductor technology. computation, and power management. Following this
These challenges and their respective goals are as follows: introduction, the chapter is presented in 3 sections:

(#1) Fundamental breakthroughs in analog and mixed-signal • Analog and mixed-signal circuits and processing
hardware are required to generate smarter, lower-power world-
machine interfaces that can sense, perceive, and reason. • Power conversion, management, and distribution (including
high-voltage/high-current systems)
Grand Goal #1
Analog-to-information compression/reduction with • RF-to-THz devices, circuits, and systems
a practical compression/reduction ratio of 105:1 that
Each of these technical areas feature a number of different
drives to a practical use of information versus “data” in
technologies that address numerous applications. References
a way that is more analogous to the human brain.
for further reading are provided for each section. We also refer
the reader to Chapter 6, which addresses optical, photonics,
(#3) Always-available communication requires new research MEMs, and sensor technologies, which are often intertwined
directions that address the imbalance of communication capacity with analog/mixed-signal semiconductor issues.
vs. data-generation rates (including 6G class wireless technologies).
For many of the above topics, there is an integration imperative.
Grand Goal #3a
While analog/mixed-signal technologies often exploit more
Advance communication technologies to enable moving
mature lithographic nodes, it is frequently desirable to fabricate
around all stored data of 100-1000 zettabyte/year at
integrated circuits in a <55 nm node and use ultra-small and
the peak rate of 1Tbps@<0.1nJ/bit.
environment-proof packaging. Heterogenous integration
Grand Goal #3a (HI) technologies, including chiplets and 3D integration
Develop intelligent and agile networks that effectively techniques, will have a significant impact in mixed-signal
utilize bandwidth to maximize network capacity. products in the coming decade. HI presents an opportunity to
integrate disparate technologies into small form factors, but

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 107
introduces a whole new set of interface issues for the die-to- special requirements with respect to extreme conditions. This
die interconnect. Analog and mixed-signal technologies will may include temperature (extremes at both high-temperature
take advantage of materials and device advances driven by and cryogenic operation), voltage/current/power, and
digital technologies (see Chapter 4). For high-frequency and exposure to radiation. In addition to posing special challenges
high-power devices, new materials solutions need to be further for devices, these applications may also introduce demands on
developed for the specific needs of analog applications. SiGe, packaging, test, and EDA/simulation.
InP, SiC, and GaN devices are now being integrated at higher
Verification, production test (including known good die),
levels of hierarchy in ICs. New materials and device solutions
metrology, quality, security, and failure analysis all present
such as AlN and carbon-based electronics need to be included
unique challenges in the sensor/analog/mixed-signal domains.
as future materials to be integrated (provided present
Significant breakthroughs and technology development will
manufacturability challenges can be overcome).
be required in these areas and are covered in detail in other
chapters of this roadmap.
New challenges arise to address the deluge of analog
data in the RF to mmWave and optical regimes, including While analog/mixed-signal semiconductor systems share
devices, interconnect, power, dynamic range/ linearity, noise, many fundamental characteristics with the digital/compute
packaging, antennas/interface, interference, and signal technologies that tend to drive a large share of the market and
processing. It is important to optimize application-specific data R&D spend, they also introduce some unique considerations.
rates for single-input-multiple-output (SIMO) and multiple- These often require special approaches to device and circuit
input-multiple-output (MIMO) systems (e.g., for automotive design, system architecture, and manufacturing. AMS circuits
and industrial radars). It behooves designers to consider that are often more sensitive to device mismatch, transistor gain
low-level sensor fusion will require moving 10s-100s of Gbps of and linearity performance, and parasitic effects. As digital
radar, camera, and lidar data to high-performance nodes in the CMOS has embraced greater sophistication, the new topologies
near future, and that such high-traffic signal processing should have often presented novel challenges for mixed-signal design.
be compatible with passive cooling and IC packaging.
As a final introductory note, the overwhelmingly most
For intelligent sensing, application requirements are driving important metric for all of the applications is whether or
integration for size and weight, exploiting traditional and not the developed technology (device, circuit, architecture)
emerging monolithic technologies in addition to using board, actually works in the intended application over process,
flex, and package integration methods such as a triple-stacked voltage, and temperature with high-yield and robust/safe
sensor example (pixel+DRAM+logic) and various back-end long-term operation. The AMS space is exceptionally diverse,
monolithic or near monolithic integration technologies. often requiring work across multiple technical domains.
New sensor modalities—including quantum sensing—need This suggests that issues like EDA, security, metrology,
to be integrated at the system level. System codesign/co- packaging, and education/workforce development will need to
optimization is necessary to satisfy the requirements stressing comprehend AMS trends and challenges.
higher energy-cost-of-data-transfer versus processing.

There are numerous packaging and heterogeneous integration 5.2. Analog/Mixed-Signal

challenges. At multi-GHz frequencies and beyond, interfaces
to the outside world are challenged by parasitic effects from
Circuits and Processing
traditional resistance, capacitance, and inductance to fringing, The SRC Decadal Plan published in January 2021 outlines
roughness, and index of refraction. The parasitic effects have new trajectories for analog electronics. This section of the
severe consequences for transmission loss and reflection, roadmap will summarize the short-, mid-, and long-term
impacting efficiency and signal-to-noise ratio. Additionally, outlook for analog-signal processing as it pertains to emerging
integration of multiple technologies will be required and applications and trends driving analog hardware. Analog-
may not be possible on a single chip and/or require very component hardware is essential to world-machine interfaces,
closely coupled passives. Large arrays in small form factors sensing, perception, and reasoning systems. Information from
will challenge the pitch and likely require new 3D solutions. the physical world is analog and the exponentially increasing
In-package antenna technologies and exploitation of “meta- number sensors globally is creating a large number of analog
surface” technologies will likely be important. inputs. Digitization of these signals would create a digital data
load that would be near impossible to consume in downstream
Because analog/mixed-signal ICs are often working at the
digital processors. Analog-signal processing or processing at
interface with the physical world, many applications present

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 108
the “analog edge” can help mitigate the number of signals that device behavior. Much like the high-performance computation,
must be processed digitally. The following subsections cover edge computation will be heterogenous—and will increasingly
the following: utilize processing in the mixed-signal/analog domain.

• How analog and mixed-signal computation must scale to Over the next decade, the known art of analog design can
accommodate “analog edge” processing. be continued by series-parallel connections of multiple small
devices, in effect using arrays of small devices to approximate
• The projected advancement of data converters necessary to
the larger and better-matched devices that the analog
accommodate larger bandwidths, higher throughputs, and
designer is familiar with.
finer resolutions.
Much effort has been expended by the semiconductor
• Physical wireline and die-to-die interfaces; security; sensor
fabrication providers in characterizing MOM capacitors. Analog
fusion; clocking systems; and power mitigation techniques.
signal processing often looks to exploit parasitic artifacts
and secondary device characteristics in the high volume
Technology scaling and application drivers
“digital” processes (including the interconnect layers). New
Among the many application drivers that require innovations generations of process technology present new challenges
in the analog/mixed-signal domain, the primary drivers include (and opportunities), calling for characterization of variability/
low-cost, energy-optimized intelligence across communication repeatability of these “parameters”.
networks and compute; high-throughput, low-latency, and
Emerging analog signal processing
high-bandwidth 6G wireless communication sensing; and high-
performance Data Centers. In recent years, analog-in-memory computing for AI/ML has
been seen in edge-based IoT systems due to their energy-
The performance and power-efficiency demands of efficient operation. Emerging bio-sensing and bio-computing
the many emerging applications require drive towards components necessitate analog processing due to the
2.5D/3D architectures that bring challenges of cost, design nanoscale nature of the compute or sensing action. Massive
methodologies, and thermal management. Technology scaling MIMO-array processing has seen optimum energy-efficienct
is heading toward sub-5nm nodes that incorporate gate-all- operation when employing a hybrid approach of processing
around transistors, nano-sheets, and fork-sheet-based devices. across both the analog and digital domains, leveraging the
Advanced packaging also plays an important role in shrinking best of each. Fully homomorphic encryption and implicit logic
large systems to nano-scale implementations. is a tremendous opportunity for analog computation, where
analog computation is carried out without a DAC on the input
This section reviews various aspects of analog and mixed-signal
and an ADC on the output, enabling implicit equation solutions
processing and how each is expected to advance in the next
(e.g., modulus of P/Q).
five to 10 years. Each different area outlines how specifications
and metrics are expected to advance over a 10-year period.
Near zero-power (nano power) processing
Analog and mixed-signal computation
Nano power involves applications that support quiet and/
Mixed-signal computation or sleep mode operation into the nanowatt regime, and yet
may still consume orders of magnitude more power during
The common theme emerging in analog/mixed-signal
awake states. Key applications today and coming in this space
processing is that design must exploit analog processing
include the Internet of Things (IoT) and wearable applications
opportunities as they arise and daringly move the traditional
addressing personal medical data collections. In the medical
boundary between analog and digital to enable more pre-
space, data collection is centered around cardiology, but the
processing in the analog-signal domain when energy efficiency
anticipated future includes monitoring physio chemistry using
or performance warrant such a decision.
blood, sweat, and/or saliva. These exceptionally low-power
Analog circuits in the next decade will evolve to make use applications provide challenges for lowering the processing
of the many thousands of devices that can be dedicated to power and for system power management (as discussed in the
analog tasks. Analog design in prior years has depended next section).
upon the detailed performance of a few devices, including
Cross Reference: Chapter 4, sections 4.2.4 discusses
the input stage of an amplifier or the elements of the typical
analog computational accelerators, section 4.2.6 discusses
PLL circuit. These can be drawn as a schematic drawing,
Neuromorphic computing.
comprehended, and improved by close scrutiny of individual

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 109
Data Converters
performance much more challenging. This drives the need for
As described throughout the SRC Decadal Plan for innovations going forward at the levels of system and data-
Semiconductors, data converters [i.e., analog-to-digital converter architecture.
converters (ADC) and digital-to-analog converters (DAC)]
will play an increasingly critical role in a wide variety of As shown in Figure 5.1, there is an extremely wide range of
applications, ranging from intelligent sensing for edge emerging applications that will require new and significantly
computing to 5G/6G wireless/wireline communications to improved data-converter performance. As an example, consider
automotive applications like motor control and radar. To the AMS computation techniques for more signal processing in
meet the system requirements for these applications, data the analog domain proposed earlier, as well as data-converter
converters with an extremely wide range of performance will architectures for edge processing that enable efficient and
be needed in the coming years (Figure 5.1). low-latency sensing-to-analog-to-information functionality,
as described in Chapter 1 of the SRC Decadal Plan. Another
Meeting these levels of performance will require innovations example of an emerging application is accurately sensing
in process technologies, application, and system-level low-frequency/DC current signals in EV battery management
architectures, as well as in the data-converter architectures applications where several hundred volts are used.
themselves. Advances in process technologies often help since, Applications like this require specialized process technologies
in most cases, the transistors become faster as the geometries and architectures for the analog frontends.
shrink. Some specific processes that are more targeted toward
analog/mixed-signal applications, such as fully depleted silicon- In the mid-frequency range (e.g., 100KSPS to 500MSPS),
on-insulator (FDSOI) and silicon germanium (SiGe) BiCMOS, applications ranging from high-fidelity digital audio to medical
offer some significant advantages, including improved applications such as MRI and ultrasound to automotive
isolation, tightly controlled threshold voltages, and high-speed applications like motor control and safety (e.g., air bag
bipolar transistors. However, in the case of CMOS technologies control) will also require significantly improved performance
that are targeted at high-performance digital applications (e.g., (e.g., cost, power, accuracy, robustness, etc.), as volumes
5nm CMOS), the supply voltages are consistently shrinking, and system performance demands increase. Since many
and layout-dependent effects (LDE) become more prevalent of these applications require high-accuracy, low-distortion
and actually make designing data converters with the required performance, in addition to being resistant to interference

Figure 5.1: Data-converter universe: application, resolution, and throughput.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 110
and reliable over a wide range of operating conditions, data- Examples of emerging architectures for very-high-speed
converter architectures that meet these requirements with low applications include the continuous-time pipelined ADC that
cost and low power will become increasingly critical. For ADCs has been published by Analog Devices; ring-amplifier-based
in car radio receivers that produce high-fidelity audio from architectures (e.g., pipelined ADCs) that have been published
the received signals, spurious free dynamic range (SFDR) is by researchers at Oregon State University and then IMEC;
the critical specification. Requirements such as these become and time-based ADC architectures such as those published
even more critical for medical and safety applications that by researchers at UC San Diego and Texas A&M University.
can impact people’s health and quality of life. Possible new Extensive research into optimal time-interleaving techniques is
data-converter architectures that could be applied to this ongoing and will need to continue into the future. It must also
application space include AI, ML-assisted, time-based, hybrid be noted that in the high-speed, high-performance application
SAR/pipelined ADCs, etc. space, the need for correspondingly high-performance clocks
is equally critical. For example, the 10-b, 10Gs/s ADC for 6G
There is also an extremely wide array of emerging applications, small cell/CPE use cases described above would require a clock
ranging from 5G/6G communications and high-speed serial at the ADC sampling circuit with ~40fs rms jitter, which is not a
links to FMCW/PMCW automotive radars and lidars that trivial requirement. This need will also drive close collaboration
require ultra-high speed/high- bandwidth, high-performance between developers of data converters and clock IP.
data converters of one kind or another. For example, for
6G small cell and customer premises equipment (CPE) use As mentioned in the chapter introduction, “fit for purpose”
cases, ADCs and DACs with ~10-b, 10Gs/s performance will be is the ultimate performance metric for data converters. As
required. Given the significant amount of signal processing an example, in an FMCW radar transceiver, one of the most
that is required for this application, the data converters must critical specifications is SFDR since, after processing, the
be implemented on the same SOC as the signal processing, received signals from targets show up as spurs in the ADC
which raises the critical question of “partitioning”. In many output. It is critical that spurs generated by the ADC itself
cases, the continuously improving heterogenous packaging be significantly lower than the spur from any target. Once
capabilities enable critical IP to be developed in an optimal the data converter has been verified to work in the intended
process technology for that IP and then be packaged application, then other figures of merit (FOM) like the Walden
along with other system components that have also been or Schreier FOMs can be used to compare performance.
implemented in different, but optimal, process technologies
to realize an optimal overall solution. But, as shown in the 6G Data converters for wireless communication (cellular)
small cell/CPE use case described above, there are also cases applications
when critical data converters must be developed in a digital
Cellular data converters can be roughly divided between base
process technology that is definitely less than optimal for
stations and user equipment (UE). In both cases there is a strong
mixed signal circuit performance.
desire to cover the entire band with one ADC or DAC, and this
should be a focus of future research. For the ADC, this typically
Digitally modulated radar (DMR) (e.g., PMCW) for automotive
means a bandwidth of several 100MHz, and about 4X-5X of this
radar use represents another example where the required
for the DAC. The reason the DAC has to have more BW than
digital-signal processing demands that the data converters
the channel is that PA predistortion and/or envelope tracking is
be integrated on the same die. In summary, on the one hand,
usually employed, which necessitates a wider BW DAC.
ADCs and DACs are needed that take best possible advantage
of an optimized process technology (e.g., FDSOI or SiGe
The dynamic range requirements are medium-hard, about
BiCMOS) with ultra-high speed and resolution. On the other
70-75dB/100MHz carrier. Low power and low cost (= small
hand, ultra-high speed and resolution ADCs and DACs are
area) are paramount for all UE cases and important for base-
also needed in process technologies that are mainly intended
station data converters. For the ADC converters, the trend
for digital (e.g., 5nm CMOS). When an optimal process
is moving toward RF sampling, meaning that the RF signal is
technology is available, fairly well-known architectures,
sampled directly by the ADC.
such as continuous-time sigma-delta or pipelined ADCs,
can be optimized to meet the application needs. But
As the radios are moving toward smaller and smaller nodes,
as application demands increase and especially when a
the relative cost, area, power, and speed of the digital
non-optimal process technology must be used, new and
logic improves compared the analog counterparts. Future
innovative architectures must be developed.
research could look into how to leverage this power of digital

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 111
to improve the data converters (often referred to as digitally reliability, low-jitter clock generation, and distribution. While
assisted analog). Examples include image cancellation inside the high data rate drives the issues enumerated above, the
the DAC, which would avoid expensive external filtering solutions to each will be strongly influenced by channel loss
after the DAC, as well as digital calibration of an ADC to at the specified data rate. As such, discussions of architectural
make it better tolerate component mismatches, for instance and circuit choices are typically organized around the channel
mismatches in SAR capacitor arrays. reach (a current stand-in for channel loss).

In general, the key metric for a cellular ADC is not the SNDR. One of the long-term trends is to leverage optical data
Rather, it is the ability of the ADC to process an in-band carrier transport and, ultimately, switching and processing. This is
in the presence of an out-of-band jamming signal. Similarly, mentioned here and discussed more in Chapter 6.
the objective for the DAC is often to generate a good in-band
signal while producing a minimum amount of out-of-band (i.e., Long reach
RX band) noise.
Long reach applications are characterized by very high channel
loss and unwieldy channel profiles. These features preclude
Data converter summary and key takeaway
simple linear equalizers in favor of high order, and sometimes
Data converters with extremely wide range of performance nonlinear, equalization. Current realizations have converged on
will be needed in the coming years to address the expansive complex digital equalizers, requiring ultra-high-speed ADCs3,4.
system requirements for emerging applications. Data This choice requires innovations in both the mixed-signal
converters designed in digitally centric CMOS technologies frontend and digital-equalization approaches to maintain
below 5nm will face more prevalent layout dependent effects area and energy efficiency. Highly interleaved data converters
(LDE), making high-performance data-converter design necessary to meet the required sampling rates (100GS/s
more challenging, which will require more “digitization” and to meet 200Gb/s/lane using PAM4) also drive the accuracy
innovations going forward at the system and data-converter requirements of the clock generation and distribution blocks5.
architecture levels going forward. Systems for 6G and other
advanced processing will require high resolution (>10-bit) and Looking to the future, a promising path is to make the
performance of at least 10GS/s. Given the significant amount of advancements necessary in optical links to use such links in
signal processing that will be required, data converters will need applications currently classified as long reach. Co-packaged
to be implemented in the same digital technologies and possibly optics6, powered by continued form factor and cost reductions
even integrate some of the digital frontend signal-processing in photonics, will enable the use of photonic links for long
tasks. It is expected that FoMs will be adjusted according to reach application. Minimal mixed-signal design techniques7
application imperatives. in the interface circuits will ensure energy efficiency, even
as the data rates are aggressively scaled. In the long term,
Wireline PHY interfaces and data connectivity mixed-signal design techniques could be refocused to resolve
integration issues like degraded receiver sensitivity in co-
Driving applications: Networking, storage, automotive, high-
packaged optics8,9 or modulator nonidealities due to process,
performance computing, and accelerators
voltage, and temperature (PVT) variation12. PDKs or modeling
approaches11 that enable this tight codesign, as well as
Key performance metrics: Data rate [Gb/s], reach (insertion
facilitate signal integrity and performance evaluation, will be
loss) [dB], power/energy efficiency [mW/Gb/s]/[pJ/bit], bit
key to the success of this approach.
error rate (BER), modulation type/order.

Medium/Short reach
Continually increasing aggregate bandwidth demands
for networking and accelerator applications have led to a The cost and form factor constraints may not support an
steep rise in required per-lane data rates. Multiple wireline optical solution for medium-loss channel profiles. In these
standards have announced per-lane data rates beyond circumstances, a re-evaluation of the transceiver architecture
50Gbps, with the highest currently at 224Gb/s. Following away from the digital realization will clear the path for per-lane
these trends, the per-lane data rate appears to double every data-rate expansion. Innovative mixed-signal equalizers and low-
three to four years. To meet or even improve on these data complexity digital equalizers may play a major role in keeping
rate projections requires innovative solutions to address the energy efficiency high. New approaches implemented in
challenges in I/O area and energy efficiency, circuit complexity, mixed-signal domain and centered around correlative channel

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 112
coding (or 1+αD)12-19, maximum likelihood sequence estimation algorithmic techniques, and near-zero-power processing. In
(MLSE) , and equalizers based on deep neural network
18, 19
many cases, these techniques will create extremely dynamic
(DNN)20, 21 will provide an alternative to ADC/DSP transceivers power loads that will pose new challenges to the power
in high data-rate applications. Folding in more traditional DSP management and delivery systems (See section 5.3).
techniques into the mixed-signal receiver will ensure improved
energy efficiency, even as data rates are scaled. Sensor fusion
Chapter 6 covers sensor and sensor technology, but an
Die-to-die interconnects
increasingly important part of mixed-signal processing is the
This class of wireline links will benefit from all the innovations effective combination of information from multiple sensors
needed to aggressively expand the data rates of the longer (sensor arrays) and multiple sensor types (sensor fusion) to
reach variants. The data rate and reliability limitation here provide a richer, more robust, more secure interpretation of
will have to do with the extent of advancement in packaging, the environment. From automotive systems that combine
peripheral component, and circuit scaling to fit I/O density radar, optical, and possibly lidar imaging modalities, to audio
constraints. Innovations to significantly reduce ESD size or beamforming systems that help suppress background noise,
develop a packaging approach that allows the assembly and sensor fusion is a critical technology for advanced systems and
deployment of components with less protection will be needed. often presents new challenges around design, integration, and
A redesign of the interface into a simpler RC interconnect that testing/verification.
requires no termination will also be necessary.
Security, trust, and reliability
Clocking systems
Chapter 3 covers security, and it is worth noting that sensors
Future of clocking systems and analog frontends present some special challenges as
Wireline and wireless consumer markets demand increasing “attack surfaces” but may also present some technologies that
bandwidths that are projected to reach multi-Gigabits per help systems detect and defend against intrusions—a critical
second and low-latency to support real-time control and factor in modern “zero-trust” system models.
high-definition video for mobile systems moving at greater
than 100km/hr. Wireline point-to-point links that support 3-dimensional heterogenous integration for
the wireless backhaul are now approaching 200Gbps. These mixed signal
wireline systems are facing challenges with maintaining signal
Chapter 7 covers advanced packaging, including three-
quality in lossy channels, as well as in implementing fast,
dimensional heterogeneous integration (3DHI), which is
accurate clock data recovery (CDR) schemes to prevent BER
a cross-cutting technology to significantly improve the
degradation in the communication link. In fact, both wireless
performance, size, weight, power, and cost (SWaP-C) of
and wireline are imposing similar challenges on clocking
analog microsystems used in wireless communications, power
circuits—low jitter, low skew, robust CDR, limited phase noise,
management, and electronic warfare applications. Analog
and enabling multi-phase clocking at four phases and above.
3DHI microsystems address grand challenges enabling:
High-frequency PLLs/DLLs with low jitter are an absolute
requirement for high-speed clocking for both wireless and • >100GHz wireless communications 3DHI microsystems
wireline applications, including clock generation, high-
• Fine-grain power management to significantly improve
performance applications, and low-power applications.
the energy efficiency of computing, communications,
automotive, medical, industrial, and medical systems
Power mitigation techniques
Much like their digital counterparts (see Chapter 4), mixed- Analog 3DHI microsystems employ the z-dimension to
signal systems are increasingly limited by power consumption/ tightly integrate large arrays of separately manufactured
power density/thermal management considerations. As a components, including:
result, technology progress and innovation will often be
• Wide-bandgap (compound) semiconductors for power
driven by the need to reduce power at the device, circuit,
transistors and power amplifiers, including gallium nitride
and system level. Analog techniques will have similarities
(GaN), silicon carbide (SiC), and emerging gallium oxide
and differences to the techniques highlighted in Chapter 4
(Ga2O3)
for digital circuits, but include power gating, clock gating,

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 113
• Silicon-on-insulator (SOI) for gate drivers and RF beam improved simulation/analysis tools will be needed to meet
former integrated circuits the upcoming mixed-signal circuit needs. Traditional PVT
simulation techniques for analog/mixed-signal design are
• Passive components, including resistors, inductors,
not accurate/adequate, and robust statistical simulation
capacitors, and antennas
techniques are needed.

Analog 3DHI microsystems complement digital 3DHI • Most compute is digital. Analog circuits are expected to
microsystems by addressing power delivery and thermal operate within a broader digital computing environment—
management constraints that limit system-in-package (SiP) applications, algorithms, and many hardware elements
performance. Analog and digital 3DHI microsystems have are digital. Jointly reasoning about analog circuits and
different technical requirements, solutions, and ecosystems. digital systems is challenging, as they use wildly different
Analog 3DHI microsystems require low I/O density, high behavioral models (digital logic vs. physics models) and
current density, and tight integration of compound require fundamentally different analyses to study. This
semiconductors and SOI made using mature process nodes semantic gap in behavior is also why digital EDA tools cannot
and passives in an ultra-small footprint. However, digital 3DHI easily be used to facilitate analog and mixed-signal design.
microsystems require high I/O density, low current density, and
tight integration of logic and memory semiconductors made These limitations restrict the complexity of analog circuits that
using advanced CMOS process nodes in a large body size. can be designed today and the degree to which these circuits
can be co-optimized with digital systems, applications, and
Mixed-signal design methodologies, EDA tools, algorithms. Therefore, we must invest in next-generation AMS
and IP approaches design productivity tools to fast-track analog design productivity
and enable seamless codesign across the analog-digital divide.
Analog design tools
Motivation Key future technologies

To enable efficient integration of analog computational Efficient simulation

elements into the 3D SiP systems presented in Chapter 9, we Given today’s simulation capabilities and the demands on
need new AMS design techniques and tooling. As noted in model accuracy imposed by advanced technologies, today’s
Chapter 9, analog design productivity tools lag significantly simulation-based EDA tools will not meet the needs of next-
behind digital design tooling, but emerging ML/AI techniques generation analog designs. Therefore, reducing the time
may hold promise. Present limitations affect the complexity of spent in the simulation will improve the efficiency of layout,
the analog circuits that can be engineered. verification, and optimization tools.

• Simulation-light design algorithms. We need new

Analog circuit design faces unique challenges that must be
design automation algorithms that strategically use
overcome.
computationally efficient evaluation procedures (e.g.,
• Simulation complexity. Candidate analog-circuit designs surrogate models) in place of detailed circuit simulation to
are evaluated through time-intensive circuit simulation. rapidly evaluate candidate circuit designs and reduce the
Because simulation is typically the “inner loop” for many number of simulations performed. Moreover, training these
parameter algorithms, including optimization, layout, and next-generation EDA procedures on previously developed
validation, these tools scale poorly with circuit complexity circuit designs will enable the incorporation of designer
and cannot performantly navigate large parameter and intuition into the search process.
input search spaces.
• Computationally efficient models. Today, practitioners
• Model accuracy. Analog-circuit designers rely on highly use computationally efficient, but less accurate, circuit
accurate, computationally demanding device models to models to perform large-scale, system-level simulations.
architect analog circuits. Maintaining the accuracy of these These reduced models capture a subset of behaviors in the
models is critical to developing ultra-high-frequency and transistor-level circuit and, therefore, only produce correct
deep nanoscale analog circuits and analog circuits, as these results under certain conditions. Developing analyses
circuits are highly sensitive to mismatch and layout effects. that bridge the gap between detailed, physically accurate
These challenges complicate circuit designs and leave little models and performant, reduced models is therefore critical
margin for error in simulation. For robust/safe operation, to enabling the efficient design of highly sensitive circuits.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 114
 Table 5.1: Technology timeline for analog and mixed-signal processing

Mixed
Signal Current 5 Year 10 Year 15 Year
Processing
AFFT Fast LP Freq domain Multi-channel Modulus solver P/Q (FHE High level
Correlator multiplex HS Ghz sampling related) specification creates
ADC ADC with combined analog and
Analog Computation

FFT based digital computer “at

correlator the edge” with sensor
input
ULP (3uW) VAD Implicit FFT input Analog Viterbi
equation soln. > 1GHz,
w/ digital I/O non-batch
continuous FFT
CAD for
calculation
mixed A & D
computation
Lidar and radar VAD on MEMs Sensing for Complex multi-sensors on Human-like
Sensor
Fusion

sensors mic agriculture single ICs (e.g., using MEMs) sensing

Ultrasonic (e.g., smell)
sensors
ULP Medical CT pipeline ULP medical >10 Gs/s, >10-b >100Gs/s, >100Gs/s, new high
Converters

Wide BW CTSD ADC (low power with ADC/DAC in 6-b ADC 12-b ADC/ performance, highly
Data

(radar) and area) in sub- tomography sub-5nm for 6G for adv DAC for efficient ADC/DAC
16nm support CPE/small cell ethernet cellular base architectures for IoT
stations
LR Digital XVRs LR Digital XVRs SR Digital XVRs SR AMS XVRs MR AMS Monolithic electro-
(ADCs ~ 50GS/s) (ADCs>100GS/s On-Board optics Co-packaged XVRs optics
Pluggable Pluggable optics Co-
Optics Optics packaged
Wireline PHY

optics
IM/DD Coherent IM/DD Coherent Coherent
PAM-4 16 QAM PAM-6/8
LR DSP, 1+αD signaling MLSE Equalizers DNN Equalizers Mixed-Signal techniques to Data-driven
SR Mixed-signal replace DSP impairment correction
Equalizers

4-phase 8-phase High-frequency CDR for Clocking for quantum

Clocking
Systems

clocking clocking LO generation >200Gbps circuits

CDR for
>100Gbps
micro-RNG Homomorphic Integrated Secure Quantum security,
(AMS), PUF (AMS), secure wireless manufacturing, Piracy and counterfeit IC
Security

manufacturing, security, HW obfuscation detection

Edge

side channel trojan detection IC watermarking, IC

attack in RF / AMS ICs authentication
detection
SR Mixed-signal 2.5D optical / 2.5D RF – 2.5D RF + photonics 3D 3D monolithic+
Equalizers photonics CMOS, III-V 3D RF + photonics monolithic,
Packaging
Advanced

3D RF – CMOS, Block
III-V folding,
Circuit
folding
AIB 2.0, UCIe, UCIe, BOW, UCIe-3D, ESD >2Tbps/mm2 Wireless 3D with no
Ecosystem
Chiplet
Mixed
Signal

SERDES, NVLink, for ~5V CDM D2D SERDES D2D ESD

BOW, NVLink, LIPINCON, standards
LIPINCON AIB-3D

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 115
Digital twins for verification and design automation High-voltage/High-current applications and key
Digital EDA tools have been enormously effective in verifying performance parameters
digital designs and automating digital circuit-design tasks.
Wide-bandgap power devices
Mapping analog circuit design and verification problems
into the digital domain (e.g., with digital twins) will enable Over the last 10 years, wide-bandgap devices have emerged
the development of EDA tools that capitalize on advances in as alternate technologies for Silicon in many high-voltage/
digital EDA. Second, digital embeddings of analog circuits can high-current applications. The principal materials of
be seamlessly integrated into a digital system design, enabling commercial interest today are Silicon (Si), Silicon Carbide
effective whole-system verification and co-optimization. (SiC), and Gallium Nitride (GaN), including its alloys with
Aluminum, Indium and Scandium. Currently SiC—like Si—is
New design metrics for requirements elicitation implemented as a vertical/quasi-vertical device on its own
Today’s circuit figures of merit and high-level functional substrate, while GaN is typically implement as a lateral
descriptions focus on the specification of canonical analog device on a Silicon or Sapphire substrate. SiC devices are
circuits (e.g., ADCs) that satisfy circuit-level requirements (e.g., commercially available from large manufacturers in the 650V
gain and bandwidth requirements) and optimize standard to 3.3 kV range, while commercial GaN devices are primarily
figures of merit. These are ill-suited to architecting next- rated at 650V or below. Under some device architectures,
generation, novel computational analog elements tightly both enhancement-mode and depletion-mode GaN devices
codesigned with system software and hardware. Therefore, can be integrated on the same die, which allows for relatively
new, highly flexible, functional descriptions and application- high integration levels necessary to increase the operating
specific metrics and figures of merit are needed that enable frequency of power converters. In addition, GaN can be grown
tight co-optimization of algorithms, circuits, and digital on Silicon wafers, and its device fabrication can leverage most
systems. These capabilities will enable the discovery of novel of the tools in a conventional Si CMOS fab, which significantly
analog computational elements that deliver substantiative lowers the barrier for adoption. All this work, however, has
performance benefits for the target application domain. been focused on lateral GaN transistors. For GaN to perform
in high-voltage/high-current applications, vertical devices would
New techniques, including ML approaches, offer prospects for be highly desirable. While there a few companies attempting to
progress on many of these challenges. commercialize vertical GaN, many issues with the technology
remain. Table 5.2 summarizes the applications and the driving
metrics for mega power and nano power.
5.3. Power Management,
Power Distribution, and Wide-bandgap devices complement fine-line CMOS, BCDMOS,
and SOI offerings with unique properties:
Power Electronics 1. Can increase the power density by reducing device and
Management and distribution of power is a critical analog system volume and weight by operating at high frequency.
semiconductor problem—from the macro level in the modern
2. Can operate at high efficiency, resulting in reduction of
electrical grids to the micro level where new technologies
static losses and dynamic losses.
like 3D stacking and heterogenous integration pose new
challenges in delivering power to diverse (and dynamic) loads 3. Have high temperature capability.
across the micro system. Additionally, new challenges (and
4. Are reliable.
opportunities for innovation) are presented by novel and
emerging energy-storage technologies for power systems.
Cost for lateral GaN has been dropping and becoming cost
competitive with Si because all the processes are fully
High voltage and very high voltage solid state systems are
compatible with Si and low-cost Si substrates. Costs for SiC are
enabled by developments in wide bandgap semiconductor
more expensive at the device level but reach cost parity at the
technology. New developments in materials, devices, circuits,
system level for certain applications like PV inverters.
architectures and systems are critical to a variety of emerging
applications. New applications in IOT are driving innovations in
Nano power circuit architectures and components.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 116
 Table 5.2: Application areas for power electronics and key drivers (+++ critical, ++ important, + moderate, - modest).

Power
Efficiency Voltage Process
Application Density Heavy Load Light Load
Application (reduce loss Conv. Ratio Reliability Tech.
Space (reduce Performance Performance
/ heat) (VOUT/VIN) Migration
size/weight)
Datacenter/
++ + +++ + +++ + GaN
Cloud

Performance Desktop/Server + + + + ++ + -
Computing
Laptop/Personal ++ ++ + + ++ ++ nm CMOS

Networking, etc + + + + + + -

Cell phone ++ +++ + + + ++ nm CMOS

Mobile/
Tablet + + + + ++ + nm CMOS
Communication
Displays + + + + + + SOI

IOT/Wearables / Consumer IOT + + + - - ++ nm CMOS

Biomedical Biomedical + +++ - +++ - +++ nm CMOS

Powertrain ++ ++ + +++ +++ + GaN/SiC

Battery (BMS) + ++ + +++ ++ ++ BCD/SOI

Automotive
Battery (charger) + ++ + +++ +++ - GaN/SiC

Peripheral DC-DC + + ++ +++ + - BCD/SOI

Rectifier (AC-DC) GaN BCD/

+ ++ - + + +
(e.g. low power) SOI
Grid Interface/ Inverter (DC-AC)
++ + + +++ ++ + GaN
Renewable (e.g. Solar PV)
Energy
Battery Storage + - + ++ ++ ++ -

LED Lighting ++ ++ + ++ ++ + -

Low power
+ + - - + + nm CMOS
Wireless Power (e.g. mobile/IOT)
Transmission High power
++ + + ++ ++ + -
(e.g. automotive)

Industrial Motor Drives ++ + - ++ ++ + GaN/SiC

Automation COTS DC-DC - + - ++ + + -

Key challenges moving forward are: 5. An emerging trend for the development of fully integrated
GaN power electronic circuits. Current GaN power circuits
1. Thermal- and parasitic-inductive issues or inductive-load
exist as hybrids with Si technology, with only a few examples
issues with device packaging and modules25.
of monolithic GaN circuits. Moving forward, the challenges
2. Gate drivers for wide-bandgap devices, which connect to of system on a chip (gate drivers and real-time diagnostics)
circuit architecture, EMI, overvoltage ringing, and turn-on- need to be addressed either through monolithic or
slew rate. Implementation of gate drivers is more challenging heterogeneous integration27.
in wide-bandgap technology than Si technology . 26
6. GaN materials technology for implementation of a vertical
3. A desire for GaN/MOS structures, which currently do not exist. device technology, including:

4. Necessity for continued improvement in device reliability a. development of a low-cost, low-defect, large-area substrate;
and ruggedness issues, including short-circuit and avalanche
b. continued development of ion implantation and annealing
performance.
technology, especially for P-type doping;

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 117
 c. better edge terminations for devices; and Key challenges moving forward are:

d. wafer bow as GaN on Si is scaled to 8-inch and larger 1. High efficiency over a wide dynamic range (e.g., >90%
wafers, which affects breakdown voltage and wafer efficiency at 10mW, maintaining >90% efficiency at 1nW –
handling (breakage) during fabrication. a dynamic range of 10,000,000x).

7. Limited usable device area using SiC materials technology, 2. Large load steps, such as going from nanoamps to milliamps,
despite its relative maturity, due to substrates defects requiring a good controller to respond quickly and robustly.
such as basal-plane dislocations. Further trap reduction in
3. Switch-size modulation collaboration with device
the SiC gate oxide interface for MOS devices still presents
engineering for integrated circuit-device design (leakage vs.
challenges28, as does wafer flatness.
on-current), which is much worse at nano meter scales.
8. Superjunction device architectures in both SiC and GaN
4. Optimization of size/weight/form factor and cost.
that could significantly improve the performance of power
switches and diodes beyond their unipolar limit. These are 5. Inductor-less power conversion (e.g., include switched
just starting to become available, and significant room for capacitors and piezoelectrics), especially for low-cost and
optimization exists29. ultra-small devices.

9. The development of CMOS GaN transistor technology to 6. Future types of power to potentially include biofuel cells and
significantly change power-circuit design in wide-bandgap RF signals emitted from 5G/6G/Wi-Fi base stations.
materials. However, the performance of the p-channel GaN
transistor needs to improve. Cross Reference: Chapter 4, sections 4.2.8 discusses power
conversion and distribution issues in large digital systems.
Power management and distribution
Power-circuit architectures
Power and thermal considerations are often the ultimate
limiting factor in integration for many modern semiconductor The wide range of power-electronic applications (See Table
systems. Minimizing resistive losses means distributing 5.2) motivates a number of challenges for future circuit
power at the highest practical voltage (lowering the current), architectures. Power-circuit architectures are a mature
increasing the DC-DC conversion requirements. Modern data technology that is recently getting significant attention
centers seek efficient conversion from “48 volts to core”— due to the rise of wide-bandgap devices (for high-current
future systems may look to increase the input voltage. Efforts and high-voltage applications), as well as due to increasing
to minimize system power consumption mean the loads may applications for wearable electronics utilizing nano power
become far more dynamic, as various parts of the system are (both trends discussed in section).
powered down when not in use. These challenges add to the
existing desire to provide power to the load at the optimal In the case of wide-bandgap devices, circuit architectures
voltage with maximum efficiency and minimum size and cost. need to accommodate the unique device physics of the wide
bandgaps, which result in different circuit modes. High-power
Near zero-power (nano-power) processing circuits are being developed to control individual switches
and provide current and voltage sharing for multiple devices
As mentioned in the previous section, nano power involves
in extremely high-power applications. High-power circuits
applications that support quiet and/or sleep-mode operation
are also addressing power for Data Centers. In general,
into the nanowatt regime, and yet may still consume orders
power circuits are moving to higher frequencies to allow
of magnitude more power during awake states, which
for a reduction in the size of passive components. Passive
presents an extremely dynamic load. Most applications
components for these applications are, in turn, facing
use lithium ion batteries instead of energy harvesting, but
challenges of size reduction and temperature operation.
energy harvesting is anticipated to become a larger focus
moving forward. These applications often require a dynamic
In nano-power applications (defined as exceptionally low-power
range of power and high efficiency through this dynamic
consumption—perhaps designed to operate on scavenged or
range, as battery lifetime is of paramount importance in
harvested power, e.g., implantable medical devices), circuit
such applications. In applications such as nanorobotics, total
architectures need to continue reducing inductor usage and
volume and weight is also of great importance.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 118
address the large dynamic range of power (with concurrent nano power. At high voltage and high current, the physical
high-power efficiency) that is demanded by nano-power size of the discrete elements often determines the size of the
circuits. This implies that these circuits will have more creative power supply. By increasing the operating frequency of the
use of switched capacitor and hybrid-switched capacitors. power-conversion circuity, significant size reduction is realized.
However, this increases the demands on the switching devices
Key challenges moving forward are: and power-circuit architecture. Both capacitance and inductive
elements are used as temporary energy-storage elements
1. Gate drivers requiring isolated power conversion or power
in switching power supplies. It is generally recognized (but
across floating domains. This is particularly true of wide-
often overlooked) that it is easier (from the point of view of
bandgap transistors floating at very high voltages. Powering
size) to store energy in electric fields (capacitors) as opposed
the gate drive is a challenging problem, and current
to magnetic fields. Therefore, there has been a trend toward
solutions are large, expensive, and lack efficiency. Optically
capacitive-based switching architectures. Replacement of
triggered devices or optically powered gate drivers are a
inductors by readily-integrated piezoelectric elements is an
possible approach.
interesting option. A potential future development is the use of
2. Power-circuit architecture in monolithic GaN. These radioisotope batteries for long-life small-footprint applications.
architectures will have different design parameters
compared to architectures designed using Si CMOS. In many Key challenges moving forward are:
cases, present designs reflect architectures developed in the
1. Improving the Columbic efficiency of energy-storage
1970s and present an opportunity for a fresh perspective.
elements.
3. Interfacing high-voltage circuits with nanometer CMOS (for
2. Continued development of super capacitors.
example, Si FinFETs don’t support Li ion battery voltages).
3. New materials for piezoelectric elements.
4. Determining if there are different circuit topologies better
suited for use with stacked transistors. 4. Radioisotope batteries that are able to supply continuous
power approaching 1mW/cm3 in order to become
5. Discovering the tradeoffs between circuit-transient response
commercially viable.
and regulation.

6. The complexity of achieving a normal dc voltage using flying Advanced power packaging
capacitors (because of voltage balance).
Advanced packaging is a cross-cutting topic which affects
7. Determining the tradeoffs between circuit-conversion ratio many areas of the SRC roadmap. In the power management
and efficiency. area, packing impacts the heterogenous integration of GaN
power devices with Si control circuit, as well as development
8. Interconnecting at different levels of power.
of a fully packaged power module that combines control
9. Vertical power delivery. function with thermal management and low-parasitic
inductance. Form factor is often part of the design challenge,
10. Better device models for wide bandgaps.
since power transistors, passive devices, and thermal-
11. Going below 12 V in the Data Center, which currently management solutions often dominate the physical size of
converts between 48 and 12 V. important circuits.

12. Discovering different types of energy storage elements that

Key challenges moving forward are:
are viable, such as hybrid-switched capacitor architectures or
piezo electric charge storage … hybrid resonant (as currently 1. Integration of GaN and Si.
almost all nano-power circuits use Li batteries).
2. Isolation in high-voltage and extremely high-voltage
environments.
Passive devices/energy-storage elements
3. Conduction of large and very large currents.
Passive circuit elements that implement inductance or
capacitance are playing an increasingly important role in 4. Thermal management, including thermal conductivity and
determining the size and efficiency of power-management thermal isolation.
circuits, both at high voltage and high currents, as well as for

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 119
 Table 5.3: Power Technology Timeline

Power
Management
Current 5 Year 10 Year 15 Year
and
Distribution
Power JBS SiC Increase die size Power SiC Power Higher quality gate Power MOSFET 10 100KV Power IGBT
Wide Bandgap: SiC

diodes by reduction of MOSFET at 6.5 KV oxide improve kV DC to DC 15-25 kV

defects threshold voltage Converters should be a
Power SiC More that 50% Demonstration 15kV
stability product
vertical MOSFET Increase substrate 200mm SiC IGBT for engineering
up to 3.3kV size– > 200mm wafers Goal of 2X samples Grid
improvement in Modernization
Continued defect 200mm wafers
channel mobility
reduction efforts standard
Power GaN GaN IC integration Vertical 1200V Vertical 3.3kV GaN
Wide Bandgap: GaN

diodes GaN devices devices

900V Lateral GaN
Power lateral 1200 V Lateral 1200 V Lateral GaN
200mm GaN on Si
GaN device up to GaN is a reality
650V
More than 50% 200mm Gan on Si
200mm Gan on Wafers standard
Si Wafers
Circuit Hybrid and mutli Conversion ratio Power Density
Power Circuit
Architecture

architectures level architectures 48:1

1W/mm2 at point
traditional Better device
of load
buck boost ec. models for SiC and
Conversion ratio GaN Circuit design
10:1
Circuit Improvement in Dynamic Range Dynamic Range Dynamic
architectures efficient dynamic Range
1 Million X with 10 Million X with
traditional i.e range by using
greater than greater than 80% 100 Million X
buck boost circuit topology.
70% efficiency efficiency with greater
with PWM and
Nano-Power/

Dynamic range than 80 %

Harvesting

or PFM control Power Density Hybrid architectures

1000X with greater efficiency
with efficient maximize/exploit
than 80% efficiency .1W/mm2 at
dynamic range power density in Power
point of load
of 1000X and capacitors
1W/mm2 at
greater than Power point of use
70% efficiency
.5W/mm2 at point
of use
Lithium battery Eergy density laboratory Piezoelectric 5 W/mm2 integrated First radio Next-
technology needs to improve demonstration passives. Resonant magnetics. isotope generation
Power vs Energy of Super cap electromagnetic powered materials for
Energy storage elements

Discrete Production 1 uF/

tradeoff needs for energy passives medical capacitors,
capacitors and mm2 Silicon trench
Passive Devices/

optimization storage with product magnetics,

magnetics. Laboratory capacitors
high Columbic and
Silicon trench demonstration Production
On-die MIM efficiency piezoelectrics.
capacitors.On-die of radioisotope piezoelectric
capacitors.
magnetic cores.10 Improved batteries with 1mW passives 10 W/mm2
PCB magnetics.
MHz cored Dielectrics /cm3 of continuous integrated
magnetics. power magnetics.
1 W/mm2
integrated
magnetics.
Capacitance Integrated Chip scale
Advanced Power

structures power module integration.

Packaging

integrated into for GaN

Addressing the
modules increasing
Battery impedance
functionality
issue
incorporating
thermal design

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 120
5.4 RF to THz Devices, Principles of choice-of-frequency band

Circuits, and Systems Spectral allocations are as much a geopolitical issue as a

technical one. In wireless communications, governments will
In defining a decadal plan to develop underlying technologies
likely allocate more spectrum at higher frequencies because
(IC technologies, interposers, packages, etc.) for wireless
there is more spectrum available there. The wider the
systems, we must first project what type of systems will
allocated spectrum, the greater the feasible data transmission
likely be developed in the next decade. The type of systems
rate at a given power efficiency. More complex modulation
deployed depends not only on technical factors but also on
permits faster data transmission in a given bandwidth, but the
wireless communications and imaging market growth, as well
power radiated to accomplish this increases exponentially.
as on deployment costs, policies on use of spectrum, and on
the level of propagation losses arising from partial or complete
Disadvantages for high-frequency systems include higher
beam blockage. This roadmap will seek to make projections
cost and poorer performance of the transmitter and receiver
based on likely trends, influenced by physical principles.
ICs; increased worst-case31-35 atmospheric attenuation (Figure
5.2), which reduces range; and greater probability of beam
Applications, frequency bands, and wireless equipment
blockage from objects lying between the transmitter and
receiver, including foliage and trees.
The driving applications for wireless innovation include
communications and imaging modalities—mobile and fixed
Higher carrier frequencies can theoretically make MIMO
wireless communications, automotive and other radar, lidar,
systems smaller. However, to recover the communication
and other imaging applications. Broadband wireless systems
distance, a larger array to maintain a sufficient aperture or
communicate to the wireless end-user equipment with wireless
antenna gain is needed. MIMO systems use many antennas
hubs. The hub can be connected to the main network either
to radiate multiple independent signal beams, each carrying
with optical fibers or with wireless backhaul. When the hubs
separate data. The radio spectrum is reused many times,
are closely spaced, the backhaul links will have shorter range
supporting a larger capacity in a given allocated bandwidth.
and perhaps lower data capacity—this is called wireless
fronthaul. Such links need fronthaul and backhaul transceivers.
Figure 5.2: Worst-case atmospheric attenuation
Fundamentally, the need to quickly move large amounts
of data requires broader channels and new techniques to
increase the effective b/s/Hz. Next-generation cellular
channels may want to push to 500MHz-1GHz, with other
wireless data application seeking even wider channels,
while new waveforms and multiplexing methods are being
researched in parallel. The search for wider channels pushes
users to ever higher frequency bands, where range becomes
a significant challenge. Antenna array systems are helping
to address some of these challenges, but users will ultimately
adopt spectrum sharing and conditional access techniques to
more completely exploit the easier-to-use lower bands.

The frequency bands30 for wireless communications systems,

now or in the future, include sub-6 GHz, 28 GHz, and 39 GHz.
Other frequency bands, either already allocated for wireless
communications and/or radar or of interest, include ~57-64
GHz, 71-86 GHz, ~90-95 GHz, ~135-175 GHz, and 210-310
GHz. Systems may be driven to exploit fragmented frequency
allocations across multiple bands.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 121
In MIMO hubs, the array width tends to vary as the inverse of carrier frequencies are naturally the same as those used
frequency. In MIMO backhaul and endpoint links, the MIMO for wireless communication, such as Wi-Fi, 5G FR1/2/, UWB,
array length tends to vary as the inverse square root of etc. Looking forward, E band and D band are promising.
frequency. As a general trend, higher frequencies may make The wider bandwidth and smaller antenna size will enhance
high-capacity MIMO systems more compact and, therefore, both range and angular resolution. Due to a larger free-
more practical. space path loss (FSPL), a higher antenna gain is necessary to
generate sufficient EIRP (Effective Isotropic Radiated Power).
In automotive radar, shorter wavelengths provide better Note that while performance may be worse with lower
angular resolution for given radar antenna array area. frequency ranges, and a linear antenna array may be the only
Improved angular resolution allows for better discrimination configuration possible for handheld devices (limiting both
of important adjacent objects, e.g., a motorcyclist stopped the angular resolution and the spatial information with only
under a bridge, or some pedestrians standing beside a roadway 2D point cloud), there are still useful applications, such as
while others may be standing on it. Higher carrier frequencies presence detection.
are therefore desirable if the ICs and packages work well and
cost little. Although increasing the carrier frequency increases Using automotive radar as an example, 24, 77, and 79 GHz
the worst-case atmospheric attenuation, automotive radar bands have been allocated by most countries. Although
need not work over very long range. For example, when a car automotive radar need not support extremely long range,
travels at 67 MPH, a 300-meter range radar will provide 10 the line-of-sight propagation loss is twice of that for
seconds warning of a hazard. Given such short range, even the communication in dB scale (i.e., 40 vs 20 dB/dec). The small
attenuation from extreme rain can be accommodated. Further, radar cross section (RCS) at 300m away, for instance, can
radar range can be allowed to decrease in extreme rain, as a make the detection very challenging. Therefore, increased
car cannot be safely controlled if driven at 67 MPH in extreme atmospheric attenuation is still a substantial disadvantage.
rain, even if the radar lets the driver see ahead. More antenna elements to maintain a sufficient aperture is
required. The adverse effect is that the beamwidth is smaller,
As a general observation, given greater atmospheric impacting the corner-radar performance. Higher-frequency
attenuation, high-frequency systems generally support shorter systems do offer better angular resolution, but ICs and
propagation ranges Water vapor attenuation in hot, humid packages perform less well (and/or are more expensive).
weather becomes extreme above 300 GHz. Systems operating Currently, 77 and 79 GHz band automotive radar is widely
above 300 GHz must be extremely short range, avoid places sold, and 140 GHz automotive radar is readily feasible in
in the world where there is hot, humid weather, or operate at low-cost production CMOS and high-volume SiGe BiCMOS
higher altitudes, avoiding the air and its moisture. technologies. Approximately 200 GHz appears to be the
upper limit of low-cost mass-market IC technologies today.
High-frequency wireless signals are more easily blocked. At
a distance R from a receiver, an object of area ~ΔR , the 1st Given the potential for further improved angular resolution,
Fresnel zone area, will block most of the power. Such blockage automotive radar systems above 200 GHz, perhaps as high
can occur with discrete object, or from the collective effects of as 300 GHz, may be of commercial interest. This will require
many small ones, e.g., beam blockage due to leaves on a tree. use of semiconductor technologies having higher power-gain
cutoff frequencies (500-600 GHz) than the ~300 GHz of current
Choice of carrier frequency for radio sensing high-volume CMOS and SiGe BiCMOS technologies. Power
gain cutoff frequencies of 700 GHz (SiGe HBT), 1100 GHz (InP
Radio sensing/imaging can utilize a wide range of frequencies. HBT), and 1500 GHz (InP HEMT) have been demonstrated
Available bandwidth versus application requirements are in low-volume laboratory and/or pilot line processes. Mass
major concerns. For instance, consumer devices would enjoy production of automotive radar systems above 200 GHz would
unlicensed bands, such as ISM, UWB, and automotive radar require bringing one of these materials into high-volume,
frequency bands. Even if micro-Doppler signatures, which high-yield, low-cost manufacturing. Heterogeneous integration
are less dependent of the bandwidth, were used as the technologies could be a favorable solution because it would
main detection mechanism, range detection is still often permit such transceivers to be constructed using only very
needed as part of the sensing system. Therefore, carrier small dies of the advanced high-frequency ICs, with the vast
frequencies at 2.4 GHz and higher are generally desired. majority of the IC area in VLSI CMOS.
For integrated communication and sensing (aka ICAS), the

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 122
Choice of carrier frequency for wireless then c.a. 10Gb/s or less. Systems at 75, 140, 210, or even 280
communications GHz can support 100-1000 Gb/s data rates, but >700 m range
will be difficult to support. Beam blockage is less problematic
With the advent of 5G systems, cell phone handsets with 28 in such systems, as the propagation path is known. Fixed
GHz and 39 GHz transceivers are available to the public. Yet, wireless endpoint will use hardware and deployments similar
during 2020-2022, worldwide adoption of such hardware has to fronthaul, but the needed capacity per endpoint links will be
been slow. This may simply reflect slow development of high- smaller than that of backhaul. Carrier frequencies at 28, 39, 75,
capacity wireless markets. It may also reflect fundamental and perhaps even 140 GHz are feasible. Even the 75 GHz band
difficulties with high-frequency propagation, resulting in should be sufficient to provide >50 Gb/s/link, sufficient for the
further challenges for mobility and the network operations. next decade for many fixed destinations.
The roadmap must acknowledge this uncertainty.
IC technologies: Process and devices
Mobile wireless endpoint connects the hub to the cell phone
Today, RF-optimized mass production CMOS VLSI technologies
handset. The path of such links varies greatly as users move,
provide 300 GHz power-gain cutoff frequencies.
hence path loss from blockage is likely. This is the application
where the high path losses and high blockage probabilities of • CMOS transistor noise figure and CMOS transistor RF
high-frequency systems pose the greatest difficulty. Though output power is sufficient to support high-performance
commercial deployment of 28 GHz and 39 GHz systems is RF/wireless mobile transceivers below 100 GHz. For hub
ongoing, it’s possible that future mobile wireless endpoint and backhaul transceivers operating below 100 GHz, the
links may migrate to lower frequencies, between the present CMOS chipset may be supplemented with GaN HEMT
sub-6 GHz and 28 GHz bands, to minimize path losses and beam or SiGe HBT power amplifiers. Between 100-160 GHz,
blockage probability. To provide the needed capacity with CMOS IC performance is sufficient to shorter-range links.
lower carrier frequencies, hence lower bandwidth, massive Combining CMOS with a InP HBT, SiGe HBT, or GaN HEMT
MIMO will be required. Thus, one path for mobile wireless power amplifier, or with an InP HEMT low-noise amplifier,
endpoint in the next decade is microwave massive MIMO. On will permit links of greater range or higher capacity.
the other hand, slow 28 GHz and 39 GHz adoption may simply
• Mass production SiGe BiCMOS have cutoff frequencies
reflect slow growth of the wireless data transmission market.
similar to CMOS, but higher performance SiGe HBTs have
If so, as capacity at 28 GHz and 39 GHz is exhausted, in the next
been reported as laboratory demonstrations or as pilot
decade mobile wireless endpoint may migrate to 70-75 GHz,
production technologies. As these transition to mass
and even possibly 135-145 GHz.
production, higher-frequency systems will become feasible
in Si technologies.
For mobile endpoint, the choice of carrier frequency strongly
depends on market growth. If the information density (Gb/s/ • Currently established in low-volume pilot production,
km2) is low, wireless hubs should be widely spaced to keep InP HBT technology readily enables 100-300 GHz
infrastructure costs low. If the information density is high, power amplifiers of record power and efficiency. If
cellular areas, hence hub spacings, will be reduced to lower the the market demand can support the cost of doing so,
total data capacity per hub. The propagation distance between production versions of InP HBT technology might emerge.
hub and user then becomes smaller, and the high atmospheric Heterogenous integration, e.g., small InP die on Si, may
attenuation and the greater probability of beam blockage enable low cost.
become less serious limitations of high-frequency systems.
• Established in low-volume pilot production for military and
scientific applications, InP HEMT technology is by far the
Wireless backhaul and fronthaul connect hubs to the internet
lowest noise figure transistor technology at any frequency.
backbone. Lower-frequency systems provide greater range,
As with InP HBT, there is presently a gap between cost and
while higher-frequency systems can provide greater capacity,
compelling need, but HI or other new technologies might
both from more available spectrum and from being able to
help bring the cost down.
support MIMO in an array of smaller dimensions. Given the
frequency dependence of rain attenuation noted above, • Below 100 GHz, GaN HEMT technology provides record
systems providing more than 1 km range will, in the next RF output power and efficiency. There are R&D efforts
decade, most likely use <35 GHz carrier frequencies, with range worldwide to extend and improve the performance of GaN
increasing as the frequency deceases. Feasible data rates are HEMT as an efficient power technology above 100 GHz.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 123
• Carbon nanotube and other emerging technologies will demands on package integration density and thermal density
continue to be explored. These technologies offer some are somewhat relaxed.
tempting fundamental physical properties, but have also
posed some significant manufacturing challenges that stand Circuit technologies
as obstacles to commercial exploitation.
While the need to exploit new/enhanced device technologies
continues to be an important part of pushing to higher-
Package technologies
frequency bands and bandwidth, innovation in circuit
RF systems offer special packaging challenges, including technology continues to be a critical piece of advanced RF
the need to interface to or integrate antennae (increasingly systems. Classic RF circuits achieved performance through
in the form of linear or two-dimensional arrays), integrate narrowband/heterodyne techniques that provide good signal
chips of disparate technologies, and handle significant selectivity, but fixed the system to a particular frequency or
thermal challenges associated with high-power transmit band (or required cumbersome tuning technology). Circuit
devices. Package connectivity must provide low/tuned advances, including linearization technique, have led to more
impedances consistent with the frequencies being handled. broadband multi-carrier or even multi-band approaches,
providing much greater system agility.
IC-interposer interfaces using flip-chip bonds with Cu studs
• Amplifier and frequency synthesizer topologies. The
have been developed for connecting microprocessors to
performance bottlenecks of many RF systems include the
memory and other digital ICs. The high-density Cu-stud flip-
transmit-power amplifier, the receive-antenna amplifier (LNA,
chip technology performs adequately even over DC-300 GHz
or low-noise amplifier), and the frequency synthesizer (LO,
(although enhancements are desirable at the upper end of this
or local oscillator). Systems will continue to seek the best
range). Therefore, this provides an excellent baseline package
possible devices (see previous section) but will also continue
technology for wireless systems.
to exploit circuit innovations to improve system performance.
Doherty techniques have been used to enhance transmit
To support efficient antennas and low-loss transmission lines,
amplifier linearity at higher power, and digitally enhanced
packages for wireless systems—particularly at 30-300 GHz—also
techniques are becoming more common (noted below).
require at least one plane of low-dielectric-loss materials. The
package’s dielectric materials must have either high thermal • Direct RF sampling/synthesis circuits and architectures.
conductivity to support heat removal from ICs and power As noted in this section’s opening comments, applications
amplifier transistors, or it must provide dense arrays of thermal requirements are calling for more bandwidth and greater
vias for heat removal. More aggressive technologies, such as system flexibility, pushing radio architectures to move
package-level phase-change thermal solution may be needed. from traditional narrowband/superheterodyne approaches
Generally, the package must simultaneously support high to broadband/multi-channel/multicarrier/multi-band
densities, low-dielectric loss, and high thermal conductivity. approaches. This trend has been expanding for the last 40
years and will continue to grow as the need to maximize the
In the next decade, many wireless systems will integrate use/reuse of scarce wireless spectrum intensifies. These
CMOS transmitter and receiver ICs, closely integrated with broadband techniques present great challenges to all
very-small-scale non-CMOS (SiGe HBT, InP HBT, InP HEMT, aspects of the system, from LNAs and power amplifiers to
GaN HEMT) power amplifier and low-noise amplifier ICs. The data converters and digital processors.
package must support dense integration of these, adequate
• “Digitally Assisted” RF (DARF). Although this has been
thermal management, and appropriate high-frequency
progressing for 30 years, and progress continues as
connections. Package design is made more difficult in higher-
processors become more sophisticated, recent and future
frequency arrays, where RF channels and antennas are often
advances will include ever more sophisticated compensation
placed at a half-wavelength lateral (horizontal) pitch. In fixed-
of non-linearities and greater exploitation of ML techniques.
infrastructure transceivers, such as those used for hubs and
There are other DARF/DAA technologies emerging, such
fronthaul and backhaul transceivers, the required range of
as amplifier efficiency improvements using Digital Doherty
vertical beamsteering is considerably less than 180 degrees.
techniques. The quadrature channels required to implement
Although the array element lateral pitch may be constrained
such techniques may benefit from analog-assisted Doherty
to half-wavelength, the array element vertical pitch may be
approaches, shifting some of the processing out of the
several wavelengths. With larger area available per RF channel,
digital domain.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 124
System/Architecture Technologies also be used to better manage the RF beams or to reduce
the power consumption. With embedded intelligence and
System and architectural evolution complement circuit
capability of the meta-surfaces, data modulation and simplified
advances. New waveforms, coding, multiplexing techniques,
transceivers may be achieved to improve beamforming
etc., are emerging to support higher data rate, lower latency,
performance and RF chain-energy efficiency.
better spectrum efficiency, and more flexibilities. For instance,
MIMO and beamforming systems exploit the use of multiple
Related technologies: Radio processors
transceiver elements to overcome many of the propagation
Signal processing of large-array systems with GHz bandwidth
challenges presented by higher frequency signals. As noted in
and low-latency requirements creates some unique and
the opening discussions, this opens up more spectrum reuse
extreme processing demands. In many cases, the processors
and higher bandwidths for greater communication capability
may need to be optimized for these requirements and may be
and spatial resolution in imaging systems, but it presents
distinct from the processors required for conventional high-
multiple challenges (including the need to exponentially
performance computing or even GPU/AI workloads. In addition
reduce the size, power, and cost of each individual transceiver
to the work noted in Chapter 4, it’s vital to track developments
element for the system to remain viable.) Furthermore, as the
for high-performance GHz bandwidth systems.
non-terrestrial network (NTN) is being aggressively deployed,
terrestrial networks (TN) and NTN need to be harmonized to • Multi-channel (MIMO) wireless hubs and backhaul links
form 3D networks. New development for spectrum-sharing/ require signal processing to separate the many high-speed
collaboration and interference avoidance are needed. signal streams. Recent trends suggest that this MIMO
decoding can be by fast digital processing, often at low
The architecture tradeoffs are multi-dimensioned. resolution36,37. For such digital MIMO processors, the data
rate per channel and the number of channels must be
• Beamforming: analog, digital, hybrid, digital low resolution
extended. Such efforts are eased by the continued scaling
• Arrays: distributed, sparse, very large, and small arrays of VLSI CMOS process technologies.

• Array calibration, compensation, and synchronization: phase, • Extremely complicated networks, including adaptive
true-time-delay, narrow band, wide band, algorithms, etc. networks and spectrum-sharing systems, requires the
emergence if the RIC (radio intelligence controller).
• Security: resilience to jammers for wake-up radios, PHY
security with multiple potential techniques, etc. • Radio processing has started to embrace ML/AI techniques,
and this is expected to continue to expand.
• Protocol: seamless handoff across the whole 3D networks

Extremely low-power wireless systems

Multi-band and spectrum-sharing/cognitive-radio architectures
Many applications (e.g., wearable/implantable healthcare
will drive systems to wider RF bandwidths, pushing large
devices) are struggling with higher than desired peak powers,
amounts of the radio functionality into the digital domain.
even in Bluetooth low energy for short-range applications. On
the other end of the spectrum, there is a realization that certain
Special technologies: Antennas, meta-surfaces, etc.
standards like narrowband internet of things (NB-IoT) are not
As previously noted, higher RF frequency signaling may
really providing low-power solutions. Smart-city deployments,
introduce significant challenges in terms of atmospheric
as an example, often require much larger than desired batteries
attenuation and blocking/scattering of signals. One possible
(or grid power). The working life of wearable and implantable
solution is to exploit materials whose RF characteristics
devices that may be critical for healthcare, safety, and
(including transmission and reflection) may be controlled
consumer applications is often determined by a combination
and dynamical-adjusted to provide adjustable antennas or
of battery capacity and functional power consumption. In
reflective surfaces. Precursors to this technology have been
many applications, the wireless communications functionality
around for some time—generally referenced as “reflect
may represent a significant portion of the power budget. As
arrays” and explored as both passive and active (with gain)
a result, a push for ultra-low-power wireless communications
implementations. However, with new emerging use cases
mechanisms is expected to continue.
under dense deployment for NLOS conditions, the interference
from adjacent users, multi-path reception, etc., creates many
Power optimization techniques have been discussed
new technical challenges to be addressed for this technology
throughout this roadmap—wireless systems will leverage
to move to the commercial mainstream. A meta-surface may
these techniques. In particular, they are likely to exploit

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 125
a tiered operation and “adaptive performance” methods, adaptively optimize its performance and power consumption
including an interference-resilient wake-up radio with at any given situation. This can save orders of magnitude of
sufficient intelligence to combat security challenges. power compared to systems designed and operating at the
Moreover, it would incorporate a scalable system that can “worst case” operating point.

Table 5.4: RF/mm Wave Technology Timeline

RF/mmWave/THz Current 5 Year 10 Year 15 Year

Channel BW: up to
Channel BW: <100MHz
Spectral Utilization: 500MHz-1GHz Channel BW: >5GHz
Wireless Comms Bands: sub 6GHz, 28GHz,
Bands: 8-20GHz, 57-64GHz, Bands 135-175GHz
39GHz
71-86GHz, 90-95GHz
Spectral Utilization: Auto radar: 24GHz, 77GHz,
140 GHz 200-300GHz
Imaging 79GHz
PAE > 30 % to 140 GHz PAE > 30% to 250 GHz
Power Amps PAE > 30% to ~90 GHz
PAE > 60% to xx GHz PAE > 60% to xx GHz.

LNA F < 4 dB to ~90 GHz F < 4 dB to ~140 GHz F < 4 dB to ~250 GHz

1st generation multi-band 1st generation cognitive

Radio Architecture MIMO, M-MIMO
radios radio/spectrum sharing

arrays: 64 elements, 4 arrays: 256 elements, arrays: 1024 elements,

Antenna arrays
simultaneous signal beams 32 simultaneous beams 128 simultaneous beams
1st gen HI Arrays
2nd gen HI arrays
Advanced RF packaging Stacked Antenna-in-
LTCC substrates
package modules
Analog, digital and hybrid Low res/very low res
Radio Processing
beamforming digital beam processing

Extremely low power

Bluetooth low energy
wireless links

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Contributors
Dave Robertson (Analog Devices) – Chair Neelakantan Gopalan (Synopsys) Tawfiq Musah (Ohio State University)

Farhana Sheikh (Intel) – Vice Chair Deukhyoun Heo (Washington State Tomas Palacios (MIT)
University)
Mark Rodwell (UC Santa Barbara) – Vice Chair Marcus Pan (SRC)
Austin Hickman (Soctera)
Michael Spencer (Morgan State Christian Peters (Bosch
University) – Vice Chair Chih-Ming Hung (MediaTek)
Elena Peterson (PNNL)
Kaveh Ahadi (NCSU) Harish K. Krishnamurthy (Intel)
Gabriel M. Rebeiz (UC San Diego)
Zeshan Ahmad (Texas Instruments) Hanh-Phuc Le (UC San Diego)
Jason Stauth (Dartmouth College)
Jon Chisum (University of Notre Dame) Paul Lesso (Cirrus Logic)
Sharad Vidyarthy (Analog Devices)
Allan Cox (Silicon Intervention) Martin Mallinson (Silicon Intervention)
Michael Vincent (NXP)
Patrick Fay (University of Notre Dame) Babu Mandava (3D Glass Solutions)
Jun Xiao (UW-Madison)
Jeb Flemming (3D Glass Solutions) Lennart Mathe (Qualcomm)

Doug Garrity (NXP) Patrick Mercier (UC San Diego)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 126
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(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 128
Chapter 6

Photonics and MEMS

6.1. Introduction While co-packaged optical transceivers are making data
transmission more efficient, optical sensors and actuators are
With transistor 2D scaling slowing and 2.5D/3D packaging playing a growing role in data collection and manipulation.
technologies maturing, the development of optical These sensors and actuators are crucial in products such as
transceivers and interconnects built with integrated TVs, headlights, projectors, and DNA analysis chips, as well as
photonics technology, fabricated in CMOS fabs, and using for optical switching in data sensors and wearable heartrate
advanced IC packaging technologies starts to become a plus oxygen sensors. Many of these sensors are built with
more critical technology innovation. The optical transceivers Microelectromechanical systems (MEMS) technology. MEMS
that are co-located with data processing (computing) devices and fabrication technologies are also used to tune,
and memory chips in the same package are referred to as modulate, or adjust alignments in optical devices like tunable
Co-packaged Optics or CPO. The dies that contain active filters, lasers, and optical fibers, which enable new products
photonics devices and related photonics circuits are called such as near-infrared (NIR) materials analysis scanners. In
PICs (Photonics Integrated Circuits). These PICs convert addition, the combination of MEMS and PICs maturing at the
electrical signals to optical signals and transfer data in the same time will enable products not possible before.
optical domain between packages and/or among computing
cores and memories within the package. The most important Miniaturization of sensors has driven a revolution in
value propositions of CPO are increased bandwidth density telehealth, allowing diagnostics to be done in remote areas
and enhanced energy efficiency—two critical metrics or at home, providing less invasive surgical alternatives,
driven by the ever-growing demand in computing power and enabling implantable, ingestible, or wearable sensors
and communications bandwidth. This demand is especially and neural probes. Miniature sensors have also fostered
impacted by the rapid growth and implementation of the use of digital twins of individuals, so that doctors can
sophisticated AI and ML accelerators and compute clusters practice surgery by simulation and provide more accurate
that are pushing the boundaries of interconnect bandwidth, visualizations of the body to allow better diagnoses.
power efficiency, and lower latency from chip-scale to
large-scale systems comprised of thousands of GPUs, Sensors are also enabling innovations in smart homes, smart
CPUs, and memory ICs. cities, and advanced manufacturing facilities. New chemical

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 129
sensors allow the detection of gases for monitoring pollution encompasses hardware, algorithms, and software either near
and air quality in buildings. The Internet of Things (IoT) is or on the edge devices. For example, it might reside on a
based on the availability of small-form-factor, low-power sensor at the edge of the IoT data management and compute
sensors. Sensors will also continue to find critical applications solution. Typically, consuming ~1mW power, ML inferences on
in structural health monitoring and predictive maintenance, sensor data are made locally. As TinyML grows over the next
defense, and aviation to name but a few. In the next decade, decade by proliferation within IoT, critical areas of interest
the market for handheld and wearable gadgets is expected to will include low-power wake-up circuits; non-volatile memory
continue its rapid growth. Moreover, AI-powered robotics and integrated with silicon built using advanced Si nodes; and ML
autonomous vehicles will continue to find widespread use. All algorithms that effectively utilize limited memory/compute
these applications will require more sophisticated, reliable, resources with milliwatt power budgets.
and lower-cost sensors with high-bandwidth interconnects.
Silicon photonics holds the promise of extending frequency
and bandwidth for multiple applications, from sensing and
6.2. Sensors for the Next interconnects to communications and computing. Advanced

Decade optical sensors for health/medical sensing, including

blood sugar detection, blood pressure, and heart disease
The mobile phone economy is driven largely by cost, size, markers, as well as sensors for automotive applications
performance, and bandwidth. Robust sensor design is critical such as LiDAR, present important growth opportunities.
to the success of the handset’s GPS, gyroscopes, as well as A significant issue for these sensors is to achieve the
accelerometers, pressure sensors, magnetometers, optical accuracy and reliability of competing solutions.
image stabilization, microphones, and fingerprint sensing.
Sensitivity and accuracy of the sensors grew tenfold in the Further development of optical-phased arrays and gratings
past five years, while power, cost, and size decreased to a are needed to deliver true solid-state beam steering for ADAS
fifth in that time. These trends are expected to continue. (Advanced driver assistance systems) LiDAR systems. Solid-state
beam steering will lower cost, improve reliability, and shrink the
The fusion of physics and AI in on-device computing has made LiDAR scanning systems, all of which are necessary to achieve
designs in MEMS-based products better. The integration of mass production of SAE level 3 and above autonomous vehicles.
these sensors makes for seamless execution of activities
such as navigation dead-reckoning, stability control, impact The silicon-level integration of emitters with OPA (Optical-
detection, adaptive lighting, image stabilization, and traction phased arrays)/grating elements and detectors with point-
control. Better sensor performance implies higher Signal-to- cloud processing is also needed for ADAS LiDAR systems in
Noise Ratio (SNR), higher dynamic range, and sub-milliwatt mass-produced vehicles. The integration of these elements
power consumption. may be best achieved through codesign of the elements and
wafer-level hybrid-bonding or similar approaches.
Sensors with additional functionality are also needed. For
instance, Si-integrated components with a smaller bandgap Sensor data is often trusted without further security checks by
than that of Si, which work in shortwave infrared (SWIR), are the systems that use it. Therefore, manipulating the physical
required to enable eye-safe long-range LiDAR (Light Detection phenomena that the sensor is designed to interpret can
And Ranging) with high resolution. It is also desirable to cause an undesired course of action. For example, the MEMS
encapsulate these sensors in ultra-small packages. Flexible accelerometer on a smartphone can be tricked to measure
packaging is another emerging area important to wearables steps by simply playing a YouTube video with embedded
and medical applications. Sensors and actuators with associated sounds that cannot be easily heard. Information can even be
signal processing (sensor fusion) are a key focus of the Decadal communicated using this method. For instance, with a laser
Plan chapter on New Trajectories for Analog Electronics. shining through a window, a perpetrator can inject commands
into a voice-controlled system. Therefore, the security aspect
Computation and smart processing close to the sensor of integrated MEMS devices is a challenge that needs to be
are vital for energy efficiency and latency, while hardware addressed to prevent nefarious data tampering. MEMS can
and software co-optimization is an important vector for also be part of security solutions, as MEMS devices can be
collaboration. TinyML (www.tinyml.org) is another rapidly used as part of a physical security mechanism for protecting
growing area of interest for sensors and actuators. The field circuits from tampering.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 130
Trends in sensor manufacturing and design include: Challenges remain in integration and power/area-efficient
optical-electrical-optical conversion and interfaces. These
• The replacement of crystal oscillators by CMOS-compatible
challenges must be addressed to broaden the application of
MEMS-based resonators to allow for new architectures,
this technology.
improved performance, and the removal of off-chip passive
components.

• The use of piezoelectric MEMS sensors and actuators in 6.3. Communication

applications such as handheld ultrasounds, as well as
Integrated photonics will bring massive improvements to the
improved and miniaturized speakers and microphones.
communications infrastructure. In the next five years, it is
• A full suite of technologies that can deliver cheaper sensors expected that the channel-symbol rate will easily exceed 100
in high volumes using new lower-cost materials and Gigabaud and that transceiver modules with aggregated
fabrication techniques, while creating sensors with high bandwidth of 3.2 to 6.4 Tbits/s will be demonstrated in
accuracy for critical tasks such as GPS-denied navigation. integrated photonics for optical fiber communication.
Relentless requirements for increased bandwidth and power
• Sensors in clothing and fabrics to create new categories in
efficiency will drive architectural transition from pluggable
fashion, competing with phone, ring, body-patch, and watch-
optics to co-packaged optics (CPO) within Data Centers,
based sensors. Many innovations here also have military
pushing the transition from copper cables to optical fibers
uses. Fabric-based sensors are driving new requirements on
for even shorter reaches (under 1 meter).
interconnect, reliability, and durability.

• MEMS-enabling advances in quantum computing, as MEMS It must be emphasized that the tremendous bandwidth of
structures are used to enable quantum bits to communicate the optical fiber cannot be fully exploited (to achieve orders
with the outside world. of magnitude increase in bandwidth density with photonics)
without the use of Dense Wavelength Division Multiplexing
Unlike many electronics, sensors are made with a variety of (DWDM, or equivalent multiplexing methods) to place multiple
fabrication processes that are often specific to application or optical channels on a single fiber. Successful implementation
sensor type. Depending on the sensor, it may need to be open of DWDM or coherent technology on the PIC also opens the
to sense its environment while also protected from unwanted possibility of trading off channel data rate with the number of
environmental influences. Some sensors are better suited to channels for a given bandwidth per fiber. Such tradeoffs can
hermetic packaging. Key factors that provide for the unique bring benefit to energy efficiency and system cost. In the years
packaging needs of specific sensor architectures include to come, as the bandwidth density of photonics interconnects
the packaging of sensors made with disparate fabrication increases and their use becomes more prevalent, it will become
technologies, as well as the combination of flexible and rigid more critical to reduce the overall optical system’s energy, cost
sensors on flexible substrates. A competing trend is that, per bit, and latency (especially for AI/ML applications). Co-
for some applications, standardization of sensor packaging packaging optics close to ASICs and other compute ICs using
solutions is beginning to occur, which allows for a more short, low-loss channels will help enable some of these power
efficient supply chain. efficiencies and bandwidth enhancements, enabling low-
power electrical-optical conversion and high-bandwidth data
Integration of sensors with associated electronics can be done transmission over large-scale systems.
in multiple ways. Sensors can be built on the same chip as
electronics in a special compatible process, created on top/ Analog-photonic links are currently used to simplify mm-wave
below the CMOS as a postprocess, or combined as separate node IC architectures that can enable scaling up to more than
chips. MEMS can also be built out of the CMOS stack, and 1000 antennas per chip. They have also greatly increased
some researchers are even using finfet structures as the basis energy savings in the process and are vastly more energy
for sensing elements. Separating the chips, or post-processing, efficient than the digital links in the signal chain.
allows the use of advanced CMOS nodes and optimized
MEMS processes. These different integration strategies have There is also a large window of the electromagnetic spectrum
implications for packaging, materials choice, fabrication, and that remains untapped for communication applications.
assembly. For the foreseeable future, each of these strategies Technology innovations are needed to leverage this vast
will have a niche. untapped spectrum. Innovative semiconductor technologies,

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 131
such as SOI/SiGe-based photonics, VCSELs, microLEDs, bandwidth, energy, and cost requirements of computing and
avalanche photodiodes, and InP-based PICs, will provide communications.
advanced process platforms to enable many of these future
improvements in bandwidth and power. AI accelerators and neuromorphic computing are other
exciting areas that are driving higher compression ratios, with
In the area of MEMS, optical switches are replacing OEO a great potential to improve energy efficiency in conjunction
switching. MEMS-based tunable filters and capacitors, RF with advanced 2.5D/3D package integration. Light-based AI
switches, and the aforementioned MEMS resonators are accelerators are being explored, and increased investments in this
allowing new architectures and higher levels of integration, area could place additional demands on the PIC roadmap. There
thus reducing footprints and simplifying packaging. These are also increased R&D investments in Si-Photonics for Quantum
novel components are unleashing a whole new era of creativity computing, which requires new materials and processes.
in communications circuit and system design. Using MEMS
for tunability, alignment, and calibration of communications MEMS-based products require more onboard computation
components also leads to improved specifications. to produce ever-smarter sensors. MEMS manufacturers have
“moved up the food chain” by going beyond supplying the
raw sensors outputs. Typical MEMS sensors today supply
6.4. Computing and Memory intelligent actions or other processed data. This is part of the
trend toward intelligent edge processing. The architecture of
Photonics presents significant opportunities to address
how computing is combined with sensing is changing rapidly,
power and bandwidth bottlenecks in continued scaling of
influencing CMOS-MEMS integration and advanced packaging.
data movement for high-performance and Data Center
computing systems. Novel high-speed, low-power transceivers,
light sources, waveguides/modulators, and photodetectors
represent some of the essential building blocks for integrated
6.5. New Materials and
photonics—a field where sustainable dimensional scalability Processes for Photonics and
remains a key challenge. Photonics offers opportunities for low-
power, high-speed I/Os and photonic interconnect fabric. Also,
MEMS
photonic devices have been shown to enable certain classes of To enable higher performance and higher-integration density,
mathematical operations, such as matrix vector multiplication. innovative semiconductor process platforms include SOI/
Ge-based photonics; integration of III-V materials on Si wafers
By enabling photonics integration in proximity to processors through epitaxial growth, wafer/die bonding, or laser-in-cavity
(CPU/GPU/FPGAs/ASICs) and the link from processors to attachment for the light source, modulators, and detectors; and
memory, the enormous bandwidth and low-loss advantages active devices based on physical effects (Plasmonics, Graphene)
of optical transmission as compared to copper could be other than the plasma dispersion effect. Lithium Niobate and
leveraged to improve bandwidth density by >100X and Barium Titanate thin films for hybrid integration are enablers for
energy efficiency by >10X, as well as to extend package-level high-frequency modulation, while photonics wire bonds for laser-
performance systemwide. package interconnects leveraging 3D printing are other areas to
examine further. High-bandwidth, lower-transmission loss, and
Optical links offer power-efficient and low-latency interconnect lower-power optical chip-to-chip interconnects are also expected
to enable disaggregation across network, compute, and to require advances in embedded waveguide in substrates/PCB.
memory. This will utilize the aspects of co-packaged optics It is important to ensure a low-cost, high-reliability photonics
with ASIC/CPU/GPU and use optical communication standards bill of materials that maintains stable performance over time
for linking between compute and memory across racks in and wide temperature ranges, while also maintaining low
hyperscale Data Centers. thermal hysteresis and low-loss characteristics, thus requiring
low overall energy consumption.
Work scope could be directed to address roadmap metrics
following Technical Areas 1–3 in DARPA’s PIPES Program For certain sensors and actuators that require CMOS-
https://research-vp.tau.ac.il/sites/resauth.tau.ac.il/files/ compatible scaling while increasing inertial sensor
DARPA-Photonics_for_Scalability_Amend_1_HR001119S0004. performance and RF filter power-handling, new materials
pdf and IPSR https://photonicsmanufacturing.org to meet the such as Tungsten or other high-atomic-mass metals need to

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 132
be explored to reduce the overall footprint. CMOS-compatible to facilitate controlled motion to generate, move, and detect
platforms based on aluminum nitride are being explored as sound. Due to the large number of cycles the devices must
well. New piezoelectric and phase-change memory transducers endure, a key feature for MEMS materials is that they deform
with much higher force density and linearity are also being predictably yet do not fatigue. Optical sensor/actuator materials
investigated. These novel materials for sensors and actuators that are prized include those that create flat, reflective surfaces,
will in turn trigger the innovation in packaging materials and do not readily deform, and have the appropriate optical
techniques that require temperature and humidity control. properties. In RF MEMS switches, the development of reliable
contact materials continues to be important.
Two important material drivers for inertial sensors are the
ability to prevent the mechanical devices from sticking to There are several emerging next-generation materials of
the substrate and material sets that have a good CTE match interest for Photonics and MEMS applications that should be
to prevent unwanted bending and stress—especially from considered for volume-manufacturing productization. There
packaging. Improved and low-cost getter material and anti-wear, is a need for precursor characterization work to integrate
anti-stiction, anti-corrosion, and charge-eliminating coatings these materials into semiconductor manufacturing and
are also required for these sensors. For chemical sensors, develop automated frontend manufacturing equipment to
materials requirements are to facilitate chemical reactions in a apply or remove these materials. Some examples are listed in
repeatable and stable manner. Some of the needs for acoustic Table 6.1 below.
sensor/actuator materials, such as microphones/speakers, are

Table 6.1: New materials for photonics and MEMS/sensing

Technologies/ Process developed and Additional development Major development

Materials ready for manufacturing work needed effort needed for HVM

Doped & undoped polysilicon and New Interferometer architectures and

Integrated InP lasers
single crystal Silicon electro-optical materials
Silicon nitride & low stress Silicon Enhanced FOM waveguides (lower loss, New waveguide and cladding materials
Nitride superior line edge roughness) for lower losses and cost
Integration of additional high refractive
Silicon oxide
index materials
Low thermal application materials
Silicon
Low Hydrogen oxides & nitrides enhancement such as extremely low
Photonics
temperature applied Silicon nitride
High quality Ge Photodiodes Low cost materials
Mach-Zehnder interferometers
(MZI) & modulators (MZM), heaters,
waveguides
Integrated TIAs and rich PDKs
Doped & updoped polysilicon and Improved gettering material and low
Reduce or eliminate need for getterers
single crystal Silicon cost gettering technology
Low stress materials enhancements
Silicon Nitride & low stress Silicon
such as extremely low stress applied Low cost materials
Nitride
Silicon Nitride
Low thermal application materials
Motion Silicon oxide enhancements such as extremely low
Sensors temperature applied Silicon Nitride
Silicon On Insulator, (SOI) substrates Low CTE mismatch materials sets
Advanced coatings—anti-stiction, anti-
Anti-stiction layers
wear, anti-corrosition, charge eliminating
Coating Enhancements—deposition of
Tribological (anti-wear) layers
coatings near STP

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 133
 Table 6.1: New materials for photonics and MEMS/sensing (cont.)

Technologies/ Process developed and Additional development Major development

Materials ready for manufacturing work needed effort needed for HVM

Magnetoelastic materials Polyaniline Boron-doped Silo nanowires

Potentiometric materials, (Pt / Pt02; W/ Nanoparticles for specific gas attraction
W203, Pb/PbO2 with increased adsorption sites
Highly effective sticking coefficeint
ZnO for NH3 sensors
Chemical materials
Sensors AI electrodes

Nickel or Tungsten heater

Aluminum, Alumina

Pt, TiO2
New Higher piezoelectric coefficient
Doped & undoped polysilicon and Piezoelectrics that do not fatigue at
nanomaterials in the form of nanowire/
single crystal Silicon low temperatures
nanobelt/nano shell or polymetric films
Piezoelectrics with high piezoelectric
Silicon nitride coefficient and high electromechanical
coupling coefficient
Pb-free piezoelectrics such as KNN (K,
Acoustic Sensors/ Silicon oxide
Na) Nb03
Actuators
Layer thickness increase in the range of
Piezoelectrics such as AIN, SiNx, PZT,
5-50um that are manufacturable in high
BSPT
volume
Development of magnetostrictive
actuator materials
Development of low power
electroresistive materials
Thin film layers for adhesion promotion
Au, Pt, Pd, Ti electrodes Low power electrets
and diffusion for mirror metals
Silicon, optical glass, ARC coatings Layers do not change metal over
substrates and protective layers operating temperature range
Better homogeneity as depositied
Glass to metal bonding in packaging
LiNiO3 material
NiCr strain gauges using Cu, Au, Si3N4,
Pb-free optical glass
Optical Sensors/ SiO2
Actuators and SAW and BAW filters—LitAO3, Low vapor pressure materials for
Acoustic Filters BaSrTiO3 piezoelectrics optical sensors
Piezoelectrics that do not fatigue at
FBAR filters—ZnO, AIN materials
low temperatures
Pb-free piezoelectrics such as KNN
(K,Na) NbO3
Layer thickness increase in the range of
5-50um that are manufacturable in high
volume
PMUT (Piezoelectric Micromachined
Doped AIN or new piezoelectric New more robust and less lossy contact
Ultrasonic Transducers)—PZT, AIN, SiN,
materials with higher PE coefficient materials
Silicon
RF MEMS and PMUT—PE materials with higher
CMUT (Capacitive Micromachined
Ultrasonic performance FOMs (stability,
Ultrasonic Transducer)—SiN, Silicon
Transducers reproducibility, homogeneity, cost)
CMUT—low(er) stress materials with
MEMS switches—contact materials—
enhanced thickness uniformity across
Au, Ag, Pt, Pd, Ru, Rh, Os
the substrate

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 134
6.6. State of the Art / Product MEMS products incorporate advances in sensor/actuator
fabrication technology, materials, and design. Some examples
Examples of emerging products are:

The effort to bring photonics into the IC package has already • MEMS-based speakers
begun. Some initial products showing the transition from
• Chemical sensors that can sense multiple species
standalone transceivers to CPO or optical engines designed
for CPO were demonstrated in recent years. • Ultrasound arrays for handheld imaging instruments

• BAW devices that can be integrated with CMOS

Examples of these early-stage CPO products are given in
figures 6.1 and 6.2. Figure 6.1 shows a Ranovus Odin optical
An example of a state-of-the-art MEMS product is given in
transceiver, operating at 896Gbps, integrated on the same
figure 6.3. It shows an eXo Imaging low-voltage pMUT array
package substrate with a Versal FPGA from AMD/Xilinx. It
chip: Exo Silicon. Exo Silicon blends the proven imaging
was demonstrated at the Optical Fiber Communication (OFC)
excellence of piezoelectric crystals with the affordability
conference in 2022. Figure 6.2 depicts Ayar Labs’ TeraPHY optical
of silicon. Each chip contains 4096 individually-controlled
transceivers integrated with a data processing IC. These TeraPHY
pMUTs with large bandwidth, unparalleled sensitivity, and
operate in 8-λ WDM, (Wavelength Division Multaplexing), which
the capability to deliver ultra-wide fields of view up to 150
is supported by the 8-λ light source – the SuperNova.
degrees. Exo’s silicon architecture allows for rapid imaging
quality evolution and delivers real-time AI capabilities
State-of-the-art MEMS products combine multiple sensors
where every frame can be analyzed to guide the user to an
with electronics that offer high-level outputs that have been
immediate answer. Looking into the future, the promise of
processed by onboard low-power electronics that often
pMUT technology will enable powerful 3D and, potentially, 4D
incorporate AI and advanced calibration. Products from
imaging. Caregivers will be able to see even better into their
Bosch, ST, Invensense, Analog Devices, Texas Instruments,
patients to make faster diagnoses.
etc., come with APIs ready to insert in systems. Emerging

Figure 6.1: AMD Xilinx Versal ACAP co-packaged with Ranovus’ Odin™ Analog-Drive CPO 2.0

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 135
 Figure 6.2: Ayar Labs’ TeraPHY optical transceiver and SuperNova laser source

Figure 6.3: Exo Imaging’s pMUT Chip

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 136
6.7. Limitations with Current drivers often dictate a custom process. As result, a MEMS
device fabrication process and its associated packaging must
Technology be codesigned. Another limiting factor is that there is no
primitive element as in CMOS—that is, the transistor. Test
Optical communication is nothing new. Since the
methods are often unique to a sensor’s working principle
manufacturing of optical fibers started to mature and III-V-
or application, so the test and assembly infrastructure,
based light emitters and detectors became available over half
ecosystem, and supply chain are more complex than for
century ago, optical transceivers have been playing a rapidly
electronics. Much progress has been made in these areas,
expanding role in transporting data over long distances—
but these issues still limit the widespread adoption of MEMS
thanks to the low loss, low dispersion, and wide bandwidth of
technology, making time-to-market an issue for MEMS-based
the glass fiber. Technology advancement and diversification
products. As the MEMS market continues its rapid growth,
allowed the costs to plummet, enabling optical transceiver
more suppliers will create MEMS offerings and the situation
proliferation in access and client-side applications. Meanwhile,
will improve.
the advent of DWDM technology and the Erbium-doped
fiber amplifier (EDFA) in the 1990s revolutionized the long-
haul network and laid the foundation of the information
superhighway. Over the years, the optical transceivers
6.8. Challenges, Future Needs,
morphed from custom-designed equipment to board- and Possible solutions
mounted modules and then to a plethora of multisource
Technical and supply chain challenges in several areas need
agreement-specified small form factor (SFF) pluggables. These
to be addressed for communication, computing, and memory
standalone pluggable transceivers play an indispensable role
applications:
in today’s Data Centers.
• Photonics IC (PIC) performance (200G/Lambda +), yield,
However, with continued growth in data volume and the manufacturability, and cost
computing power of the data processing ICs, the standalone
• Mass production of low-cost DWDM III-V laser light sources
transceivers can quickly become a bottleneck for high-
(especially in the O & C-bands) for silicon photonics
bandwidth data transfer. The total number of transceivers
that can be mounted on the faceplate may not provide • DFB (Distributed FeedBack) QDOT and other laser sourcing
enough bandwidth for the data processing unit or data options, performance, wall-plug efficiency, and cost
switch on the line card. As the data rate increases to 100
• Non-hermetic lasers with high performance at elevated
Gigabaud and beyond, the losses from copper traces between
ambient temperatures to be suitable for an intra-IC
the SerDes of the IC and the optical transceiver data input
packaging environment
pins become challenging from a signal-integrity standpoint.
CPO thus presents a good alternative in this case, as well • Integrated high-power lasers with high yield and
as a compelling option to break this physical barrier while reliability
continuing to reduce overall system power and cost.
• Hybrid integration of lasing materials

Bringing optical transceivers on the same package resolves • Edge-coupled and vertical-coupled fiber attach passive/
the signal-integrity problem by eliminating long copper traces active schemes, fiber pitch scaling, and cost
across the line card with shorter, lower-loss interconnects and
• Fiber assembly processes—low coupling loss, high
potentially direct-drive optics. However, to truly overcome the
throughput, high yield
bandwidth-density bottleneck, we likely need to introduce
DWDM technology for long-haul/long-reach transceivers while • Ribbonization of fibers with high fiber count/density and
maintaining the short-reach co-packaged optical-Ioss regimes. reduced cladding-diameter fiber arrays

• Fiber-array interconnect/termination hardware

Because MEMS devices typically require custom processes,
development and standardization
it’s hard to create a highly standardized CMOS-like platform.
A magnetic sensor, for example, may require materials that • Fiber management for Co-packaged Optics (CPO) –
are not needed for inertial sensors. Some manufacturers have high-density fiber (high fiber count) per package and
attempted to offer fabrication processes that make multiple ribbonized fibers
sensor types on the same die, but cost and performance

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 137
• Advanced heterogeneous packaging, including 3D TSV to CMOS and multi-sensor integration
enable high-bandwidth density, high SI (Signal Integrity),
• Transition from stacked, wire-bonded sensors must
and low interconnect power
continue to occur using new packaging methods for
• Optical bus architectures for processor-processor and greater heterogeneous integration
processor-memory access
Sensor design and fabrication improvements
• Low-cost light sources for optical interconnects
• Inertial sensors improvement to navigation-grade through
• Thermal tunability and junction-temperature management
the use of calibration in the field, multiple sensors, and/or
• Design-for-test (DFT) and Design-for-manufacturability (DFM) combination with other non-MEMS sensors

• Stable and viable PIC, lasers, and fiber integration supply • Improved design and fabrication methods, as well as
chain and ecosystem enablement process window enhancements to compensate for
fabrication non-idealities
• Standards for modeling photonics circuits for ecosystem
enablement • MEMS-based energy harvesters must increase
in transducer conversion % power output to be
Technical and supply chain challenges in several areas need to competitive with solar and thermo-electric devices
be addressed for sensors/actuators applications:
• Continued development of lower power and near-zero
power sensors to meet energy requirements
CAD
• Optical glucose sensors must become more accurate to
• Nonlinear reduced-order modeling of sensors/actuators
compete with needle-based electro-chemical sensors
• Codesign of MEMS (sensor/electronics and packaging)
• Accuracy of paper and plastic sensors must improve to
• PDK (Process Design Kits) with material properties in all compete with silicon-based sensors
relevant physical domains
• Continued work on atomic clock technology to replace
large components
Materials

• Characterization of new materials in all relevant physical

domains

• Materials synthesis tools to discover and optimize

materials with desired properties

• Characterization of materials under bending and

stretching, especially for wearables

Standards

• Standards for materials properties on bending and

stretching

• Sensor performance FOM standards

• Reliability and test standards for emerging technologies

Workforce development

• Training of students in multiple physics fields needed for

MEMS (e.g, mechanics and electronics)

• Training to allow bachelor’s and master’s students to

participate more fully in MEMS and photonics design, as
was done for VLSI

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 138
Contributors
Chuan Xie (AMD) – Chair Anthony Hoffman (University of Notre Bassam Saadany (Si-Ware Systems)
Dame)
Mary Ann Maher (SoftMEMS) – Vice Chair Shafi Saiyed (Analog Devices)
Jennifer Hollingsworth (LANL)
Guy Eristoff (Tower Semiconductor) – Umit Sami (Memcus)
Vice Chair Vladan Jancovic (Northrop Grumman)
Rajinder Sandhu (Northrop Grumman)
Farrokh Ayazi (Georgia Tech) Jason Kawasaki (UW-Madison)
Ravi Shenoy (Qualcomm)
Juthika Basak (Nokia) Omer Khayam (Google)
Pooya Tadayon (Intel)
Kris Bertness (NIST) Lionel C. Kimerling (MIT)
Mert Torunbalci (Broadcom)
Sunil Bhave (Purdue University) Sanjay Krishna (Oregon State University)
Joris van Campenhout (IMEC)
Mike Burkland (Raytheon) Gilles Lamant (Cadence)
Jaime Viegas (Khalifa University)
Benson Chan (SUNY Binghamton) Babu Mandava (3D Glass Solutions)
Ying Wang (UW-Madison)
Brion Cline (Lumoniq) Varughese Mathew (NXP)
Tiwei Wei (Purdue University)
Bob Conner (3D Glass Solutions) James Pond (Ansys)
Dana Weinstein (Purdue University)
Jeb Flemming (3D Glass Solutions) Steven Ralph (Georgia Tech)
Jim Wieser (Texas Instruments)
Siddhartha Ghosh (Northrop Grumman) Suresh Ramalingam (AMD)
Jun Xiao (UW-Madison)
Jason Gorman (NIST) Sandeep Razdan (Cisco)
Jie Xue (Cisco)
Mitchell Heins (Synopsys) Dave Robertson (Analog Devices)
Todd Younkin (SRC)
Chris Hinkle (University of Notre Dame) Stefan Rusu (TSMC)
Zongfu Yu (UW-Madison)

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 139
Chapter 7

Advanced Packaging and

Heterogeneous Integration
7.1. Introduction
Information and Communication Technologies (ICTs) are the • Radically new memory and storage solutions
source of exponential increase in data that must be moved,
• Hardware to address emerging security challenges in highly
stored, computed, communicated, and secured. Traditional
interconnected systems
semiconductor technologies that rely on feature-size
reduction (dimensional scaling) are reaching their physical • Artificial intelligence (AI)
limits. Significant challenges remain in scaling up system
1
• Exponential growth in energy consumption by general
performance as the industry moves to double transistor
purpose computing
energy efficiency along with transistor scaling. Progress to
new technology nodes has slowed to more than the two-
The energy consumption is doubling every three years
year technology cadence. Increasingly, the need is becoming
and outpacing the efficiency improvements achieved by
critical for “More than Moore” Heterogeneous Integration
dimensional scaling, requiring new computing paradigms.
(HI) alongside “More Moore” traditional transistor scaling to
Thus, the broad goals addressed by this chapter are:
achieve cost-effective Systems in Package (SiPs). HI will be
fundamental to cost- and power-efficient implementations
of next-generation computing and communication systems. Grand Goal
Advanced packaging through heterogeneous integration To discover computing paradigms/architectures
will be critical as it “…provides an alternative avenue for with a radically new computing trajectory,
innovation in density and size of products”2. Moreover, “just as demonstrating > 1,000,000x improvement in
Moore’s law led the advancement of the global semiconductor energy efficiency.
industry over the past 55 years, heterogeneous integration is
and will be the key technology direction going forward.”3 Chapter Goal

Advancements in HI technologies are necessary to meet the Develop technologies for integrating analog
anticipated seismic shifts1 in ICT, including: and digital systems, including neuromorphic and
quantum computing, sensing, photonics, and
• Analog hardware required to generate smarter world- wireless communication.
machine interfaces

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 140
The scope of this chapter on Advanced Packaging and The system-integration challenge extends beyond codesign
Heterogeneous Integration includes (but is not limited to): of chip-package8. It includes package materials selection,
process development for interconnect pitch scaling, and
• Chip-package architectures and codesign
thermal solution design, all while meeting the reliability and
• Next-generation Interconnects manufacturing yield goals. These in turn require sophisticated
hotspot, as well as defect metrologies, test, and simulation that
• Power delivery and thermal management
enable a fundamental understanding of system performance
• Materials and reliability. Finally, novel materials are the foundation for
innovations in interconnects, high density substrates, heat
• Substrates
dissipation, and development of emerging devices.
• Assembly and test

• Performance and process modeling and model validation

7.2. Chip Packaging
• Reliability
Architectures and Codesign
Cross-cutting activities under advanced packaging include: The demands on bandwidth, latency, and energy efficiency
are ever increasing in AI, high-performance computing, high-
• Energy efficiency and sustainability
definition sensing, and other emerging applications. Although
• Supply chain: materials, chemicals, substrates recent advances in monolithic chip design address the above
challenges, the scaling trends still lag behind the demands. In
• Manufacturing process and performance metrology
this context, technological innovations beyond a monolithic
• Security and privacy chip, especially 2.5D/3D heterogeneous integration at
the macro and micro levels, are vital to enabling future
• Design modeling test and standards
ICT systems with various types of chiplets and bringing
significant performance and cost benefits to microelectronic
In general, different applications require domain-specific
designs. (Trends in advanced packaging architecture and their
architectures and appropriate system integration strategies to
implication for interconnects are described in Section 7.3). Such
efficiently achieve performance, power, area, and cost (PPAC)
a paradigm shift will drive new innovations in chiplet design
tradeoffs while ensuring signal and power integrity, power
encapsulated as intellectual property (IP), heterogeneous
conversion and delivery, testability, and security. Possible
architectures, on-chip/on-package networks, and reliable
solution strategies for system integration include horizontal
system integration (Figure 7.1).
integration of separately manufactured components into a
higher-level SiP,4 three-dimensional (3D) stacking of separate
Some challenges and research needs include:
chiplets, and the sophisticated layered fabrication of logic
and memory in a single, monolithically integrated System- Design IPs for HI
on-Chip5 (SoC). SiP architectural and physical design requires
Chiplets and their signaling interface bring a new silicon
high-fidelity as well as high-efficiency modeling tools and
module into the microelectronic ecosystem, with high
techniques including those based on machine learning.
bandwidth, high-area utilization, and low cost. They open a
new technical and business model of IP reuse, allowing
Progression toward high-density 3D system integration will
different functional macros to be flexibly produced
improve bandwidth density and energy efficiency.6 Horizontal
without the limitations of processing. Such a change
and vertical interconnect pitch scaling, as well as next-
requires design capabilities to define the physical cores and
generation interconnects, are critical approaches to achieving
chiplet-to-chiplet interface, as well as hardware-software
high-bandwidth density and energy efficiency. Given that the I/O
codesign to categorize reusable IP modules.
bandwidth will scale proportionally to the scaling of compute
cores, with an accompanying exponential growth in package
Heterogeneous Architecture
pin counts and I/O power consumption, alternative innovations
in optical interconnects that promise high-bandwidth density, A tight collaboration between chiplet and package designs is
energy efficiency, and reach are generally necessary. 7
vitally important throughout the entire design cycle, including
design tools, models, and workflows. System architects must

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 141
 Figure 7.1: The workflow of chip-package codesign (RTL = register-transfer level;
APR = automatic place and route; PDK = process design kit; BIST = built-in self-test).

be involved early in the design process to analyze the system interaction among various components keeps increasing in
and packages, partition the design into various chiplets, and 2.5D/3D integration, reliability assessment needs to shift
assess necessary tradeoffs in computing, data movement and from the current empirical/statistical method for each
fabrication cost. Design and verification tools at this stage, individual module to the construction of physical reliability
such as SystemVerilog, need to incorporate the package models that describe their correlation at the product level.
design and planning knowledge to support the codesign
workflow. This represents a significant revision to today’s
separated ASIC and package design process. Furthermore, 7.3. Next-generation
early predictive analysis of the HI system is essential to
minimize the iteration cost between architecture/micro-
Interconnects
architecture definition and design implementation. It is well recognized that the cost advantage of shrinking the
die using finer transistor nodes (below 20 nm) is no longer
Synthesis Tools for a HI System obvious. This is where a new approach is necessary, which is to
disaggregate a monolithic die into smaller cells, or chiplets. To
To achieve chip-package codesign, it is necessary to consider
enable functional scaling through HI of device chiplets and
packaging at each step of the synthesis flow, including
passive components, the substrate must transition from
architecture definition, RTL design, placement and routing,
a chip carrier to an integration platform. Driving attributes
verification, and timing/power analysis. The new set of tools
for this integration platform need new advanced packaging
further needs to have a smooth interface among themselves
methods to achieve these fundamental requirements, including:
and support future chiplet design kits. Unique challenges
of HI synthesis include timing analysis for the chiplet-to- 1. Performance Optimization: Enables selecting the optimal
chiplet interface, thermal/mechanical stress analysis, and silicon process node for each IP block/chiplet.
power delivery and integrity of various components.
2. Product customization: Enables customization of each
product by selecting chiplet combinations that provide
Test and Reliability
optimal performance.
A heterogeneous system contains multiple components that
3. Cost Reduction: Enables lower cost due to higher yields for
have significantly different electrical, mechanical, and thermal
individual chiplets compared to monolithic SOCs.
properties. Future testing of the heterogeneous system
needs to provide sufficient modularity to address the specific
The proliferation of chiplets is expected to continue as the
test method for each component, with balance of coverage,
industry drives toward higher performance and lower-power
complexity, and cost. Self-testing, such as built-in self-testing
solutions that are customized for each application. Next-
(BIST), is a preferred solution, but requires more research on
generation packaging needs to support this explosion in
joint testing of multiple functions. As the thermal/mechanical

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 142
 Figure 7.2: Trend which shows the transition from organic to 2D packaging using Si interposer to ultimate 3D chiplet integration9.

heterogeneous integration by enabling interconnects that The HI roadmap for interconnecting chiplets and achieving
accommodate very fine pitch I/O die (< 10 µm pitch) and very these future high-performance requirements is shown Table
fine lines/spaces (sub 1 µm L/S) circuitry. Figure 7.2 shows 7.1. To achieve the future needs for the Si interposer, it will be
the trend toward 3D chiplet integration9 to achieve two necessary to have the capability to produce a higher number
fundamental performance requirements, including (1) higher of buildup layers on the topside, as well as multi-layered
bandwidth measured in terms of IO/mm and IO/mm2 and (2) RDL layers on the backside. The substrate thickness will also
higher efficiency measured in terms of pJ/b. likely need to decrease from 100 µm to 50 µm or lower. For

Table 7.1: Roadmap technology development needs to enable future Heterogeneous Integration.

HI
2022 2023 2024 2025 2026 2030 2035
Tech.

2-3 layers of Up to 4 layers Up to 4 layers of Up to 5 layers of Up to 5 layers of Up to 6 layers of Up to 7 layers

>=1 µm L/S of <1 µm L/S <1 µm L/S topside <1µm L/S topside <1µm L/S topside <1µm L/S topside of <1 µm L/S
topside Cu topside Cu Cu Damascene, Cu Damascene, Cu Damascene, Cu Damascene, topside Cu
Damascene, Damascene, Integrated MIM integrated integrated integrated Damascene,
Data Converters

1 layer of 1 layer of capacitors, up to 2 MIM caps and MIM caps and MIM caps and integrated
backside RDL backside RDL layers of backside resistors, up resistors, up resistors, up MIM caps and
>=10 µm L/S, >= 10 µm L/S, RDL >= 10 µm L/S, to 2 layers of to 2 layers of to 3 layers of resistors, up
10 µm x 100 µm 10 µm x 100 µm 10 µm x 100 µm backside RDL >= backside RDL >= backside RDL >= to 3 layers of
TSVs. TSVs. TSVs. 7 µm L/S, 10 µm x 4 µm L/S, 10 µm x 4 µm L/S, 10 µm x backside RDL >=
100 µm or 5 µm x 100 µm or 5 µm x 100 µm or 5 µm x 2 µm L/S, 10 µm x
50 µm TSVs 50 µm TSVs 50 µm TSVs 100 µm or 5 µm x
50 µm TSVs
Wafer Level Wafer Level Wafer Level 1.8 Wafer 1.4 µm L/S. Wafer 1.3 µm L/S. Wafer <1 µm L/S. HVM Panel <1 µm
Fan-out
Recon

5 µm L/S for 2 µm L/S for µm L/S. Sub 100 Start Panel Level. Start Panel Level. Start Panel Level. L/S
buildup layers. buildup layers. µm molded core.

Solder Solder D2W Hybrid D2W Hybrid D2D Hybrid D2D (sub-micron D2D (sub micrron
Assembly

(5 µm pitch) (1 µm pitch). (1 µm pitch). Die pitch). pitch) on Organic

stacking. carriers (e.g. FO
packages).

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 143
the Reconstituted Fan-out technology, the major technology The increase in power rails due to increased core count has
driver will be producing L/S that are sub 1 µm for both the added complexity to the problem of delivering power to the
topside and backside buildup layers. For both HI technologies microprocessors. Another factor that poses additional power
it will be necessary to accommodate die with I/O pad pitches delivery challenge is the current trend of scaling Thermal
< 10 µm. This is when assembly technology will transition Design Power (TDP) to feed the increasing number of cores.
from conventional solder methods to hybrid bonding. Microprocessors in these high-power segments will draw
Future development efforts need to focus on die-to-wafer currents in excess of 1000 A in the near future. When it comes
(D2W) and die-to-die (D2D) hybrid bonding to meet the future to lower-power mobile processors, the primary emphasis has
performance and cost objectives. been on reducing the overall form factor of the device and
maximizing battery life. As a result, the area occupied by the

7.4. Power Delivery and microprocessor, the memory, and the voltage regulators has
been forced to shrink to make room for a bigger battery. In
Thermal Management addition, the push for thinner devices has meant that the
height of the microprocessor and power delivery components,
Power delivery challenges
such as inductors and capacitors, have all had to shrink.
Microprocessors have undergone a significant evolution
in complexity and capability from their introduction in the Power delivery solutions
early 1970s to the present day. The exponential increase
Integrated Voltage Regulators (IVRs) have emerged as
in microprocessor performance and cost can be attributed
a key solution vector to address several of the power
to the semiconductor industry’s adherence to Moore’s law,
delivery challenges discussed earlier. IVRs are broadly
which posits that the transistor count in a chip will double
defined as solutions that incorporate the final stage of voltage
every two years. The traditional scaling approach based on
regulation on the package or the die. IVR options have been
the template laid out by Robert Dennard was very effective
increasing in popularity and have been implemented on a
until the early 2000s in keeping the power density constant
number of commercial microprocessors. The drive to minimize
even as the transistors got progressively smaller with
power consumption through fine-grain power management
each generation. However, as the transistor feature size
has resulted in a large number of power rails. It is not practical
approached atomic dimensions, sub-threshold leakage
to have tens of voltage regulators on the platform due to a
became a problem. As a result, process engineers had
lack of platform-level resources. It is much more efficient to
to resort to alternative methods through innovations in
use the finite resources to have a small number of robust
materials and transistor structure to achieve the necessary
platform-level voltage regulators, which can deliver the
area scaling to keep pace with Moore’s law.
input power to the various integrated voltage regulators
on the package or the die. The other factor that is driving
While the non-traditional scaling methods have been mostly
the push for IVR is the steady growth in processor power
successful in scaling the transistor area while improving
levels, especially in Data Center CPUs and GPUs. As the power
performance, they were not as effective in reducing power.
levels go up, the routing losses in the power delivery network
The power density of microprocessors started to go up
can have significant impact on the overall system efficiency.
with the breakdown of Dennard scaling in the early 2000s.
IVRs can address this problem by bringing power to the
Furthermore, while Dennard scaling provided a means to
processor at a higher voltage. This reduces the current
reduce the gate delay, scaling the interconnect dimensions
through the power delivery network and minimizes the
did not translate to a reduction in the RC interconnect
routing losses in the PD network. At high power levels, the
delay. As the interconnect delay approached a significant
reduction in routing losses is more than enough to offset the
fraction of the clock period, it became another bottleneck
conversion losses introduced by the IVR.
to increasing the processor frequency. While architectural
improvements resulted in an improvement in the instructions
IVRs can be broadly classified based on their topologies. The
per clock (IPC), this was not enough to overcome the lack of
simplest on-die power delivery solution is a power gate switch.
frequency scaling. This has resulted in a slowdown in single-
Power gates are used to turn off the power to inactive circuits
core performance scaling. As the single-core performance
to minimize their leakage power consumption. A common
leveled off, microprocessor architects resorted to the use of
application for power gates is in delivering power to multiple
multiple cores and parallelizing the workloads to maximize
cores using a single platform-level power supply. The biggest
performance.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 144
downside of power gates is their inability to regulate the output More recently, new switched capacitor-based hybrid
voltage. Linear or low-dropout (LDO) regulators address this topologies have been introduced to work around these
drawback by including a control loop in their design. LDOs are drawbacks. Hybrid schemes based on buck regulators and
relatively easy to implement on die as well, due to the absence linear regulators have also been implemented. In order to
of an energy storage element. However, LDOs are usually limited generate a scalable number of on-die power domains with
to applications where the input voltage is close to the output fewer inductors, single-inductor-multiple-output (SIMO)
voltage. Hence, they are not good candidates for high-power regulators augmented with linear voltage regulators for
rails where the motivation for using an IVR is to minimize routing transient management have been implemented.
losses by bringing in power at a significantly higher voltage.
The future power delivery requirements for advanced
The switching regulators are better suited for IVR packaging are listed below in Table 7.2.
implementations that require a higher input voltage.
Switching voltage regulators use an energy storage element Thermal management challenges
to achieve high-efficiency voltage conversion. The energy
Understanding the future roadmap needs for tackling the
storage element in a buck regulator is an inductor, while a
thermal challenges of advanced packaging and heterogeneous
switched capacitor voltage regulator (SCVR) uses a capacitor
integration requires first looking back at historical architectural
as its energy-storage element. As capacitors typically have a
trends. In early high-performance computing applications,
higher energy-storage density than inductors, it is possible
Moore’s Law transistor scaling and product architecture
to design high-efficiency compact SCVRs. However, simple
choices aiming for improved performance led to the first
SCVRs suffer from poor regulation, as they are best suited
focus of thermals toward tackling both high-power density
for fixed ratio conversion from input to output and often
(owing to higher frequency transistor operation and process
suffer from poor efficiency when the input-to-output voltage
scaling) along with tackling higher total-package powers. This
deviates significantly from the optimal ratio.

Table 7.2: Power delivery requirements

Power delivery

> 2023 > 2028 2033 and +

Ingredients

On-die MIM Cap Density: > 100 nF/sqmm On-die MIM Cap Density: > 500 nF/sqmm On-die MIM Cap Density: > 1 uF/sqmm
Capacitors
DTC/MLCC Cap Density: > 1 µF/sqmm DTC Cap Density: > 5 µF/sqmm DTC Cap Density: > 10 µF/sqmm
Wafer Level 5um L/S for buildup layers.
Inductors
High Frequency Inductors (10-100 MHz) on Package
VR 2V IVR on Package 5V IVR (LDMOS, GaN) on Package 12-48 V IVR on Package (GaN)
Technology 12-48 V VR on MB (LDMOS) 48 V VR on MB (GaN)

Metrologies

Passive Characterization of passive capacitors under typical use conditions (bias voltage, temperature)
characterization Small signal and large signal characterization of inductors under typical use conditions (bias current, temperature)
Measurement of impedance seen by the on-die load as a function of frequency (DC to 1 GHz)
Active Voltage droop response to different current steps to assess non-linear transient response
characterization Streaming on-die voltage monitors to accurately measure voltage as a function of time at different sense points on die
Measurement of loop gain of voltage regulators to assess performance and stability of the compensator.

Modeling

On-die 3DIC EDA tools to run on-die IR drop EDA tools to run 3DIC simulations for 3DIC simulations to assess > 5 die stacks
simulations simulations for 2-die stack 2-4 die stacks
Full wave 3D model of section of a Full wave model of entire package Full wave solvers to assess package + MB
Package & package.
2.5D solvers to assess MB
board modeling
2.5D solvers to assess MB

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 145
unsustainable trend was broken in the early 2000s thanks to system heat sink with the package thermal design (and often
architectural improvements such as a multi-core architecture and with the specific workload in mind). This was first seen in the
increased focus on instructions per clock cycle. With multi-core mobile space where the location, size, and direction of heat
architectures, the focus was on using the power of Moore’s Law pipes within a laptop thermal solution needed to account for
to deliver additional cores for computing performance and on package core floorplan. This need is expected to grow as 3D
parallel instruction. This era also saw the first movements toward integration and advanced packaging continues to increase and
heterogeneous integration of IPs like memory controllers, thermal solutions at the system level improves.
graphics, etc. In recent years, this trend has accelerated owing to
5. As per-layer silicon thickness decreases in 3D packages,
advanced packaging techniques which allow a disparate number
the level of lateral spreading of hot spots is substantially
of chiplets, power delivery elements, memory blocks, etc., to be
decreased. This creates increased levels of effective power
integrated at the package level—often into a 3D heterogeneous
(thermal) density as the heat leaves the package, as well as an
package. Recent products have included over 100 billion
increased sensitivity to thermal defects within a package. For
transistors with 47 active compute tiles across five different
example, when silicon thickness decreases from 700 µm to 100
process nodes integrated into a single package.
µm, the critical defect size in the thermal interface in contact
with the package decreases correspondingly. This requires
These trends are expected to continue and will most likely
high-resolution (x, y, and z) understanding of the thermal
accelerate into future compute products. As a result, the
characteristics (in particular conductivity) within a 3D stack.
following are thermal challenges related to both process
scaling and advanced packaging moving forward:
The above challenges are driving the need for new ingredients,
1. Increased power density at a chiplet level due to metrologies, and modeling techniques as shown in Table 7.3.
continued process scaling, as well as performance/
frequency increases with time. This will be exacerbated in
architectures where a 3D stack will create an additive- 7.5. Materials
effective power density requiring careful inter-stack
Materials that remain within the semiconductor package after
floorplan optimizations to mitigate power densities to the
processing (e.g., direct materials) are defined as constituents.
extent that the architecture can support.
These materials include a carrier (substrate, leadframe,
2. Heterogeneous architectures lend themselves to multi- interposers, buildup materials, redistribution layers, etc.), die
point thermal optimization because of the multitude attach, underfills, encapsulation materials, and solder materials,
of workloads to which the part may be subject, as well in addition to thermal solutions (e.g., lids, thermal interface
as the continued increase in core/execution unit count. materials, etc.). In contrast to constituents, “assist” materials
This becomes acute since an advanced package thermal are used as process consumables (e.g., tapes, resists, chemicals,
architecture often needs to make thermal tradeoffs and slurries); these are outside the scope of this section.
to improve thermals in one part of the package at the
expense of another part of the package. Application-specific drivers, including high-performance
compute, power electronics/electrification, and sub-THz
3. Power densities of high-speed IO continue to increase (for
communications infrastructure, will be used to specify
example, high speed SERDES). In some cases, it is desirable
new material capabilities for system-level performance
for these IP blocks to be placed in base dies of 3D stacks.
enhancements in the context of advanced packaging. Areas
This will increase the difficulty in dissipating the IP block
of focus include material improvements needed to enable
power due to the higher thermal resistance between
higher package-routing density/miniaturization, improved
the base die and the top of the 3D stack caused by
electrical performance, and mechanical and thermal
interconnect and dielectric layers in the silicon metal stack
performance enhancement for improved processability
(both in face-to-face and face-to-back 3D stacks).
and reliability. Advanced thermal solutions will be required
4. Thermal optimization across the package scale and system to enable system-level performance within the constraints of
scale is needed. The size and complexity of packages have maximum device-junction temperature, size, and cost. Package
been increasing, while the system cooling approach has platforms requirements range from traditional laminate and
moved closer to the package (e.g., moving from copper heat leadframe based packages to high-density flip-chip/fan-out
sinks toward liquid cold plates at relatively close proximity wafer level and large-format panel-level packages to enable
to the package). This results in the need to codesign the next-generation product cost and performance targets.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 146
 Table 7.3: Thermal management requirements

Power delivery
> 2023 > 2028 2033 and +
Ingredients
Thermal interface materials with low
thermal resistance and high resilience
Thermal
to package and board-level assembly
interface
techniques (50% or greater reduction
materials (TIMs)
especially in effective thermal
resistance under reliability conditions)
High conductivity (2x or greater than High-conductivity spreaders for
copper), low-cost materials for interfacing integration within a 3D stack that
Heat
that are capable of being cost-effectively are process-compatible; thermal
spreaders
manufactured into integrated heat conductivities >= 3000 W/m/K with a
spreaders on the package thickness of 50 mm to 200 mm
• Thermodynamically efficient system- Techniques to pull heat from within a
level solutions that include and address 3D compute stack
cold temperature operation necessary
for applications like quantum
computing within their scope.
System cooling
• Techniques to pull heat from within a
solutions
3D compute stack (including extracting
heat from each layer of the stack)
• Scalable two-phase technologies that
address global warming potential
and other regulatory requirements
Metrologies
Non-destructive, intra-package Non-destructive, intra-package Non-destructive, intra-package
temperature measurement technique temperature measurement technique temperature measurement technique
with 3 °C accuracy with 1 °C accuracy with <1 °C accuracy
Measurement of xy interfacial thermal Measurement of xy interfacial thermal Measurement of a spatial conductivity
resistance across 2 bonded silicon layers resistance across 4 bonded silicon layers and heat capacity field (including
interfacial resistances) within a 3D stack
Modeling
Thermally aware silicon place and route Digital twins that accomplish electrical-
techniques within EDA tools thermal-thermomechanical codesign
Workload-specific power estimation
tools during early pre-silicon design

Improved accuracy aero-acoustic

modeling/prediction techniques

Process developed and ready Additional development Major development effort Information only.
for manufacturing. work needed. needed for HVM.

Application-specific performance needs listed in Table 7.4 Such driving attributes or elements of this substrate platform
on the next page drive material property, processability, and are bump pitch and I/O scaling for chip interconnect and power
performance requirements. Specific material requirements delivery through embedding of discrete components.
and roadmap needs are outlined in Chapter 8.
For high-performance compute (HPC) applications, the
industry leaders have proposed a platform that can scale to
7.6. Substrates 10,000 IO/mm2. Translating this figure of merit to interconnect
terms implies interconnect areal density equal to 10,000
As the substrate transitions from a chip carrier to an integration
bumps or pads per square mm, which requires a bump
platform, driving attributes or elements of this substrate
or pad pitch of 10 micrometers. As the graph in Figure 7.3
platform need to transition to new scaling terms and targets.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 147
 Table 7.4: Package material needs and capability assessment

Power electronics/ Communications infrastructure

Material performance drivers High-performance compute
electrification (mmWave)
Device technologies Si-based Si, GaN, SiC Si, GaN, SiC

Interface frequency Medium (<100 GHz) Low (MHz) High (Sub-THz)

I/O interface pitch High (<10 µm) Low (>100 µm) Medium (<100 µm)
# Routing/Redistribution layers
High (>10), thin layers Low (<4), thick RDL layers Medium (<10)
(substrate, interposer)
Thermal requirements High (<125 Tj) High (up to 200 Tj) High
High (RF isolation, low loss),
Electrical requirements High (Isolation, low loss) High (HV isolation >1500 V),
thick dielectrics
Passive integration High (integrated) Medium Medium

Warpage management High (Panel Level) High Med - High

Low—Consumer/Industrial Med–High
Reliability requirements Medium—Industrial
High—Auto Industrial/Automotive/Aerospace

Low—Consumer
Zero-defect quality High Medium
High—Auto
Cost sensitivity Low-Med High Medium

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

illustrates, this density places interconnect requirements in Further, HPC applications utilizing HI technology will require
the transition region between solder-based and copper-to- both higher and lower linear-density wiring layers. The number of
copper interconnects—a transition that will present challenges wiring layers will depend on the IO density required, based on the
to both assembly and substrate technologies. For substrate levels of integration and performance needed. Also, the number
technologies, trace width, copper thickness, associated spacing of wires/mm/layer versus the half-line pitch in micrometers,
requirements coupled with dielectric materials and buildup as shown in Figure 7.4, illustrates the linear wiring capability
blind via pad diameters will influence areal-density capabilities. range of different interposer and substrate technologies.

Figure 7.3: Interconnect areal density (bump/mm2) versus bump pitch. Scaling the bump pitch
requires a transition from solder-based interconnects to Cu-to-Cu interconnections(adapted from 10).

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 148
Figure 7.4: Number of wires/mm/layer versus the half-line pitch in µm illustrates the linear wiring capability range of different interposer and
substrate technologies. The above are two elements of scaling for an advanced substrate serving high density/performance applications10.

To summarize, there are several options for future high- In any of these paths, it will be necessary to focus on
density substrate scaling. In one path, fine-pitch bumped manufacturing science and engineering to improve the
die (chiplets in most cases) would be attached to a high- economics and advanced substrate-manufacturing practices.
density organic substrate with features of ≤ 2 µm line and Specific operational goals, including yield, output, and
space. While there are concerns that the current material utilization, mapped over time and aligned with Industry 4.0
and process set may not support features below 5 µm line (smart manufacturing) initiatives, are needed to position the
and space, research is underway to develop new materials U.S competitively in this space.
and processes to achieve the desired target. Another path is
to use an organic/inorganic redistribution layer (RDL) to RF devices operating above 6 GHz require innovative solutions
route the fine-pitch bumps that are attached. The molded allowing for a high level of functional integration while still
or assembled RDL structure would be attached to a less dense ensuring optimum die operation temperature. Consequently,
laminate substrate. There are also potential new material the need for new materials, structuring, and assembly
alternatives that could be used. The trends in high-density technologies are continuously growing.
substrate technology are summarized in Table 7.5.

Table 7.5: High-density substrate technology assessment

> 5-10 years out (Grand

Attributes Current tech state of the art Near-term target (2-5 years)
Challenge)
Chip to substrate/bump pitch (µm) <100 (SOC) <50 (chiplets/HBM) <25? (chiplets/HBM)
2/2 or below
Conductor line / space (µm) 9/12 5/5
0.8 µm/0.8 µm (stretched target)
RDL/buildup via diameter (µm) 50 <25 <10

Body size (sq mm) 65x65 >100x100 >120x120

Layer counts 8 to 20 >20 >20

Core thickness 400 –1000 µm >1200 µm >1500 µm

Ability to embed low-density Integrated voltage regulators,
Si-bridge, capacitors Capacitor, inductor, IPDs
components encryption/security chips
Embedded component pitch (µm) 100 80 65

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 149
Substrates used in 5G and 6G devices are no longer simple • Encapsulation (underfill)
printed circuit boards (PCBs). These substrates are critical
• Thermal solution/lid attach
building blocks supporting the integration of systems and
are often referred to as system in packages (SiPs). They are • Ball grid arrays (BGAs) and components attach
now driving advanced IC substrate technologies, even though
• Inspection
previously carried by standard PCBs.
• Module test
Future systems, especially those operating above 100 GHz
• Scan and pack
[Years 1–3: 110–170 GHz (D-Band); Years 3–5: 220–350
GHz (G Band)] are leading-edge products supporting the
Advanced packaging includes a variety of assembly
implementation of several chips capable of processing and
technologies for integrating chiplets into packages,
transferring an increased amount of data. Advanced substrate
maintaining Moore’s law, increasing system performance, and
technology used for the manufacturing of RF packages and
enhancing and energy efficiency, all while also lowering cost.
modules are driven by miniaturization more than ever.
The various assembly technologies include fan-out wafer-level
package (FOWLP), redistribution layers (RDL), system-in-
In the near future, technologies will be needed that are
package (SiP), 2.xD (interposer, bridge), and 3D integration.
capable of embedding several passives and at least one active
component. Accordingly, the next generation of RF devices
Assembly technologies and tooling have evolved from
will require advanced IC substrate technology with miniaturized
traditional 2D multichip-module packaging to accommodate
structures such as L/S below 15/15 µm, a pitch size below
heterogenous integration of dies/chiplets (different size and
20 µm, and a pad size below 30 µm, in addition to assembly
functionality) and components on 2D SiP. Manufacturing lines
technologies with improved alignment accuracy.
need to be modified and optimized to enable multi-dies,
components placement—both on the topside metal (TSM)
Moreover, conductive traces and antenna patches will
and backside metal (BSM)—paste screening, solder-paste
be manufactured with an ultra-low surface roughness. In
inspection, and automated optical inspection. Assembly
combination with the implementation of low Dk/Df materials,
processes need to allow more stringent spacing between
these traces might suffer from delamination. Consequently,
components and join chips to laminates with advanced ground
these typically laminate-based substrates might require
rules. For example, at the encapsulation step, a capillary
adhesion-promoting agents to avoid delamination while
underfill needs to be dispensed in restricted areas with
still ensuring outstanding performance. Finally, manufacturing
precise and repeatable low-volume dispensing using new
of such systems-on-panel level (order of µm over 500 mm
dispense tools with high throughput. In addition to advancing
panels) will need simulation-based process optimization to avoid
assembly technologies driven by pitch scaling, component
warpage and reliability issues.
rework processes also need to be developed. Finally, these new
assembly processes need to be manufacturable while also

7.7. Assembly and Test meeting manufacturing yield goals, assuring robust reliability
specifications and being cost competitive.
Assembly
Assembly challenges
Packaging of an electronic system must consider protection
from mechanical damage (mechanical protection of the die), The transition from traditional flip-chip packaging (200–150
electrical connection (input/output), cooling (removal of µm pitch, solder-based interconnect) to fine pitch (130 µm)
heat dissipated by circuit function and device leakage), space with copper pillars (CuP) and new laminate design ground rules
transformation (transition from microscopic to macroscopic that offer higher interconnect density present new challenges
interconnect), radio-frequency noise emission, electrostatic to assembly and manufacturing. The eventual adoption
discharge, and product safety. of large laminate formats (> 80 mm x 80 mm), enhanced
thermal solutions, and new interconnect structures (CuP) will
The traditional assembly process flow is as following: necessarily cause a change in the materials and processes prior
to and during the assembly. Some examples of these impacted
• Die, sort, and pick/backside grind
materials and processes include different flux strategies (spray
• Chips and components place and join vs. dip), new encapsulation materials, and alternative thermal

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 150
interface materials for thermal performance that are still with advanced packaging solutions presents its own unique
compatible with BGA products. New tools are needed to handle challenges, and those depend at which assembly steps the
the increased warpage of these large laminates to ensure BGA optical engine is integrated into the package. For example,
coplanarity and/or component screening-process compatibility it could necessitate using a fluxless chip-joining process,
(TSM/BSM). New inspection tools are also required for these low-temperature cure TIM, and seal band materials, as
complex module layouts. well as low-temperature BGA alloys. Building the optical
engine requires a whole different set of skills that consider
To address high bandwidth and the need for additional I/O fiber-attach assembly processes, module connectivity (ability
in the transition to chiplets, the advancement of newer to reflow fiber components), and optical characterization.
technologies like ultra-fine-pitch packaging (<= 55 µm One of the grand challenges for CPO will be around the fiber-
pitch), CuP and advanced-packaging solutions (such as attach assembly since, as the design ground rules improve, the
2.xD, Si bridges), and 3D vertical integration are necessary. densification of the fibers increases, and the attach process
Assembly of chiplets (potentially thinner, multi-pitch, and will increase in complexity.
cantilevered), as well as components using these advanced
technology elements, require more precise dicing/picking Test challenges
and placement tools while being able to handle thinned Si.
Advanced packaging and heterogeneous integration
Alternative chip joining methods and tools are also needed,
produce a mosaic of diverse system-in-package designs and
such as thermocompression bonding to replace mass reflow
applications. Manufacturing test development of such a
with the possible inclusion of a non-conductive paste (NCP)
mosaic is challenging in many aspects. Specifically, using off-
material for encapsulation and/or flux. Moreover, the
the-shelf existing chips in design leads to non-optimized
encapsulation process itself might need a more accurate
design-for-test (DFT) integration. DFT insertion is often
dispense within a confined area that drives the need for new
done on a per-die design basis, with a single-chip design
dispense tools and/or new dispense pumps. New inspection
perspective, and does not account for impacts of multiple
tools are also required for wafer incoming inspection, pre- and
chips in SiP. This leads to deficiencies in DFT resulting in more
post-joining, and encapsulation of these higher-density complex
expensive instrumentation in automated test equipment
module layouts. These new assembly processes need to be
(ATE), an overall higher cost due to longer test times
manufacturable, reliable, and cost competitive. Consideration
(sequential ratio vs. concurrent testing possibility), massive
must be given to contamination control for assembling very-
amounts of scan test patterns, and a much larger volume of
fine-pitch packages since some high-performance applications
data that must be transferred to the SIP-ATE testers.
may require a higher cleanroom specification.

Consideration of analog, RF, mm-wave, and photonics

Within the next decade and beyond, moving to even finer
applications imposes higher digital and non-digital channel-
pitches (< 10 µm) will be required to meet the extreme needs
count ATE requirements. Chiplets with fine-pitch bumps
of interconnection density for future chip performance, lower
are also challenging, though they present opportunities for
power for energy efficiency while maintaining signal and
additional advances in test.
power integrity. The assembly technologies and processes
will need to transition from solder-based interconnects to
Innovation is required to address the challenges that are
solder-free interconnects (Cu-Cu). This transition will involve
expected in the future. There is a need for industry-wide
development of silicon stacking solutions and tooling for die-
standardization and strong market adoption for SiP DFT, as
to-wafer (D2W) or die-to-die (D2D) hybrid bonding. In addition,
well as test architecture that supports manufacturing level and
hybrid bonding processes will require wafer finishing equipment
fast test times with diagnostic test capabilities that are also
like chemical mechanical planarization (CMP) and a cleaner
power-aware. EDA industry leaders that adopt new standards
environment than is typical in assembly/manufacturing lines.
for SiP package and chiplet designs will foster a waterfall in
ATE instrumentation/software offerings at lower cost, with
Co-packaged optics (CPO) will be critical to address the
modularity, high commonality, and reuse rate. In addition,
future bandwidth and power needs. We can anticipate a
there is a need for self-automatic scan and algorithmic test
wide range of applications for CPO from Data Center (multi-
pattern generation, sampling in chips by SiP configuration-
chip module or MCM CPO) to AI/HPC (3D CPO wafer-level
aware engines and super SiP built-in self-test (BIST) engines
processing) to future systems with silicon photonic (SiPh)
with power-aware throttling.
chiplets. Integrating optical engines to a SiP and others

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 151
7.8. Performance and at different length scales need to be coupled at different
levels of accuracy to support diverse codesign needs. Machine
Process Modeling and Model intelligence and domain expertise need to be fused to

Validation significantly accelerate modeling, analysis, and optimization at

device, circuit, and system level.
Validated performance and process modeling is key to
accelerating microelectronics and advanced packaging Hierarchical uncertainty quantification (UQ)
technology development. A significant challenge to modeling across design layers
complex heterogeneously integrated (HI) systems is the need
Quantification of the uncertainties of complex heterogeneous
to span nearly eight orders of magnitude in length scale,
system under process variation needs to be carried out. Such
from angstrom to centimeter, spanning materials/structures,
models are very challenging because of many correlated design
devices, chips, and packages, along with the need to couple
blocks, high-dimensional uncertainty sources, and insufficient
material, electrical, photonic, electromagnetic, thermal, and
knowledge about the statistical behavior of uncertainties.
mechanical behaviors. Broadly, modeling serves several roles:

1. develop novel materials and interfaces through ab-initio High-fidelity failure models for chip and package
techniques; structures
2. assess coarse performance during design exploration; Detailed multiscale behavioral models are necessary to
accurately estimate the time-to-failure or viability of a
3. create accurate behavioral assessment for design
processing condition. As through-silicon-vias (TSVs)
refinement through detailed evaluation;
and interconnect lines are scaled down to sub-micron
4. assist manufacturing process development through length scales, and as solder bumps are scaled down to
simulation; and tens of micrometers, the microstructure will impact
electromigration-driven voiding and fatigue fracture.
5. improve manufacturing process yield through defect
High-fidelity models for these failure mechanisms are not
prediction.
readily available at present.

For models to serve their expected role, they must be

Models of materials and interfaces
rigorously validated.
The scaling of semiconductor technology has led to
In general, the data representations in the models consist of dimensional convergence between materials and structures,
both physics and geometrical attributes in each of the length which in turn has led to new emergent properties and
scales. The information exchange between the scales will characteristics. Examples of these include complex
consist of material, geometry, and simulation attributes. convolution between electronic, electrical, thermal,
Given that each of the scales consists of its own governing mechanical, and chemical properties. In addition, scaling has
equations, interfacing between the scales is necessary to caused interfaces to become critical to materials. In general,
provide a modular platform for linking, independent of models of materials and interfaces that bridge length scales
the underlying models. Thus, the model abstractions need from quantum to continuum are needed.
to be modular, flexible, and scale-, material-, and geometry-
independent. Machine learning (ML) models may be good Material property database
candidates for such abstractions.
Modeling structures at the device level (FEOL, BEOL metal,
and low-k materials), chip level (3D interconnects and
Following are details of the specific elements that must be
bonding interfaces), and package level (solder/underfill,
addressed in the modeling.
mold compound, redistribution layers, bumps, thermal-
interface materials, and cooling solutions) require a
Rapid multiphysics, multi-resolution modeling
database of accurate material properties to be developed.
for codesign
Empirical correlations for effective heat-transfer coefficient
Rapid, large-scale, and coupled multiphysics modeling prediction also need to be developed using computational
and analysis from atom to system level (multiscale) are fluid-dynamic (CFD) modeling. The current status of the above
necessary to enable HI codesign. The multiphysics models modeling needs is listed in Table 7.6.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 152
 Table 7.6: State-of-the-art and future modeling needs related to advanced packaging and HI

Modeling attribute State of the art Future need

Chip-package codesign tools are not Tools and algorithms to enable efficient co-optimization across
Rapid modeling for
automated; system design is manual and multiple domains, e.g., thermals, power integrity, signal integrity,
codesign
tedious reliability, and manufacturability
Uncertainty
Deterministic design Variation-resilient design
quantification
ML for models Not widespread, fidelity to physical models ML models that match physics-based models in fidelity but are
abstraction unproven significantly less computationally expensive to run
Simulation tools for thermomechanical modeling and reliability
Life prediction is generally not accurate, often
High-fidelity failure to enable correct-by-design configuration; fullwave solvers
in error by 100%; damage accumulation physics
models approaching linear computational complexity; multiscale processing
not well captured in models
simulation tools
Defect metrology using reconstructed images Tools for improved modeling of unit processes; AI-based tools for
AI for process control
takes hours near-real-time defect metrology
Metrologies that measure constitutive behavior and fracture
toughness of films (and film interfaces) < 10 μm in thickness;
Film-adhesion characterization is challenged
metrology to measure adhesion strength of deeply buried
Characterization & by sample fabrication and ensuring the
interfaces across polymers-polymers, polymers-ceramics, and
reliability testing propagation of crack through the interface in
polymers-metals; improved physics-based reliability models;
test samples
test methods that better capture the effects of multiple failure
mechanisms, including AI enhanced methodologies

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

7.9. Reliability Both the overstress and wear-out failure mechanisms

are caused by thermal, mechanical, electrical, chemical,
The reliability of heterogeneously integrated packages radiative, magnetic, and humidity loads acting alone, as
is critical for meeting the increasing demands of high- well as acting in combination with one another, such as with
performance electronic systems. Grand challenges include thermo-mechanical, thermo-hygro-mechanical, thermo-
the integration of advanced packaging architectures, electrical, and thermo-chemical loads. These loads may
materials, and structures (e.g., use of advanced adhesive come either from internal working of the product and/or the
and self-healing materials), the use of advanced modeling external environmental or operating conditions. Application-
and simulation techniques, and the development of new specific magnitude and duration of such internal and external
testing and qualification methods. conditions will be essential to assess reliability. Such an
assessment can be performed through physical prototyping
In general, the reliability of a product is its ability to perform and testing, as well as through virtual (simulated) prototyping
its core function(s) through the intended lifetime. The and testing. Table 7.7 provides application-specific reliability
reduction in performance of core functions, as well as qualification guidelines.
the loss of auxiliary functions, will be considered reduced
or compromised reliability but not loss of reliability. The HI is evolving horizontally and vertically with 3D, hybrid bonding,
loss and reduction in reliability in advanced packaging and embedded bridge, and other advanced technologies with new
heterogeneous integration is a result of failures in devices, materials, innovative processes, and testing protocols. However,
packages, subsystems, and systems, which are caused by when demands for higher functionality, better performance,
overstress and/or wear-out mechanisms. The overstress and enhanced power requirements are augmented with the
failure occurs when the applied load exceeds the critical load/ need for smaller size and reduced weight and cost, reliability
strength of a material, while the wear-out failure occurs under and testing challenges arise. The reliability of these advanced
repetitive or cyclic application of subcritical loads. Overstress packages is crucial for enabling these technologies. Thus, the
failure mechanism is usually catastrophic and sudden, and qualification metrics in the table will not change significantly
the examples include brittle cracking, debonding, melting, over the next 10 years but are shown in red, especially since
and dielectric breakdown. Wear-out failure mechanism is it will be challenging to meet the same reliability metrics if
gradual and cumulatively damaging, and the examples include such new materials, processes, and the dimensions do not
interconnect cracking, debonding, and electromigration. take reliability into consideration upfront during design.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 153
 Table 7.7: Application-specific reliability qualification guidelines are not expected to change
significantly, but meeting these same metrics will be challenged in the next decade (shown in red).

AMS Power electronics, Harsh conditions

Digital
(Mobile) automotive E-vehicles (IC automotive, defense)

2023 2033 2023 2033 2023 2033 2023 2033

-40°C to -40°C to -40°C to -40°C to

Thermal -55° to 150°C -55° to 150°C -55° to 150°C 55° to 150°C
125°C, 125°C, 125°C, 125°C,
cycling 2,000 cycles 2,000 cycles 2,000 cycles 2,000 cycles
700 cycles 1,000 cycles 1,000 cycles 1,000 cycles

25°C to 25°C to -40°C to -40°C to -40°C to -40°C to

Power and
- - 110°C, 110°C, 125°C, 125°C, 125°C, 125°C,
Temp Cycling
1,000 cycles 1,000 cycles 1,000 cycles 1,000 cycles 1,000 cycles 1,000 cycles

Thermal
85°C, 85°C, 150°C, 150°C, 150°C, 150°C, 150°C, 150°C,
storage or
1000h 1500h 1500h 2000h 1,000h 2,000h 1,000h 2,000h
HTSL

110°C/ 110°C/ 130°C/ 130°C/ 130°C/ 130°C/ 130°C/ 130°C/

HAST 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 85%RH, 85%RH,
96h/192h 96h/192h 96h/192h 96h/192h 96h/264h 96h/264h 96h/264h 96h/264h

TH and Bias TH and Bias

Temp/ 85°C/ 85°C/ 85°C/85%RH, 85°C/85%RH, 85°C/ 85°C/ 85°C/ 85°C/
Humidity 85%RH 85%RH 1000 h 1000 h 85%RH, 85%RH, 85%RH, 85%RH,
testing 1,000h 1,500h 85°C/85%RH/ 85°C/85%RH/ 1,000h 1,000h 1,000h 1,500h
3.6 V, 1000 h 3.6 V, 1000 h

Junction
105°C 110°C 105°C 110°C 180 to 225°C 225 to 300°C 105°C 110°C
temp

1500G, 1500G, 1500G, 1500G,

1500G, 1500G, 1500G, 1500G,
1 drop, 6 axes 1 drop, 6 axes 1 drop, 6 axes 1 drop, 6 axes
Shock 10drops, 10drops, 5drops, 5drops,
(MEMS cavity (MEMS cavity (MEMS cavity (MEMS cavity
3 axes 3 axes 3 axes 3 axes
device only) device only) device only) device only)
50G sweep 50G sweep 20G sweep 20G sweep 50G sweep 50G sweep 50G sweep 50G sweep
from 20Hz to from 20Hz to from 20 Hz to from 20 Hz to from 20Hz from 20Hz to from 20Hz from 20Hz
Vibration 2,000Hz, test 2,000Hz, test 2,000 Hz, test 2,000 Hz, test to 2KHz to 2KHz to 20Hz to 2KHz to to 2KHz to
done for 60 done for 60 done for 15 done for 15 20Hz, 60 min 60 min per 20Hz, 60 min 20Hz, 60 min
min per axis min per axis min per axis min per axis per axis axis per axis per axis

Intended
2-3 years 2-3 years 7-10 years 7-10 years 15-20 years 15-20 years 15-20 years 15-20 years
lifetime

Quality of
<100 PPM 10-50 PPM <10 PPM <10 PPM < 1 PPM < 10 PPB < 1 PPM < 10 PPB
reliability

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

7.10. Challenges, Future chiplet system architecture is the industry answer. Advanced

Needs, and Possible Solutions packaging solutions will be required to achieve chiplet
integration for HPC and future quantum and AI technologies. In
The need for higher performance and more bandwidth based general, the exponential growth in package pin counts and I/O
on traditional semiconductors dimensional scaling has reached power consumption, domain-specific architectures, technical
their physical limits. So, with the slowing down of the shrinking and business model of IP reuse, and mixed technology node
of transistor gate pitch and chip sizes reaching reticle limit, a chiplets will drive advances in HI and advanced packaging.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 154
Technological progress for advanced packaging will The extreme interconnect density needs of next-generation
require new design tools to enable the package design to packaging will drive ultra-fine pitches (< 10 µm pitch) and
support the codesign workflow and predictive modeling to very-fine-line/space (sub 1 µm L/S) circuitry. The assembly
minimize the iteration cost between architecture and design technologies and processes will need to transition from solder-
implementation. The need for models to span nearly eight based interconnects to solder-free interconnects (Cu-Cu).
orders of magnitude in length scale and the need to carry This transition will involve development of silicon stacking
out multiphysics analysis will be significant challenges to solutions and tooling for die-to-wafer or die-to-die hybrid
designing and analyzing HI/AP systems. Power delivery at a bonding. Lastly, the need for smaller size and reduced weight
higher voltage using integrated voltage regulators is needed and cost will drive the reliability and testing challenges. While
because an increase in CPU and GPU power will cause routing the qualification metrics may not change significantly over the
losses to have significant impact on overall system efficiency. next 10 years, it will be challenging to meet the same reliability
Increased power dissipation will necessitate codesign of metrics, if such new materials, processes, and the dimensions
system heat-removal strategies through package thermal do not take reliability into consideration during design.
design. This will be exacerbated in architectures where a 3D
stack will create an additive effective power density requiring
careful inter-stack floorplan optimizations to mitigate power
densities that the architecture can support.

Contributors
Griselda Bonilla (IBM) – Chair Zia Karim (Yield Engineering Systems) John Park (Cadence)

Henning Braunisch (Intel) – Vice Chair Jason Kawasaki (UW-Madison) Mark Poliks (SUNY Binghamton)

Ganesh Subbarayan (Purdue University) – Matt Kelly (IPC) Kaladhar Radhakrishnan (Intel)
Vice Chair
Jong-Hoon Kim (SK hynix) Gnyaneshwar Ramakrishna (Cisco)
Amit Agrawal (NIST)
Walter Kocon (GlobalFoundries) Urmi Ray (iNEMI)
Bilal Akin (UT- Dallas)
Michel Koopmans (Micron) Sathya Raghavan (IBM)
David Bergman (IPC)
Deepak Kulkarni (AMD) Sadasivan Shankar (SLAC Nat’l Lab)
Kirk Bresniker (Hewlett Packard Enterprise)
Gilles Lamant (Cadence) Ravi Shenoy (Qualcomm)
Yu (Kevin) Cao (Arizona State University)
David Landsman (Western Digital) Akshay Singh (Micron)
Abjhit Chatterjee (Georgia Tech)
Thomas LeBrun (NIST) Suresh Sitaraman (Georgia Tech)
Aiping Chen (LANL)
Timothy Lee (Boeing) Spyridon Skordas (IBM)
Gary Chen (TSMC)
Heejin Lee (SK hynix) Ilseok Son (TEL)
Promod Chowdhury (IBM)
Sung-Kyu Lim (Georgia Tech) Eric Tervo (UW-Madison)
Bob Conner (3D Glass Solutions)
Ravi Mahajan (Intel) Sharad Vidyarthy (Analog Devices)
Josh Conway (America’s Frontier Fund)
Babu Mandava (3D Glass Solutions) Chip White (Georgia Tech)
Mike Delaus (Analog Devices)
Varughese Mathew (NXP) Glen Wilk (ASM)
Patrice Ducharme (IBM)
Andrew Mawer (NXP) Brett Wilkerson (AMD)
Jeb Flemming (3D Glass Solutions)
Rajiv Mongia (Intel) Jaimal Williamson (Texas Instruments)
John T. Heron (University of Michigan)
Benoit Montreuil (Georgia Tech) Charles G. Woychik (Skywater Technologies)
Tengfei Jiang (University of Central Florida)
Kwangjin Moon (Samsung) Jinkyoung Yoo (LANL)
Dan Jiao (Purdue University)
John Oakley (SRC) SeHo You (Samsung)
Dae Young Jung (SUNY Binghamton)
Valérie Oberson (IBM) Katie C. Yu (NXP)
Pikyu Kang (Samsung)
Kunal R. Parekh (Micron) Ming Zhang (PDF Solutions)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 155
References for Chapter 7
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1

The White House 100-Day Review, “Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-Base Growth,”
2

https://www.whitehouse.gov/wp-content/uploads/2021/06/100-day-supply-chain-review-report.pdf

W. T. Chen, “The Future Is Heterogeneous Integration,” https://www.3dincites.com/2021/01/the-future-is-heterogeneous-integration/

3

R. Mahajan and B. Sankman, “3D Packaging Architectures and Assembly Process Design,” Ch. 2 in 3D Microelectronic Packaging, Y. Li and D. Goyal
4

(eds.), Springer, 2017.

M. M. Shulaker et al., “Three-Dimensional Integration of Nanotechnologies for Computing and Data Storage on a Single Chip,” Nature, vol. 547, pp.
5

74–78, 2017.

D. Yu, “Foundry Solutions for 2.5D/3D Integration,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2021.
6

R. Mahajan et al., “Co-Packaged Photonics for High Performance Computing: Status, Challenges and Opportunities,” Journal of Lightwave
7

Technology, vol. 40, no. 2, pp. 379–392, Jan. 2022, doi: 10.1109/JLT.2021.3104725.

Codesign for Heterogeneous Integration, Ch. 13, https://eps.ieee.org/technology/heterogeneous-integration-roadmap.html

8

H. Multaba, “AMD Discloses its Multi-Layer Chiplet Design Era, Starting with Zen3 with 3D Stacked V-Cache Technology,” website:wccftech.com/
9

AMD. August 22, 2021.

10
R. Mahajan, “Tighter Integration between Process Technologies and Packaging,” https://www.edn.com/tighter-integration-between-process-
technologies-and-packaging/

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 156
Chapter 8

Materials, Substrates, and

Supply Chain
8.1. Introduction and isolation. Larger package formats with improved
economies of scale (e.g., panel-based) and thick Cu layers
Key technology application drivers, including high-performance
are needed to compete in a global environment.
compute, automotive sensing, electrification, power electronics,
and 5G/6G communication infrastructure, require significant • Sub-THz mmWave: The drive to higher RF frequencies
improvements in packaging materials over the next decade and requires material development to enable 5G/6G
beyond to enable system performance scaling. The increased communications, including antennas-in-package and
data-bandwidth requirements of 6G drives the need for higher Automotive Sensing applications with low loss materials and
frequencies1-2, as shown in Figure 8.1. thermal solutions.

• High-performance compute: Architectures with reduced

Specific technology trends across market
memory latency require new interposer, substrate, and
segments
thermal solutions to enable higher levels of signal isolation,
• Power electronics/electrification: Migration to GaN- lower signaling loss, and improved thermal management.
based and SiC-based devices for high-power applications, Beyond server applications, materials will need to support
including electric vehicles and battery management, automotive reliability and cost requirements for L4/L5
requires new package materials that can withstand higher autonomous driving compute applications.
temperatures and operating voltages with high reliability

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 157
 Figure 8.1: 4G to 6G mmWave: Communications Frequency and Bandwidth Trends (adapted from Ref 1)

This chapter outlines development needs of packaging structural and operational transformation to develop the
materials, as defined as all constituents that connect devices adaptability, agility, competitiveness, efficiency, resilience,
to application-specific printed circuit boards, including security, sustainability, and trustability necessary for thriving
substrates, interposers (Si based, organic, inorganic, glass), within the emerging complex world. This complexity includes
die attach, underfills, interconnects, solder balls, and high uncertainty and disruptiveness, fast technological
encapsulation materials, as well as materials used for heat evolution, and geopolitical volatility and polarization.
dissipation (lids, metal slugs, thermal interface materials,
etc.). Significant materials development is required to enable
miniaturization, electrical performance (isolation, low loss), 8.2 Material Requirements
improved mechanical performance, processability, advanced
thermal solutions, and reliability within cost constraints
for Power Electronics/
required by each specific application. Fundamental changes Electrification Advanced
will also be required to enable environmental sustainability, in
addition to new formulation/selection of materials to enable
Packaging
zero-emissions and recyclability. Key material development needs include: advanced thermal
solutions to reduce system cost, weight, and size; high-
The final section of this chapter addresses the key innovation voltage isolation/miniaturization; high reliability at higher
challenges over the next decade and beyond for the end- temperatures (higher Tj) with transition to GaN; SiC and large-
to-end semiconductor supply chain ecosystem. In essence, format processing with thick layers for high voltage/current;
the ecosystem and its numerous supply chains need a deep and warpage control.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 158
 Table 8.1: Package material capability assessment for Power Electronics/ Electrification.
Global capability assessment of Tier 1 material suppliers independent of geography.

Power Electronics/ Electrification Packaging Material Requirements

Attributes Current 5 years 10 years

Packaging platforms Laminate & LF-based Laminate & LF-based Laminate & LF-based (QFN, LGA, BGA, SiP)
(QFN, LGA, BGA, SiP), (QFN, LGA, BGA, SiP), flip Contactless package (example: EM energy
power QFN, specialized chip/ (HD) FOWLP transfer), flip chip/ (HD) FOWLP/PLP
package (TO)
Package dimensions 2x2 to 7x7mm 1x1 to 2x2 mm Chip scale

Device material Si GaN, SiC GaN, SiC

Max junction temp 175C 200C 200C and beyond

Max voltage 1300V >2000V TBD

Interconnect/via WB- Au wire, Cu wire, WB-Cu wire, OSP, Cu Pillar, OSP, SOP, ENIG, ENEPIG, Electrolytic
material/surface multiple Cu vias, Cu SOP, ENIG, ENEPIG, NiAu
finish pillar, OSP, ENIG, Electrolytic NiAu, Cu New materials (graphite, etc.)
ENEPIG, Electrolytic pillar interconnect,
NiAu thicker Cu-via/larger
surface area (clips)
Die attach materials Epoxy, solder (lead-free Sintering adhesive TLPS (Transient Liquid Phase Sintering)
& leaded) Sintering (Pb-free) Diamond New materials (graphite, etc.)
adhesive (Pb-free) and graphite-loaded
materials

Substrate Coreless/embedded Coreless with embedded Improved cooling integrated in substrates

with vias die
Embedded Embedded technology Die and passives Improved cooling integrated in substrates
technology (buildup, (buildup, substrates) integrated in buildup
substrates) layers
Encapsulation Low-alpha, High-thermal Low-alpha, high-thermal Low-alpha, high-thermal conductivity, MUF
materials/EMC conductivity, MUF conductivity, MUF Elimination of encapsulant
Thermal management Natural convection, Natural convection, Natural convection, forced convection, active
solutions forced convection, forced convection, active cooling, liquid cooling
active cooling cooling, liquid cooling
Conductive cooling Topside cooling
through substrate
Thermal materials metal lid, Cu slug TIMs (organic, metal Carbon-based or diamond
filler)
Underfill materials CUF, MUF CUF, MUF CUF, MUF

Second-level Solder paste, solder Solder paste, solder balls, Solder paste, Solder balls, Cu slugs
interconnect balls, Cu slugs Cu slugs
Passive integration Integrating passives into Integrated into device wafer (mainstream
system-in-package adoption when it becomes more cost effective)

Process developed and ready Additional development Major development effort Information only.
for manufacturing. work needed. needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 159
8.3 Material Requirements for Sub-THz mmWave Packaging
(5G/6G and Automotive Sensing)
Key material development needs include: advanced thermal launcher-in-package configurations; low Df/Dk materials;
solutions to maintain Tj <125C with reduced system cost, improved RF interconnect methods; thicker dielectrics;
weight, and size; improved RF performance at sub-THz warpage and variability controls; processing/aging resilience
mmWave frequencies to enable antenna-in-package and and materials to enable improved board level reliability.

Table 8.2: Package material capability assessment for sub-THz mmWave applications.
Global capability assessment of Tier 1 material suppliers independent of geography.

Sub-THz mmWave Packaging Material Requirements

Attributes Current 5 years 10 years

Frequency 28GHz-100GHz 100GHz-300GHz 300GHz and beyond

Desired packages Flip chip/ (HD) FOWLP Flip chip/HDFOWLP/PLP/ HDFOWLP/PLP (>300GHz), contact-less package
Hybrid PoP/PiP (example: optical or other energy transfer
method), glass-embedded
Package dimensions 10x10 to 20x20mm >20mmx20mm Chip scale

Interconnect/via Cu Low roughness Cu, air- Nano wires, optical connections, Si bridge, RF
material/surface filled waveguide, reduced isolated TSVs
finish feature sizes with
improved RF isolation
Die attach materials Sintering, CDAF Diamond paste, carbon- Graphite
loaded materials
Substrate BT substrate, low-loss Flip chip substrates with Glass
glass in laminate wave guides, low Dk/Df
materials
Embedded Multilayer buildup stack Hybrid integration of Meta-material structure enhancing local
technology (buildup, passives and actives, low functionalities (thermal, electrical, and
substrates) Dk/Df materials dielectric)
Encapsulation Thermally enhanced EM sensitive/ thermally Green materials, low-process temperature, high
materials/EMC mold compounds enhanced, active mold reliability
structuring
Thermal management Natural convection or Active/two-phase cooling Small form factor integrated active cooling
solutions liquid cooling
Thermal management TIMs (organic, metal Diamond paste, carbon- CNT pastes
materials filler) based paste TIM
(graphite filler)
Underfill materials Low Dk/Df materials low Dk/Df materials low Dk/Df materials

Interposers 2/3 Layer RDL/laminate Multilayer interposers

(coreless)
Second-level Solder balls
interconnect
Passive integration Integrating passives into Integrated into device wafer (mainstream
system-in-package adoption when it becomes more cost effective)

Process developed and ready Additional development Major development effort Information only.
for manufacturing. work needed. needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 160
8.4 Material Requirements for High-performance Compute
Packaging
Key material development needs include advanced thermal improved electrical performance, in addition to mechanical
solutions, such as methods applicable to 3D stacks and and thermal performance enhancement for better
materials to enable reduced pitch interconnects and chiplet processability and reliability. Advanced thermal solutions will
stacking. As discussed in Chapter 7, solutions are needed to be required to enable system-level performance within the
enable higher package routing density/miniaturization and constraints of max device junction temperature, size, and cost.

Table 8.3: Package material capability assessment for high-performance compute applications.
Global capability assessment of Tier 1 material suppliers independent of geography.

High-performance Compute Packaging Material Requirements

Attributes Current 5 years 10 years

D2D interface speeds 6 (HBM3 envelope) 32 (UCIe-A spec) TBD
(Gbps/wire)
Packaging platforms 2.5D, 3D 2.5D, 3D TBD

Substrate feature (9/12) mm line/space is mainstream High-bandwidth die-to-die links could TBD
sizes moving towards 8/8um drive features to ~(2/2) mm
Interconnect/via Cu – ENIG (Ni used for improved EM) Cu – ENIG (Ni used for improved EM) TBD
material/surface Oxide-based hybrid bond interconnect Oxide-based hybrid bond interconnect
finish
Die attach materials (Sn-Cu + Cu pillar) solder encapsulated Same materials for reduced-pitch TBD
with filled epoxy underfills interconnects
SiO2/SiCN Oxide
Substrate buildup/ Low-loss dielectrics (tan-d < 0.01)/ TBD (continued scaling will help) TBD
core organic core)
Encapsulation Epoxy molding compounds with silica Same materials for reduced-pitch TBD
materials/EMC fillers interconnects
Thermal management (Solder and polymer TIMs) + Cu IHS)/ (Solder and polymer TIMs) + Cu IHS)/ TBD
solutions bare die + (liquid cold plates or air- bare die + (liquid cold plates or air-
cooled heat sinks or limited single- cooled heat sinks or limited single-
phase immersion cooling) phase & two-phase immersion cooling)
Thermal management Solder and polymer TIMs, water or Solder and polymer TIMs, water or TBD
materials dielectric fluids for immersion dielectric fluids for immersion
Underfill materials Silica-particle-filled epoxies Silica-particle-filled epoxies TBD

Interposers Passive silicon Passive silicon TBD

Second-level (SAC or Bi-based low-temperature (SAC or Bi-based low-temperature TBD

interconnect solders) + board-level encapsulant (not solders) + board-level encapsulant (not
always used) always used)
Passive integration LSC/DSC, embedded passives, DTC LSC/DSC, embedded passives, DTC TBD

Reliability Consumer/Industrial Consumer/Industrial Automotive/

Industrial
(AECG2, 175C)

Process developed and ready Additional development Major development effort Information only.
for manufacturing. work needed. needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 161
8.5 State of the Art/Product Examples
Power electronics/electrification: Compared to traditional Sub-THz mmWave (5G/6G): System-level optimization to
silicon IGBTs, SiC MOSFET power devices offer electric vehicle reduce weight and size enables easier and more efficient 5G
makers the ability to increase the range and overall efficiency mid-band deployments in dense urban and suburban areas
of their systems. NXP GD3160 half-bridge EVB for RoadPak SiC as demonstrated by the AIR3268 ultra-lightweight antenna-
power modules deliver an automotive-qualified power density integrated radio. Weight reduction by over 40% reduces
efficient xEV inverter solution. Performance enablers include infrastructure required for deployment.4
fast and efficient power-device switching, plus galvanic
isolation between low-voltage and high-voltage domains, High Performance computing (HPC): Figure 8.2 shows the rack
which enables control and status channels between low- power and max device power needs for futuristic data centers.
voltage (<14V) and power (>300V) domains, as well as robust The three different system configurations will be supported
operation in harsh and noisy environments.3 for thermal management by air cooling and liquid cooling.

Figure 8.2: High-performance compute data center cooling technology needs.5

8.6 Challenges, Future Needs, and Possible Solutions

Material, package configuration, and system-level challenges Areas for material performance improvement
(thermal, reliability, mechanical, electrical performance, cost)
Thermal management: To enable reliable operation of high-
are specific to application driver requirements and trends. To
power devices in harsh conditions, materials development
further expand on areas of materials development required,
for high thermal conductivity and high thermal dissipation
needs are outlined by focus area.
capabilities is needed. These future needs include: novel
materials with desired electrical and mechanical properties
8.6.1 Power Electronics/Electrification Advanced
to reduce hot spots at high thermal densities ( > 500 W/cm2);
Packaging
high thermal conducting polymeric encapsulation materials;
Next-generation device technologies (Si transitioning to GaN, thermal interface materials (TIM) with low thermal resistance;
SiC) with higher operating and junction temperatures drive and high-power die-attach materials (sintered). In addition,
the need for material performance improvement.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 162
system-level thermal management technology improvements Specific challenges with frequency scaling above 20GHz
are required, which may include two-phase cooling, as compared with standard BGA routing technologies are
immersion cooling fluids, heat pipes, diamond films, etc. shown in Figure 8.3. Next-generation device technologies
with increased frequencies above 100GHz, along with higher
Material electrical performance: To enable denser routing operating and junction temperatures, drive the need for
features (low leakage) with high voltage, improvements in material performance improvement.
electrical performance include high breakdown field (>200
V/µm) for high-voltage applications, as well as materials Next-gen device technologies
for advanced packages, including stacked die, high power,
Thermal management: System-level thermal management will
higher functionality, high-voltage isolation, high comparative
require technology improvements such as two-phase cooling,
tracking index (CTI) epoxy mold compounds, and lower Dk/
immersion cooling fluids, heat pipes, diamond films, and TIMs
Df materials. Materials with high electrical insulation are
with low thermal resistance and high thermal conductivity.
needed at small length scales (e.g., < 10 µm). Materials with
a high breakdown field that is much higher than in current Material electrical performance: New materials for high
polymer materials (e.g., current capability 20–30 V/µm) must frequency (substrates, buildup materials, interconnects) include:
be developed. In addition, the migration to larger-format
• Novel materials to reduce RF loss and improve isolation
substrates requires packaging materials with thick Cu layers
performance while enabling miniaturization
and large feature sizes (>10um) for reduced resistance.
• Thick dielectric layers to enable mmWave antenna-in-
Materials for high reliability/mechanical performance: To package RF performance with increasing frequencies, low
surpass AECG0 reliability requirements, dependable adhesives loss, and low dielectric constant (Dk, Df)
with high adhesion strength to various materials (such as
• Well-characterized and consistent properties compatible
dielectric, metal, leadframe, and polymeric interfaces)—even
with other packaging materials
at high temperatures (e.g., 200° C) and under cyclic loading—
are needed. Improvement of encapsulation materials with low • The ability to withstand harsh environments for processing
warpage are especially needed for various substrates like large and operation
format. For power applications, this includes enabling thick
conductors and dielectric layers. Development of materials In addition, advances are required in TCDk and TCDf
with improved processability is needed to maintain electrical (Temperature Coefficient of Dielectric Constant and
performance during integration and aging. This includes Dissipation Factor) and Sub-THz mmWave materials
corrosion-resistant materials to prevent/mitigate corrosion by characterization methods at 300GHz and beyond.
ions (e.g., Cl). In addition to substrates, material improvements Performance requirements propel the need for reduced
for enhanced printed circuit board (PCB) technology are feature size tolerance for interconnect, substrate, and buildup
imperative, including high reliability, high temperature layers (misalignment, size variations), including changes over
(150-250° C), high voltage (> 100 V), high frequency, high temperature, manufacturability control methods, and reduced
density, and corrosion-free in high temperature/humidity Cu trace roughness (as shown in Figure 8.4).
environments.
Materials for high reliability/mechanical performance:
8.6.2 Sub-THz mmWave Packaging (5G/6G and Advancement is needed, including low warpage materials to
Automotive Sensing) enable larger body sizes (>20x20mm), materials to increase
board-level reliability performance for antenna-in package
Advances in substrate design, materials, and assembly technology
configurations, and materials with minimal property shifts due
are required to optimize insertion loss and noise performance
to process integration and aging.
with migration to sub-THz mmWave operating frequencies.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 163
 Figure 8.3: Key signal integrity challenges with frequency scaling demonstrated
by traditional package routing vs. uniform microstrip above 20GHz.6

Figure 8.4: Sub-THz mmWave material performance challenges.7

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 164
8.6.3 High-performance Compute integration, and system-level assembly options (outside of the
standard OSAT realm). All of these packaging challenges have
High-power computing will require different cooling
material implications as well, which are shown in Table 8.3 and
techniques to maintain a system and chip temperature. The
need to be addressed by material suppliers.
various techniques of forced air and liquid cooling are shown
in Figure 8.5.
Industry trends toward the software-defined vehicle with
autonomous driving (L4/L5) will require significantly higher
The use of a thermal interface material (TIM) between the
central compute performance. The demand for low latency
package and the cooling plate is necessary to drive heat
memory may require 2.5D/3D package configurations with
out of the package. For the futuristic roadmap of TIM, the
TSVs and thinned memory die, as outlined in Chapter 7, but at
adhesive suppliers must drive down the thermal resistance
automotive quality and reliability levels (i.e., 175C and AECG2).
while ensuring that the other properties of the TIM (i.e.,
This will drive the need for new materials and processes.
elongation, adhesion, tensile, shrinkage, etc.) are not
impacted too much. The material must balance all properties
8.6.4 Possible Solution Substrates
to work in the application. The package warpage due to the
interaction between the package size and the temperature Substrate fabrication methods and technology are driven
exposure is also a challenge to be addressed in TIM selection. by many factors. The main contributing element is larger
To maintain effectiveness, TIM materials must have properties body size, where packages become larger than 100x100mm,
like shrinkage to offset the effects of package warpage and especially in the high-power computing spaces. Hybrid surface
remain void-free after power temp cycling. Material needs for finishes are also being requested due to the different surface
HPC are shown in Table 8.3 and are in line with the industry interfaces, i.e., OSP on the PCB interface and SOP on the flip
needs. However, for added functionality and routing, line chip side. Due to functionality for high-speed applications, the
width and spacing must be reduced to 2 µm. higher layer counts of substrates are needed. Encompassed
with an increased body size, this can also have fabrication
As HPC systems move toward advanced packaging solutions, challenges. Moreover, line width and spacing between traces
such as CoWOS, InFo, Chiplets, etc., with advanced nodes requirements are being reduced with a target < 5 µm, due to
being introduced (65 nm to 2 nm), the power density will densification of signal routing. From a stack-up material (core
also increase—as will challenges regarding package/die and buildup) point of view, materials with low CTE for stress
size increase, application power loading, system-level power mitigation and low dielectric constant and loss are required

Figure 8.5: High-performance computing cooling methods.8

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 165
for high-speed applications. Another contribution to the a two-layer substrate to a five-layer substrate, plus an added
fabrication is the stacking of vias to reduce signal path, as cost of the core layer. High-frequency packages that operate
stress mitigation comes into play when more vias are stacked in the 28 GHz + range are driving the need for low-loss
on top of each other. Coreless substrates, also known as materials, innovative packaging, and substrate techniques, as
embedded traces substrates, are also becoming predominant well as low roughness in the copper foils of the substrates.
in the fabrication process. Manufacturing challenges must be Some of the notable substrate properties required in the
overcome as well, with more buildup required, moving from roadmap are shown in Table 8.4.

Table 8.4: Buildup substrates using impregnated materials or buildup films (i.e., ABF).

Properties 2023 2028+

Line/spacing (μm) 9/12 2/2

Bump pitch (µm) 90 60

Max body size (mm x mm) > 75 x 75 120x120 +

Core thickness (µm) 400 – 1000 µm up to 1500+

Df of buildup film 0.005-0.02 < 0.004

Thick core FC-BGA, multilayer core
Package type FC-BGA (ABF)
FCBGA
Layer count 2 – 18 up to 20+

More non-lead alternatives to PZT are also imperative. The

8.6.5 Possible Solution Substrates
development of a magnetorestrictive actuator and low-power
MEMS device and package materials roadmap: Innovation electrorestrictive materials are also needed, in addition to a
in materials is critical to the success of performance high-reliability bill of materials with stable performance over
enhancements in MEMS-based products, driving requirements temperature with no thermal hysteresis.
for manufacturing, materials suppliers, and researchers.
Important advances over the next five to 15 years will be key MEMS material requirements depend heavily on the working
to achieving manufacturing success, including better materials principle of the MEMS device, the device function, and its end
characterization of bending, flexing, and stretching for the application. In the coming years, there will be a need in
development of medical devices. In addition to electrical the inertial device area to have improved getter materials
properties, characterization with respect to multiple energy at lower cost. In the area of chemical sensors, there is an
domains (e.g., vibrational and thermal) is required for sensors. entirely different set of needs, including boron-doped
Enabling the distribution of characterized material property silicon nanowires, nanoparticles that attract specific gases,
data through standard methods, such as PDKs (process design and highly selective sticking coefficient materials. Some
kits), is preferred for packaging materials. Low CTE mismatch key roadmap items specifically for optical MEMS are the
material sets for inertial, pressure, and optical MEMS are development of processes for lead-free optical glass, layers
also needed, as are improved low-stress deposited materials that do not change mirror shape over temperature, and
like nitrides, as well as improved coatings for anti-stiction, high-quality LNO depositions. Addition key requirements
eliminating charge, anti-wear, and anti-corrosion. In devices are thin film layers for adhesion and diffusion for mirror
such as microphones, actuators, and ultrasounds that use metal and low outgassing materials. For RF switches, there
piezoelectric materials, it’s vital that these materials are remains a need for high-quality materials for contacts. For
engineered to be fatigue-free at low temperatures and to PMUTs (Piezoelectric Micromachined Ultrasonic Transducers),
achieve thicker layers. Other specs that need to be improved higher-performance doped AlN is important to improving
for piezoelectric materials are process stability, reproducibility, device specs. For CMUTs (Capacitive Micromachined
and homogeneity, along with a lower deposition cost. Ultrasonic Transducers), membrane materials that have low

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 166
stress and are homogeneous across a wafer are desired. materials and processes that enable energy efficiency and
When introducing novel materials for sensors and actuators, recyclability by design. The industry must continue to develop
advances in packaging materials may be needed to maintain substitute materials to replace high-carbon-footprint
required reliability, temperature /humidity control, and materials (e.g., per- and poly-fluoroalkyl substances, PFA).
chemical resistance performance. Significant improvements in sustainability will also be made
through enhanced packaging materials that enable shipping
Photonics: Needs for optical devices are outlined in Chapter at room temperature (molding compound, die attach, flux,
6 and include development of low-loss dielectrics and other substrate, TIMs, adhesives, etc.), lower process temperatures
materials (encapsulants, mold compounds, substrates, etc.), (e.g., epoxy mold compound/die attach cure, wirebonding,
for integrated optical waveguides. In addition, package solder reflow temperatures), and optimize recyclability/reuse.
materials with excellent near-infrared (NIR) sensitivity for Developing trusted methods to quantify improvements and
LiDAR applications will need to be developed. focus resources on the largest opportunities will require
standardized methods of calculating impact by process area
Environmentally sustainable materials: With the trend and material type throughout the supply chain.
towards 75+ billion connected devices by 2030, the
environmental impact is significant, both in electricity
consumption and carbon footprint. The global semiconductor 8.7 Semiconductor Supply
industry must rise to the challenge through environmental,
social, and governance commitments.9,10 The path to net-zero
Chain Ecosystem Roadmapping
emissions will require partnership and transformation of the The semiconductor supply chain ecosystem encompasses the
entire supply chain, including mining raw materials and direct supply chains of all semiconductor actors, from raw materials
material shipment requirements (e.g., low temp storage). to wafers and packaging all the way to microelectronic devices
Other sustainability factors include semiconductor processing in the hands of users—and circularly backwards. It is critical
needs (electricity, water use), circuit board processing, and to the world’s survival and prosperity, and it’s also hugely
methods to reuse and/or recycle products.11 complex, quickly evolving, and highly disruptive to scientific
technological progress. Figure 8.6 provides a high-level
In addition to water recycling and reduced electricity use, overview of the key ecosystem, emphasizing the multiplicity
transformation of the supply chain needs development of new of actor types and their web of interactions.

Figure 8.6: Overview of semiconductor material ecosystem

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 167
On one side, the ecosystem must serve massive demand of functionally specialized oligopolies that rely on massive
for wide-spectrum functionalities, and, on the other side, investments and factories. Table 8.5 provides a sample of this
it must continually prepare for the emerging capabilities concentration across regions, nations, and firms.
and functionalities that keep displacing the not-so-long-ago
dominant ones. Faced with the continual pressure from both For most nations, this has created a dependence on foreign
sides to excel in terms of at-scale affordability, efficiency, semiconductor supply chains that ultimately hurts and
reliability, time-to-market, and sustainability, the industry has threatens their respective economies, public health, and
learned to leverage resources wherever available worldwide. security. Due to insufficient chips in the United States, for
Over the last several decades, the semiconductor supply example, car prices increased nearly 30% in 2021 and were
chain has thus become more globalized, in search of both responsible for one third of core inflation. The chip shortage
specialization and cost savings in different parts of the world. also impacted public health, as medical device manufacturers
could not produce lifesaving products like pacemakers,
Over time, there has been growing concentration of specific oxygen concentrators, respirators, and insulin pumps. The
supply chain capacity within a small group of nations and chip shortage also affected the security of nations around the
regions, as well as within a relatively small number of major globe, as defense capabilities were disrupted, including the
firms. This has transformed the ecosystem into a network engineering of hypersonic weapons, drones, and satellites.

Table 8.5: Current overview of the state of supply chain: key actors by firm, company, region.

Current Dominant Supply Chain Actors (Firms, Countries, Regions)

SK Siltron, Siltronic, Global Wafers, Sumco, and Shin Etsu

Japan, Taiwan, Singapore, and South Korea: 90+% raw wafers

ASML (Netherlands): lithography

Tokyo Electron (Japan): 97% of photoresist coaters and developers, 100% of EUV photoresist coaters and developers

Applied Material, Lam Research, KLA (USA): equipment segments in deposition, etch, lithography

Top 10 foundries: TSMC, Samsung, Global Foundries, UMC, SMIC,

Tower Semiconductor, Powerchip, VIS, Hua Hong Semi, DB HiTek:
All have their largest manufacturing locations in Asia
All but Global Foundries (USA) have headquarters in Asia

Japan, South Korea, Taiwan, China, Singapore: 90% of DRAM and NAND

Taiwan, South Korea: Most advanced chips (100M+ transistors/mm2)

Taiwan, South Korea, China: 80% of headquarters of largest foundries

Global Foundries (US) Micron (US), Infineon (EU): most wafer cap in Taiwan, Singapore, Malaysia

Large IDMs with integrated and service-offering foundries: Intel, Micron, Samsung

East Asia: most chip dicing, assembly, and testing

East Asia: 90% of outsourced microelectronics assembly & test, and used tools

Kulicke and Soffa, Besi, ASMPaciDc, SET:

Their tools are mostly made in China, Singapore, Malaysia, Vietnam

Disco (Japan): market leader in tools for grinding and cutting wafers into chips

China: 60% of chip-packaging volume

Revenue/region: Taiwan 25%, South Korea 18%, China 15%, Japan 13%, North America 13%, Europe 10%, Others 5%

Shin Etsu, JSR, Tokyo Ohka Kogyo (Japan): make all advanced ArF & EUV photoresist

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 168
Worldwide and national economic concerns, as well as The fundamental challenge of the semiconductor supply
national security issues, pose risks to the semiconductor chain ecosystem in the forthcoming decade is to learn how to
supply chain due to geopolitics associated with international transform itself, structurally and operationally, to develop the
trade wars, power conflicts, threats of such conflicts, rapid adaptability, agility, efficiency, resilience, security, sustainability,
demand changes, pandemics, biological threats or attacks, and trustability necessary for thriving within the emerging
cyberattacks, extreme weather events, terrorist attacks, volatile, uncertain, complex, and ambiguous (VUCA) world.
sabotage, and (novel) ‘unknown unknowns’.12 Such events
have already proven to expose significant supply chain The following framework offers a guiding vision to shape
vulnerabilities and fragility at the product, company, national, a transformational roadmap for the semiconductor supply
and worldwide levels. As an example, the Russian-Ukraine chain ecosystem over the forthcoming decade. It condenses
conflict has produced difficulties for the rest of the world in the supply chains into six tiers: clients, electronic devices,
sourcing raw materials, such as Helium, rare gases (Ne, Xe, Kr), packaging, wafer fabs, manufactured materials, and raw
CxFy and SiF gases for etching and cleaning, Cobalt Carbonyl materials (Figure 8.7). It arbitrarily identifies six regions for
for precursors, energy and natural gas, Pd for various chip illustrative purposes. The model contrasts alternative supply
processes and EVs, and Fluorspar for FFKM O-rings. chain ecosystems through three archetypes—global, allied,
and regionalized—and in terms of low versus high connectivity.

Figure 8.7: Contrasting global, allied, and regionalized semiconductor supply chain ecosystems with low vs. high connectivity.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 169
The upper left illustrates a low-connectivity global supply The low-connectivity allied supply chain (upper middle) is a
chain ecosystem. At each upstream tier, a few regions have response to worldwide geopolitical polarization with a few
significant presence in the market. These regions form an blocks of allied regions. It is illustrated here by a red block and
oligopoly for this tier’s market. Active regions in a tier have a a blue block, each with three regions that are not all adjacent.
large node indicating large capability, capacity, and business Each block’s supply chain ecosystem is strictly avoiding any flow
volume, often in global large-footprint heavy-investment between the blocks. This allied ecosystem is essentially identical
factories, notably at the foundry tier. Flows between nodes to its global alternative, yet structurally split in two worlds, each
illustrate that the strategic and commercial relationships with its ecosystem. It offers protection against the antagonist
between regions induce actors from a region in a given tier are block yet forces each block to have all the requisite assets and
mostly supplied from actors in one or two regions. The flows to incur convoluted flows—with all the compromises already
evolve through time, notably due to changing prices, quality, explained in the similarly constrained regionalized ecosystem,
technological capability, demand vs. capacity alignment, in terms of competitiveness, economies of scale, and resilience.
government incentives, and geopolitical relationships. At a Such a semiconductor supply chain ecosystem is currently
high level, the low-connectivity global supply chain ecosystem asserted by many as a promising solution in high geopolitical
essentially represents the current status quo. tension contexts, with suggestions to rely on friendly-shore
supply chains with only friendly and trusted partners. As an
The low-connectivity supply chain (upper right) is not illustration, consider that through governmental plans similar
regionalized, but is instead global. In the displayed extreme to the CHIPS Act, several countries and regions around the
representation, each region has invested to ensure self- world are making significant investment in semiconductor
sufficiency, except for raw materials when there is no manufacturing expansion over multiyear horizons, exemplified
sufficient regional availability. In order to serve the regional by China, European Union, Japan, Russia, and South Korea.
clients adequately, each region must develop the scientific
research, technological innovation, manufacturing capability High-connectivity global, allied, and regionalized supply
and capacity, and the appropriate workforce at all levels. The chain ecosystems (illustrated in the lower part of Figure
actors in each region must do so while offering the product 8.7) gain multi-sourcing and multi-supply options, as
performance, quality, and price customers expect, given their well as lateral transshipment and consolidation options.
comparative benchmarking with other regions. In each active This increases the adaptability, agility, resilience, and
region in a given tier, there is reduced throughput as contrasted sustainability of each of the three global, allied, and
to the global ecosystem, since it is now bounded by regional regionalized archetypes. Manufacturing, logistic, and supply
demand. This lower throughput poses huge challenges, chain innovations are required to evolve from low to high
as most of the manufacturing technology is built around connectivity ecosystems, notably in terms of pan-ecosystem
achieving maximum economies of scale. On the positive side, mindset, platforms, protocols, interfaces, and services. The
each region is protected from disruptions or manipulations most striking improvement from low to high connectivity
stemming from other regions, and the overall supply chain is is achieved with the regionalized supply chain ecosystem
much shorter and thus has the potential to be highly responsive that is transformed from isolated linear regional supply
and environmentally friendly. On the negative side, the mostly chains to an interconnected semiconductor supply grid.
linear supply chain ecosystem is hugely fragile, as any nodal or This creates a shift from highly fragile to highly resilient,
flow link disruption may dramatically hurt the semiconductor going from requiring high robust autonomy capacity with
supply capacity in the affected region, leading to low resilience. low average utilization to lower capacity and higher average
This said, such an ecosystem is currently asserted by many utilization due to plentiful options to face demand peaks and
as the ultimate best solution to enhance regional resilience disruptions. High-connectivity supply chain ecosystems gain by
and security. As an example of this thread, the United States leveraging access to highly responsive and distributed smaller
has made recent significant investments in semiconductor manufacturing facilities, as well as to hyperconnected logistic
manufacturing, such as GlobalFoundries in Malta, NY; Intel networks designed to facilitate swift, efficient, and secure
in Chandler, AZ, and Columbus, OH; Micron in Boise, ID and flows. This is a huge innovation challenge in a world currently
Syracuse, NY; Samsung in Taylor, TX; Skywater in Lafayette, dominated by large players betting on economies of scale
IN; Texas Instruments in Sherman, TX, and Lehi, ID; TSMC in through massive facilities to reach the affordability required
Phoenix, AZ; and planned expansions of pre-existing fabs, partly by customers. Yet, it may be gradually achieved. The first step
sparked by the US CHIPS Act. is leveraging supply chain strategies, such as postponement

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 170
and modularization. Next is the emerging sentient supply chain as the staged transformational pathway from the current
system technologies and the growing availability of chiplet state forward are incredibly complex. Moreover, adding
technology. Finally, with the ultimate emergence of nanochip manufacturing capacity requires high capital investment and
technology, this potential supply chain pivot could be a reality. long lead times. Therefore, it is of foremost importance to
engage as soon as possible in developing digital twins and
Through the next decade, the semiconductor supply chain stress-testing simulation and analytics capability for alternative
innovation roadmap is bound to acknowledge the significant innovation roadmaps for semiconductor supply chains, as well as
gains reachable through a gradual shift toward higher more comprehensive semiconductor supply chain ecosystems.
connectivity—and to invest in making it happen. The roadmap This includes identifying gaps in material sourcing and how this
should also recognize that the global ecosystem model part of the supply chain can be de-risked.
currently dominating the industry has serious pitfalls. In
fact, the combination of geopolitical turmoil and the widely Keys to innovative roadmaps
recognized importance of supply chain resilience and security
• Decrease foreign dependence on extraction, processing,
will lead regions, countries, and firms to migrate toward a
and active material production for semiconductor
hybrid ecosystem state somewhere between the global, allied,
manufacturing.
and regionalized archetypical states. It is key for our industry
to better balance the relative advantages of independent • Replace risky raw materials with new materials and
versus interdependent supply chain ecosystems, building an semiconductor chemistries, sourcing risk-driven R&D.
appropriate mix of interconnected domestic and regional
• Focus on material recovery and recycling.
manufacturing capacity. This will create the resilience needed
to withstand the shocks of today’s world and to de-risk—but
The ultimate aim is to rigorously assess and improve the
not fully decouple—semiconductor supply chains from reliance
current and proposed alternative pathways in terms of
on a diverse set of countries.
adaptability, agility, competitiveness, efficiency, resilience,
security, sustainability, and trustability. Within the emerging
There is huge uncertainty and misunderstanding as to the
volatile, uncertain, complex, and ambiguous world, strategic
compromises and risks at stake. The relative benefits and
decisions must be guided from both private and public sector
pitfalls of alternative supply chain ecosystems models, as well
stakeholders in the semiconductor industry.

Contributors
Katie C. Yu (NXP) – Chair Mary Ann Maher (SoftMEMS) Suresh Sitaraman (Georgia Tech)

Matt Kelly (IPC) – Vice Chair Varughese Mathew (NXP) Ganesh Subbarayan-Shastri (Purdue)

Promod Chowdhury (IBM) Benoit Montreuil (Georgia Tech) Sharad Vidyarthy (Analog Devices)

Michel Koopmans (Micron) Gamal Refai-Ahmed (AMD) Ben Wang (Georgia Tech)

Ravi Mahajan (Intel) David Roberts (Ereztech) Chip White (Georgia Tech)

References for Chapter 8

1
P. Holslin, “What is 6G and What Will It Look Like”, HighSpeedInternet.com, June 2022.
2
W. Saad, M. Bennis, & M. Chen, “A Vision of 6G Wireless Systems: Applications, Trends, Technologies, and Open Research Problems”, IEEE
network, 2019 – ieeexplore.ieee.org.
3
https://www.nxp.com/products/power-management/motor-and-solenoid-drivers/powertrain-and-engine-control
4
https://www.ericsson.com/en/news/2021/9/ericsson-launches-ultra-lightweight-air-3268-radio
5
Refai-Ahmed et al, 2022 EPTC “Invited Talk: Pathfinding to Maximization of AI/HPC/GPC System Performance”
6
G. Daves, iMAPS 2022 Keynote,“6G: Opportunities and Packaging Challenges.”

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 171
7
G. Daves, iMAPS 2022 Keynote,“6G: Opportunities and Packaging Challenges.”
8
G. Refai-Ahmed et al, “Holistic Understanding of Best Engineering Practice to Extend Cooling Limit of Next Generations of GPU” 2022 EPTC
9
https://www.mckinsey.com/industries/semiconductors/our-insights/sustainability-in-semiconductor-operations-toward-net-zero-production
10
European semiconductor industry reduces its fluorinated greenhouse gas emissions by 42 percent in Europe during the last decade: https://
www.eusemiconductors.eu/sites/default/files/ESIA_PR_PFCEmissionReductions.pdf
11
“Chasing Carbon: The Elusive Environmental Footprint of Computing” U.Gupta, et al. https://arxiv.org/pdf/2011.02839.pdf
12
Kaplan, et al., “The Risks You Can’t Foresee”, HBR, Nov-Dec 2020, pp 40-46

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 172
Chapter 9

Design, Modeling, Test, and

Standards
9.1. Introduction electronic design automation (EDA) tools do not comprehend
3D integration of mixed domain and mixed technology
Designing, manufacturing, and deploying 3D HI SiPs circuits at a level of complexity now predicted for advanced
that combine the strengths of best-in-class components 3D HI systems. These design tools were created for planar
will catalyze a new era of innovation for applications electrical circuits manufactured on a common IC substrate or
including data center, HPC to mobile, communications for printed circuit boards that never had to consider billions of
and infrastructures, edge and IoT, automotive, bio/health, components integrated on an IC.
defense, and harsh environment—plus others that may not
yet be known to us. 3D HI SiPs carry with them the promise A key enabler for the semiconductor industry will be an EDA
of lower power consumption, higher performance, higher portfolio that gives chip and system designers capabilities to
reliability, and lower costs. At the same time, 3D HI SiPs also explore and optimize across metrics of performance, power/
give designers the flexibility to use best-in-class technologies energy, area/volume, reliability, security, and safety. By
without the compromise of trying to make all technologies demanding new ways of thinking about software architecture,
work on a common chip manufacturing process. algorithms, simulation/emulation hardware, and cloud
architecture, this forward-looking view on EDA will also be an
Before 3D SiPs can be manufactured, they must be designed. application driver for the very chips and hardware where EDA
Next-generation 3D HI SiP designers will require new design tools are run.
tools and data paradigms to enable co-design of mixed
domain chiplets (including digital, analog, mixed signal, Defining such a roadmap—with both an “enabler” and a “driver”
power, photonics, and MEMs) in a common package. Existing view—on a 5- to 15-year horizon is the scope for this chapter.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 173
 Figure 9.1: System of Chips Figure 9.2: Journey of system creation

Key shifts for the expansion of design • AI and machine learning will play an increasingly important
automation tools role in design of complex systems and will also provide
new scaling drivers for system in the post-Moore’s era.
• Multi-domain 3D SiP design, verification, and test
methodologies: System of chips (or chiplets) is the new SoC, • Materials: The incorporation of new materials into the
with electronic-photonic-MEMS co-design becoming the manufacturing processes will require advances in modeling,
new mixed-signal design paradigm (Figure 9.1). simulation, and design tools.

• Automation and collaborative co-design: System-level full- • Standards for 3D design and manufacturing: The industry
lifecycle robust design and optimization from material and must agree upon hardware interface standards for
process co-optimization will be employed through design combining multi-domain 3D chiplets in a SiP, supported by
of devices, circuits, chiplets, interposers, and packages. design automation tools and methodologies.
The design process is complex and needs to comprehend
• Security, requirements tracing, and lifecycle management:
co-optimization of both design and manufacturing
Security must continue to reap benefits from an increasingly
processes, assembly and test, and post-manufacturing
complex semiconductor ecosystem (Table 9.1).
tuning (Figure 9.2).

Table 9.1: Industry trends

Present Future
More compute/ intelligence/ communication in more places;
Data center demand remains strong
consumer (mobile, gaming), self-driving cars, cell towers, IoT
3D/hybrid package architecture emerging with standardized
2/2.5/3D Interconnect scaling continues
chiplet-to-chiplet interfaces/functions
Heavy customization Standardization
Thermal and power management at material, circuits, chiplets,
Thermal and power management mostly at component level
and system levels—proactively and early
Electrical-mechanical-thermal-photonic co-design and co-
Qualitative architecture decision-making
optimization
Design implementation is main bottleneck Verification gap continues to widen
Deterministic design Variation-resilient design
Some limited metrologies In-line metrology and data management
Controlled supply chain Security and trust in a complex and fragmented supply chain
A design/manufacturing problem A full lifecycle problem where AI should help more
New models and abstraction levels with hierarchical
Compute farms and parallel processing
verification strategies

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 174
The MAPT roadmap recognizes that design and manufacturing Industry musts to enable multi-domain 3D HI SiPs
are dependent upon each other and the more complex
• Reconcile and unify different domains’ (electronic, photonic,
the system, the greater the opportunities for design and
MEMS, mechanical) data, nomenclature, and semantics.
technology co-optimization (DTCO). This is especially true for
multi-domain 3D HI SiPs. • Establish version control methodologies for large projects
integrating multiple technologies, with each component
Requirements for the design and manufacturing moving through various revisions as multiple design teams
of advanced packaging-based 3D HI SiPs work independently and asynchronously.

• Agreed-upon hardware architectures and interfaces, • Add new schemas that comprehend the aspects of different
including the package and interposers material systems, packaging, and connectivity (electrical,
photonic, fluidic) used in 3D HI SiPs.
• Agreed-upon manufacturing, assembly, and testing
processes and associated design rules • Capture materials, assembly, and manufacturing process
constraints in the form of design rules that can be used by
• Design automation tools and methodologies for co-design
EDA tools to replace manual design, implementation, and
of multi-domain 3D HI SiPs
verification steps.
• Libraries of qualified and trusted building blocks (chiplets,
• Investigate new tool architectures and data representations,
interposers, and packages)
such as modular flat-file interfaces that are programming-
• New material and mwulti-domain 3D HI data models, language and operating-system neutral, to remove potential
simulation models, data formats, nomenclature, and data barriers to software development; the industry should
that include the package and interposers as part of the agree on standard description languages.
design, as well as different forms of design parasitics
(electrical, noise, thermal, loads, impedance, etc.) To achieve these benchmarks, the industry will need
to agree on several standards and methodologies.
• Methodologies and infrastructure to enable collaborative
work across multi-company, multi-domain, geographically 1. Functional verification methodologies to drive required
dispersed teams with shared data and resources types of modeling and data abstraction views:

• Enhancing CAD tools to include multi-domain co-design and

9.2. Multi-domain 3D SiP analysis in 3D dimensions

Design, Verification, and Test • Modeling for 3D mechanical assembly, stress, thermal, and

Methodologies bending that occurs during manufacturing and product use,

which will drive 3D placement constraints of components
The industry has designed 3D HI SiPs using standard 2D IC,
• Modeling abstraction levels and how they are to be used
board, and packaging CAD tools, but it required herculean
in different combinations (stiction or ALD modeling and
efforts and employed mostly manual optimization and
materials models up to software/hardware co-design)
physical prototyping to do so. More than four decades and
hundreds of thousands of person-years have gone into the • Ensuring modeling abstractions are consistent and
creation of design automation tools for electronic board composable (e.g., FEM simulations consistent with SPICE), as
and IC design. Similar but more modest efforts have taken well as models that are consistent and numerically well formed
place for packaging, MEMs, and photonic ICs. Each of these (e.g., modeling overpressure in microphones that cause SPICE
efforts resulted in their own unique design methodologies, simulations to glitch when simulating drive/sense loops)
data models, application programming interfaces (APIs), data
• Establishing standard verification IPs and protocols for
formats, and nomenclature. Standards evolved during this time,
acceptance testing of chiplets and packaging data
but few—if any—data or interface standards exist for design
flows comprising packaging, 3D HI SiPs, or co-design of multi-
2. Hardware interface standards for combining multi-domain
domain systems.
chiplets in a SiP, such as the universal chiplet interface
express (UCIe):

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 175
• Electrical/optical interconnect fabrics and interfaces
between mixed domain and mixed material chiplets,
9.3. Automation and
interposers, packages, and boards, including analog and Collaborative Co-design
digital signaling
Since chiplets in a SiP can themselves be systems-on-a-
• Expanding upon concepts such as Networks-on-Chip (NoC) chip (SoCs), the complexity of a SiP can be considerable,
or Networks-on-Interposer (NoI) to adopt new power representing Systems-of-Systems. The industry needs to
distribution and thermal management methodologies for research and employ advanced automation capabilities
3D HI SiPs for collaborative co-design, optimization, assembly/
implementation, and verification of these complex multi-
3. 3D HI SiP test methodologies for pre- and post-manufacturing domain 3D HI SiPs.
and assembly:
The more complex the SiPs become, the harder it is for
• Incorporating multi-domain design-for-test methodologies
designers to explore and trade off different architectures
that delaminate test strategies by domain, including
that could be employed. As SiP design and verification
standard fault/failure modes, spec-based testing, etc.
methodologies become more mature and the industry solidifies
• Standardizing hardware design-for-test architectures, on shared data models and schemas for representing multi-
including concepts such as built-in self-test domain 3D systems, the industry should shift focus to more
advanced automation.
• Enabling controllability and observability through test
architectures
Advanced automation to foster 3D HI SiP design
• SiP failure mechanisms and data, along with test methods
• 3D multi-domain co-design and implementation (including
and scoring metrics for yield, assembly optimization, and
comprehending SiP assembly process and design rules for
system-level multi-domain testing
data impacting foundry and packaging design kits)
• Methods for measuring and simulating chiplet, packaging,
• Adding enhanced parasitic extraction for the entire
SiP, system reliability, and lifecycles
system, including the packaging and interposers used, that
• Methods for securing and encrypting chiplet, package, and encompasses multiple energy domains (electronic, thermal,
interposer test and debug data magnetic, photonic, and fluidic)

• Creating commercial design tools to automate in-system • Guided or automated 3D multi-domain architecture
sensor selection and placement with infrastructure exploration and system partitioning with packaging included
automation to connect measured units to a processor with as part of the system (affecting data relating to abstractions
embedded software capable of making decisions about self- levels and supported models)
healing as a system ages
• Synthesis and optimization as directed from constraints
• Methodologies and architectures to improve overall system developed during architectural design
reliability (self-checking and healing systems that make use
• Use of AI and machine learning optimizations as appropriate
of redundant interconnect and processing blocks)
to the tasks, which will require relevant research for model
• Creating methodologies for testing of mechanical optical creation
fiber alignment and accelerated lifecycle to determine
impacts of materials changes with temperature, aging, To support multi-domain 3D HI SiP designs, scalable
vibration, stress, and system activity collaborative design environments are needed. Emerging
designs will require disparate teams from different companies
Finally, the industry needs to agree upon methodologies in geographically dispersed regions of the world to work
and methods needed for post-manufacturing tuning of SiPs, together and share access to chiplet and packaging IP
especially for systems containing analog/mixed signal, MEMs, from multiple suppliers. Startups, small and medium sized
and photonics chiplets. Additionally, tools and methods to entities, and educational institutions must also be enabled to
address post-manufacturing flexibility will enable solutions to participate in the ecosystem. Emphasis should be placed on
target multiple applications without new silicon chips.
Steps to create scalable, collaborative design environments

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 176
• Establishing, storing, and searching centralized libraries of We envision the need for novel software, design, and
chiplet-based functions for SiP design (implying the creation measurement tools to characterize materials in new ways
of a new ecosystem of suppliers and requirements for for simulation, including prediction under bending and
chiplet qualification and acceptance criteria) stretching for flexible packaging used by wearables. Materials
manufacturing compatibility design rules need to be created
• Establishing, storing, and searching centralized libraries of
and incorporated into architectural tradeoff, synthesis,
packaging and interposer options for SiP design (implying the
and optimization design tools, as well as those tools used
creation of a new ecosystem of suppliers and requirements
by manufacturing professionals. New tools are needed
for packaging qualification and acceptance criteria)
for ensuring performance of materials within expected
• Standardizing chiplet and packaging IP-usage licensing environments, such as fluids and biocompatibility for
terms and conditions implantable systems.

• Developing cloud-based design environments that support

In the longer term, tools are needed for materials
multiple globally dispersed teams of different companies and
optimization, engineering, and discovery to achieve desired
disciplines working together using different abstraction levels
properties by design. This will require design at the nano
of shared data
and atomic levels, as well as cooperation between material
• Enabling flexible cloud-based environments that scientists and manufacturing engineers, along with new
offer scalability in both computational and capability models and massive amounts of simulation driving a need for
resources, with pre-packaged design automation tools in a new compute power. Some tools exist in related fields, but
collaborative environment that ensures confidentiality uptake within the semiconductor space has been slow.

Consortia such as SCALES need access to a streamlined, Standards must be set to enable interchange of materials and
project-centric, cloud-based environments that reduce the 3D-data between various entities involved in SiP design and
cost of entry and ownership of design environments. A hosting manufacturing. Key drivers include the multiple physics
organization could field requests from consortia members field nature of the design and a need to design in 3D.
to allocate credits, freeing members from establishing and Additionally, standards are needed for process/materials
maintaining costly hardware infrastructure, tools, licensing, data exchange (types of data, units, how to measure key
and the necessary specialized skills. Such a design environment metrics), as well as to document behavior of materials in new
could be highly automated, while also maintaining specialized ways (bending, stretching, etc.). It will also be important for
flows for reuse. There is opportunity for automation in manufacturers to quickly determine compliance with health and
scheduling, with cloud-based environments offering the scale safety standards and requirements for proposed new materials.
that no on-premises computing infrastructure could rival.
Similarly, members that consent can contribute to building AI/ Standards must also be developed for package-provider data,
ML models, significantly extending their lead. such as libraries with relevant 3D data for design, assembly,
analysis, and test. Some work has been done in this area,
with beginning work on packaging, but the work is far from
9.4. Materials, 3D Data, and over. A similar situation exists for chiplets standards, including

Data Standards for chiplet provider data (libraries of electrical, photonic, and
MEMs chiplets for SiP design). Additional standards that will be
New materials will be key to driving innovations in required include the following:
manufacturing of multi-domain 3D HI SiP devices to achieve
• SiP assembly and test data (Assembly Design Kit), which
needed performance and requirements for new applications.
includes 3D assembly design rules, plus all 3D CAD views for
The incorporation of new materials into the manufacturing
the SiP design and implementation flows
processes will require advances in modeling, simulation,
and design tools. Other important issues include materials • Connectors that carry non-electrical signals, such as fluidic
compatibility within a fabrication process sequence and whether signals, as part of assembly
proposed materials are allowable within a manufacturing facility.
• Photonic and MEMS Process Design Kits (PDKs) that
For example, some materials used in MEMS manufacturing are
are more complex than IC PDKs, as wafer preparation
not compatible with IC manufacturing environments.
information is needed, and material properties in multiple
energy domains must often be supplied

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 177
A challenge in providing standards for manufacturing of Lifecycle Management
HI devices is that there are often no standard fabrication
The MAPT roadmap recognizes the need for extending design
processes as in the IC world, and there are no standard
and manufacturing thinking to beyond time-zero—into full
primitives out of which devices are made. Chip fabrication is
lifecycle of deployment—to detect and mitigate in-field
highly application-dependent or, as with sensor chips, based
variations. Lifecycle management of 3D chips requires:
on the device physics used (magnetic, mechanical, optical,
etc.). We do see some standardization in packages for certain • Pre-manufacturing design verification and validation
types of devices, but we are far from a one-size-fits-all world.
• Post-manufacture testing and tuning

• In-field performance monitoring and adaptation to electrical

9.5. Security, Requirements degradation

Tracing, and Lifecycle Pre-manufacturing design verification and validation

Management Future 3D HI SiPs will integrate digital circuitry with multi-
With the establishment of a 3D IC ecosystem, the business domain analog, RF, MEMs, and photonic subsystems. While
model will embrace globalization for lower cost and shorter there are advanced tools for digital design verification and
time-to-market. To ensure the security of 3D IC devices validation, the current state of the art for mixed-signal circuits
during their prolonged in-field operations, it is essential and systems is perhaps a decade behind corresponding tools
to implement solutions that can protect against potential for digital systems.
threats from untrusted components and external
malicious intent. Supply chain and associated hardware and Evolution of algorithms, methods, and techniques
software security issues will need to be addressed, and design
• Design verification and validation of 3D HI SiPs and
tools will need to be created to check chiplet and SiP adherence
packages
to security policies associated with various threat surfaces. This
subject is covered in depth in chapter 3 of the roadmap, but • Applying existing digital verification techniques to digital-
it should be noted that such tools at this point are in their compatible representations of mixed-signal systems
infancy and will need to be developed and matured.
• Developing new representations for analog performance
in mixed-signal systems
Requirements Tracing
• Use of optimized stimulus for stressing the performances
Many life-critical end-market applications, such as systems in
of SiPs and packages, both pre- and post-manufacturing
automobiles or medical equipment, have strict requirement-
tracing policies to ensure that specific requirements are met • Diagnosing design bugs and correcting them, reducing
throughout the system lifecycle. the numbers of re-spins to lower manufacturing costs

Needed end-market methodologies and design- Post-manufacture testing and tuning

automation tools
Defect models for SiPs and packages must be developed.
• Requirements capture Conventional catastrophic failure and timing-based
defect models for digital circuits and systems need to
• Identifying the software and hardware system components
be augmented with defect models for heterogeneous
that address each specific requirement
systems that include parametric and catastrophic defects in
• Simulation to confirm specific requirements are met pre- subsystems, as well as interconnect and vias.
manufacturing
Developing new design-for-test (DFT) automation tools with
• Testing, measuring, and analysis to ensure each requirement
novel test stimulus generation algorithms will enable the
is met post-manufacturing
testing of mixed-signal and mixed-technology component
• Ensuring controllability and observability of all blocks, performance. This needs to be supported by appropriate
fulfilling key requirements that are buried in the overall SiP DFT infrastructure for controllability and observability

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 178
 of embedded signals, with minimal impact on device work concurrently on blocks of the design and then assemble
performance. Placing complex equipment like spectrum them in a top-level floorplan where they are again auto-
analyzers on-chip for performance assessment is impractical routed together. Manufacturing design rule checking (DRC)
and expensive. Indirect, machine-learning-assisted test and layout-vs-schematic (LVS) checks are run throughout the
techniques are needed that allow monitoring of subsystem design process and again at the final stages before tape-out
specifications without the use of on-chip specification to the mask shop supporting the foundry of choice. Functional
measurement hardware. Finally, low-cost techniques are verification is done at several levels, including instruction
necessary for post-manufacture tuning of chip-package level with behavioral models, gate level, and transistor level
performances. Such tuning must be fast and allow maximal for critical logic, using a variety of simulation engines that
yield recovery even under large process excursions. can co-simulate with each other. Digital teams also make
use of parasitic extraction tools, static timing analysis, and
In-field performance monitoring and adaptation to electrical optimization software to improve the overall performance of
degradation the designs. These tools are closely tied to the placement and
routing tools.
Completely autonomous techniques that detect and correct
both transient soft errors, as well as performance deviations
Analog Design
induced by electrical degradation and thermal effects, are
imperative for next-generation SiPs and packages. Thermal Analog circuits are typically implemented using custom
effects can cause significant performance degradation of design flows. Custom flows start with a schematic and employ
advanced high-speed electronic systems and packages. schematic-drive-layout (SDL), which allows the designers to
Online error detection techniques, such as those based on keep track of connectivity while doing layout. Layout is semi-
functional or algorithmic encodings of digital and mixed- automated and iterative, with the layout engineer moving
signal systems, may be used for this purpose. Error mitigation layout components in an interactive editor. Design components
is achieved through judicious use of redundant computations are typically represented as parameterized cells that change
(transient errors) or online tuning of circuit-level parameters their layouts based on parameters as set on component
(thermal effects/electrical degradation). New design instances in the schematic. Then, specialized analog routers
automation tools are needed to help designers synthesize and semi-automated interactive routers are used by layout
these autonomous techniques into their systems and to detect engineers to complete connectivity. Circuit-level functional
areas of the SiP that are still susceptible to degradation over and performance verification is done using parasitic extraction
anticipated electrical and thermal operating conditions. tools and SPICE simulators at the transistor level. For circuit
optimizations, either they are done by hand or semi-automated
optimizers are used. DRC and LVS are run similarly to digital
9.6. State of the Art design but with more extraction of layout parameters to
ensure layouts indeed match designer intent.
The design automation community currently supports robust
design tools for digital, analog, mixed-signal, and RF IC design.
Mixed Signal Design
While these ICs have many layers, the design tools traditionally
manage the design in a 2D view where layer thicknesses are Analog circuitry that is included in larger Systems-on-Chips as
abstracted away from the designer. Exceptions to this are blocks placed next to the digital logic of the IC but with different
at the semiconductor process level, including Technology power/ground supplies is known as mixed-signal design.
CAD (TCAD) in full 3D mode, as well as high-speed RF and Functional verification for mixed-signal designs is performed
microwave applications where 3D solvers are employed to get using SPICE with Verilog-A behavioral models or with specialized
accurate predictions of parasitics and performance. behavioral models like IBIS/AMI or even MATLAB.

Digital Design RF and Microwave Design

Digital designs are typically the most automated, starting RF and microwave design also follows an SDL-based flow with
with a high-level description of the IC logic in Verilog, DRC and LVS. But, in contrast, these flows use specialized
followed by logic synthesis and optimization, and then auto- solvers for parasitic extraction and SPICE engines for signal
placement and routing. Large designs are typically done in analysis. They may also use specialized interconnect routers
a hierarchical fashion that enables multiple design teams to for high-speed interconnects and electrical waveguide routing.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 179
Photonic IC Design Verilog-A, System Verilog, VHDL, LEF/DEF, Liberty, SPEF, GDSII,
OpenAccess, and OASIS—all of which are still supported
Integrated photonic ICs (PICs) now also follow an SDL-based
today. Most design automation standards currently in use
flow, complete with DRC and LVS for both electrical and
are focused on IC design from a 2D top-down point of view,
photonic connectivity. PICs include the use of waveguides
and there are no real design automation tool interface
to move light through the chip, as well as metal traces
standards for 3D type designs.
for electrical connectivity. Specialized curvilinear shape
engines are employed with automated and semi-automated
HI SiP Design
waveguide routing. Functional verification of PICs is done
using either specialized photonic circuit-level simulators or SiPs have been implemented using a combination of 2D IC
sometimes SPICE with Verilog-A behavioral models. In the design tools, printed circuit board tools, spreadsheets, and
Verilog-A case, specialized port replication must be done to scripts until the early 2020s. More recently, design tools have
transmit the additional signal information carried by photonics been introduced specifically for 3D IC design in anticipation of
that are not realized in electronics. Co-design of PICs with the move to chiplet-based SiP designs. These tools deal with
analog drivers/receivers is done through co-simulation of 3D assembly of complex SiPs. Initial designs combined digital,
SPICE and the photonic circuit-level simulators. memory, and analog chiplets, while current work includes
chiplets from different material systems and domains,
MEMs Design including integrated photonics and MEMs.

MEMS design, simulation, and verification produce challenges

due to multiple physics field interactions in device working 9.7. Limitations with Current
principles, 3D device motion, and the varying time and length
scales of the MEMS device behavior. MEMS products may
Technology
require the use of new materials, new fabrication processes,
The fundamental limitation of all design automation tools
new device designs, and custom packages.
is the lack of data in standard formats with an agreed
syntax and semantics for what the data represents
Current tools utilized by MEMS designers include those for
and how it is to be used. In general, it’s not possible to
material modeling, characterization, and design. FEM (finite
automate a “non-process”. The implication is that to create
element method)/BEM (boundary element) tools are used to
full automation tools for complex HI SiPs, there must be
analyze the device motion and predict device performance in
agreement on the data to be used and the processes to
multiple energy domains. Specialized tools employing other
implement SiP systems. Throughout this chapter it has been
mathematical methods are used for RF MEMS and Optical
noted that a lack of industry agreement on t hese areas will
MEMS devices. Because the manufacturing process and
jeopardize the ability to create such systems.
device are often co-designed, fabrication modeling software
creates 3D CAD models from a device layout and a fabrication
Key design automation gaps and investments needed to
process description. These models are then passed to the 3D
fully support SiP design are listed in Table 9.2. In general,
simulation tools for analysis. The package may be part of the
the industry must work on improving design automation
device’s function and open to the environment, so co-design
infrastructure to comprehend mixed domains, new materials
of the package and MEMS is important.
and processes, and the 3D nature of 3D HI SiPs. Necessary
improvements include design and verification methodologies,
System-level tools are available in MEMS like those used
data models, application programming interfaces (APIs), PDK
by analog circuit designers, including MEMS/Electronics
and ADK library data content, and data interchange formats
schematics and simulation using languages like Verilog-A and
(syntax and semantics). Design automation solutions will
SPICE. Physical verification tools, DRC, extraction, and LVS
require large, disparate, mixed-domain, and geographically
have been enhanced to cover multiple physics domains.
dispersed design teams from multiple companies to be able to
work together on SiP designs.
Design Automation Standards
In the late 1980s and early 1990s, an effort was made to These design automation work areas must be coordinated
work on standards for interoperability between the various with additional efforts by the industry to adopt standard
design tools. This resulted in standards such as EDIF, Verilog, fabrication processes and to characterize new materials that

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 180
would further enable new design tools for simulation and different—and often competing—priorities and agendas
predictive SiP functionality and performance. for how to move forward. There needs to be a pulling force
or goal that unites them to move in the same direction,
Lastly, design automation tools also need to adopt the use much like the moon shots of the 1960s.
of the very systems that are enabled by SiP designs, such
Future trends in design automation include the increased
as cloud-based massive parallel computing, as well as HPC
use of cloud-based simulation tools, hardware accelerators,
and AI/ML hardware accelerators for exploration of the
and Digital Twins. As PICs and MEMS mature, characterized
complexities arising from 3D HI SiP designs.
IP blocks and standard processes will become available,
enabling top-down design and simulation approaches plus

9.8. Challenges, Future Needs, more accurate and complete PDKs and ADKs. Standard
fabrication processes with well-characterized materials
and Possible Solutions will allow more widespread and accurate use of statistical
analysis, optimization, and synthesis tools. Reduced order
Technical challenges are numerous, spanning from basic
modeling will also mature with more nonlinear effects
materials development to full system implementation and
and multiple physics domain models, with cross-coupling
verification, including architectural additions for improving
between the domains being modeled more accurately.
system security and reliability. The most difficult challenge,
however, is coming up with a way to marshal and organize Table 9.2 is a brief overview of the key areas of investment
the forces of a diverse ecosystem of companies who have needed for 3D HI SiP design.

Contributors
Mitchell Heins (Synopsys) – Chair Antonio de la Serna (Siemens EDA) Sung-Kyu Lim (Georgia Tech)

Min Tsao (Siemens EDA) –Vice Chair Farimah Farahmandi (University of Florida) Patrick Madden (SUNY Binghamton)

David Landsman (Western Digital) –Vice Chair Yousef Iskander (Microsoft) Mary Ann Maher (SoftMEMS)

Ashraf Alam (Purdue University) Steve Hoover (Redwood EDA) Ming Zhang (PDF Solutions)

Abjhit Chatterjee (Georgia Tech) Mohamed Kassem (eFabless)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 181
 Table 9.2: Key industry investment areas

Investment Areas Short Term (5 years) Medium Term (10 years) Long Term (15 years)
Design Automation, • 3D-HI SiP design • Chiplet and package version • Constraint-driven
Functional Verification, methodologies control • 3D HI SiP placement and
Physical Verification • 3D SiP assembly tools • Advanced parasitic extraction routing
for all design domains
• 3D SiP simulation
• Design/technology co- • Architectural design
• SiP thermal analysis
optimization exploration tools
• SiP parasitic extraction
• Automated or directed AI/ML
• SiP DRC/LVS tools system synthesis
• Cloud-based design
environments
• Better reduced-order
modeling algorithms
Materials, 3D-data, • New materials • Standardize nomenclature, • Network on chip
and Data Standards, characterization tools and 3D HI data models,
Data Interchange, • New design rules for • Standards for process/
and Hardware materials manufacturing materials data exchange
Architectures compatibility
• Reconcile data models
• Reconcile modeling and • Tools for materials • Network on interposer
abstractions engineering, optimization, • Inter-chiplet photonic bus
and discovery
• Inter-chiplet interfaces interfaces
• Power distribution
architectures
• Standards for photonic and • Establish central chiplet, • Wafer-level stacked
MEMs PDKs packaging, and materials interposers in package
libraries • Self-diagnostic, self-healing
• Massive parallel compute system architectures
resources for materials
simulation
3D HI SiP Testing • Test methodologies per • Chiplet and package • In-package test structure
domain (electronic, photonic, acceptance testing synthesis
Design-for-
MEMs) • SiP manufacturing stochastic
Manufacturing • Standard failure models and
• Post-manufacturing tuning metrics data modeling
Design-for-Test methodologies • Design-for-test architectures • Monte Carlo Analysis for yield
like scan and BIST for each prediction
domain
Security • Establish methodologies for • Commercial SiP security • Synthesis of SiP security
creating secure SiPs scanning tools architectures and protocols
Requirements Tracing
• Facilitating trusted supply • In-system self-diagnostic
Lifecycle Management chains and security IP vendors security checking
• Establish SiP security • Research SiP
scanning techniques, AI-based threat surface
detection
• Establish SiP security
standards and standard
metrics

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 182
Chapter 10

Manufacturing and Process

Development Metrology
10.1. Introduction 10.2. Key Trends in Metrology
This chapter describes the characterization and metrology Metrology is fundamental to developing new materials and
requirements for all areas of the Microelectronics and Advanced devices that achieve grand objectives such as reduced energy
Packaging Technology (MAPT) Roadmap, including Materials usage, improved miniaturization, and faster logic processing.
and Devices through Advanced Packaging and Heterogeneous With exploratory research into new materials, metrology
Integration and Systems. Metrology measurements enable methods must provide atomic-level resolution of the
all aspects of semiconductor materials and device research, structure and identify defects and impurities, while also
development, and manufacturing. Exploration into new determining the function relationships between electrical
materials and structures is metrology-intensive, and metrology properties and physical characteristics.
use increases as process technologies become more mature.
Offline, at-line, and inline metrology include all aspects of Metrology methods are challenged by the near-term (next
physical and electrical measurements and can span length-scales 10 years) measurement needs for new materials, structures,
from atomic to macro measurements (see NIST report ). 1
devices, and processes. The critical link between process
and metrology is a key element of successful metrology
Although metrology is defined as “the science of measurement”, R&D. Measurement methods are often specific to crucial
the semiconductor industry typically uses the term process areas such as patterning, front-end processes, on-chip
“characterization” for lab-based capabilities and “metrology” interconnect, chip-to-chip interconnect, and packaging.
for in-fab capabilities. For this chapter we will use the term
“metrology” with its original definition to cover both segments.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 183
 Figure 10.1: Metrology landscape, edited from Markus Kuhn, VLSI Metrology Workshop 2020.

A key trend in metrology is the convergence of capabilities be difficult to achieve with 3D structures. An example of such
between lab and fab. The need to quickly provide information a challenge is the development and process control of through
to control IC fabrication is driving analysis capabilities such silicon vias (TSV). This technology has been in development for
as Big Data and machine learning into the field of metrology more than a decade and, although advances in metrology have
for semiconductors. The need to correlate local device enabled progress, there are many remaining challenges.
measurement at near-atomic scales to die- and wafer-
level information requires improved measurement speed More recently, fusion and hybrid bonding have emerged
and more statistically relevant data. This, in turn, requires as strategic bonding technologies in 3D integrated circuit
advanced measurement capabilities and improved test technology (3DIC)2. Surface roughness/recess depth, bond
structures, which then correlate to electrical properties. energy, and overlay measurements are critical, as is void
This is summarized in Figure 10.1. detection at bond interfaces. AFM is used to ensure sub-nm
surface roughness and recess depth of bond pads. Bond energy
Another recent trend is the characterization of new materials is presently monitored by a variety of techniques, including
shown to impact adjacent materials properties. This illustrates crack initiation and measurement, shear test, and four-point
the importance of understanding the interconnected bend. Voids are typically monitored by Confocal Scanning
intricacies of newly conceived device structures made with new Acoustic Microscopy (CSAM), while transmission IR is utilized for
materials. Materials characterization must advance to improve bond overlay measurements. Some promising new metrology
spatial resolution while maintaining statistical significance. technology for this includes THz imaging and microwave
characterization for highly integrated systems. On the electrical
Additionally, there is the evolution of 3D packaging and measurement side, advances in Known Good Die (KGD)
heterogeneous integration, which provides a critical techniques are necessary to ensure high yield and performance.
challenge for physical and electrical measurements.
Physical methods such as SEM/TEM microscopy require Another trend associated with the increased prevalence
destructive preparation of samples, while non-destructive of 3D structures comes from the multilayer film and chip
X-ray microscopy has spatial resolution requirements that may stacks. Two prominent examples of considerable importance

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 184
to metrology equipment suppliers are the vertical stacking of
n and p MOS devices predicted sometime in the next 10 to 15
10.3. Metrology for Devices
years, as well as increased stacking of multilayer films with very Both process development and manufacturing require
high aspect-ratio holes. A central aspect to metrology for these advances in characterization and in-fab metrology. As the
structures is the need for fundamental materials property challenges associated with 2D scaling increase in difficulty, 3D
information for the nano-scale structures at a much wider range structures are expected to provide scaling solutions for both
of wavelengths (from the IR to EUV to X-ray) and electrical logic and memory devices. Leading edge transistor structures
properties. Defect detection is greatly challenged by the need are expected to transition from nanowire/nanosheet FETs
to provide statistically significant information from devices with to forksheet and then to CFET designs. The forksheets are
decreased feature dimensions and higher aspect ratios. vertically stacked nanosheet channels with the n-FET and
p-FET separated by a dielectric, and the CFETs have the n and
The inclusion and continued advancement of unique facilities at p sheet channels stacked vertically for the CMOS structure.
NIST and the DOE National Laboratories are critical for complete These new transistor structures embody all of the challenges
characterization of new materials and structures . The
3-7
listed in Table 10.1 on the next page.
Synchrotron Ultraviolet Radiation Facility (SURF III) is a unique
NIST facility for advancement of EUV Lithography. Other key 3D memory devices like 3D NAND already have more than
NIST facilities include the Center for Nanoscale Science and 230 layers and are expected to increase to 500 layers and
Technology (CNST), Boulder Microfabrication Facility, and the beyond, using high-aspect-ratio structures for metal contacts
related Precision Imaging Facility. The Laboratories at NIST, that extend to the bottom of the film stack. These 3D
such as the Physical Measurement Laboratory and Material memory structures provide examples of how new structures
Measurement Laboratory, provide crucial capabilities. For are driving advances in metrology. The first commercial
example, NIST is working on best-in-the-world measurement use of IR scatterometry and critical dimension small angle
of material optical properties over broad frequency ranges. X-ray scattering (CDSAXS) was for process control for the
NIST also has a wide range of materials characterization high-aspect-ratio contact hole etch process. Research into
capability through a suite of beam lines at the Brookhaven the materials and structures that will eventually result in 3D
National Labs NSLS-II facility. Each US National Laboratory DRAM are also pushing advances in metrology. New memory
has a DOE user facility with a variety of different capabilities. types such as ReRAM, as well as innovative approaches to
Another DOE facility providing advanced microscopy capability memory, are driving physical and electrical measurements.
is the National Center for Electron Microscopy. Several URL The use of spiking signals for the artificial synapses found in
links are provided at the end of this chapter. neuromorphic circuits is an example of new electrical testing.

Through NIST, the necessary reference materials and Defect detection for future IC generations is challenged by
standards for a multitude of metrology measurements both dimensional scaling and high-aspect-ratio structures. The
can be provided for advanced metrology in the near need for increased spatial resolution and higher throughput
term, and exploratory research into new measurement is driving the introduction of multi-electron beam systems,
methods can be done in collaboration between academia, where multiple electron beam systems scan the wafer in
characterization and metrology equipment suppliers, and parallel. The increased complexity of this approach raises many
IC manufacturers. practical challenges, including the need for high system uptime.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 185
 Table 10.1: Illustration of the current state of the art and future needs for different metrology requirements.

Metrology Technology Current 5 years 10 years 15 years

Atomic-level Aberration- Advanced Aberration-corrected Continued Continued
characterization of new corrected electron SEM improvement improvement
materials and devices STEM diffraction via invention
methods AI/ML analysis of
Automated characterization data,
FIB sample Advanced i.e., strain analysis
preparation energy
with consistent dispersive ML-based analysis
lamella X-ray of crystal phase
thickness spectroscopy and orientation in
nanostructures
APT Backscattered
SPM electron Reduced time to
diffraction analysis
Methods capable of Optical ML-based Increase in wavelength Increased X-ray Continued
controlling manufacturing scatterometry data analysis range for optical source intensity for advancement
at reduced pitches in the visible and recipe methods into the IR In-fab X-ray methods
wavelength creation and EUV such as CDSAXS
range and CD-
SEM Robust design of Utilizing AI to identify
test/measurement and design test
structures that closely structures for n+1
represent functional nodes based on yield
structure on the die and reliability of the
current node
Methods capable of IR- CDSAXS Increase in wavelength Increased X-ray Continued
controlling manufacturing scatterometry range for optical source intensity for advancement
with increased aspect methods into the IR in-fab X-ray methods
ratios (3D Devices) and EUV such as CDSAXS
Methods capable of Destructive X-ray methods Invention Widespread use Continued
characterizing and microscopy for epitaxial advancement
controlling buried using cross- film stacks
Interfaces sectional
samples
Electrical test structures Ring oscillators Electron- Test structures for Methods for Continued
and methods for new and high- beam-based difficult-to-detect advanced structures advancement
materials and devices frequency test via testing defects
Structures for
transistors

Interconnect
test structures
Defect detection for 3D Optical and Sensitivity Sensitivity Continued Continued
structures multi-electron to smaller advancement advancement
beam defect particles and
detection defects
FI/FA for advanced devices Electron Advanced E-beam FI, continued X-ray FI, continued Continued
and architectures microscopy FIB sample advancement of FA advancement of FA advancement
preparation

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 186
10.4. Metrology for Packaging and Highly Integrated Systems
Table 10.2: Illustration of the current state of the art and future needs for metrology of packaging and highly integrated systems.

Packaging Current 5 years 10 years 15 years

Non-invasive inspection >1 um <1 um <500nm <250nm
and failure-analysis
imaging capability Acoustic, IR, X-ray Scaling of acoustic, IR, Hybrid approaches, Continued
for defects (voids, methods X-ray methods electrical + physical advancement
delamination, cracks)
Chemical mapping for < 10 um < 5 um < 3 um < 1 um
organic and inorganic
composition/residues at X-ray, mass, and Spatial scaling of existing Improved performance Continued
small dimensions photoelectron-based platforms, X-ray, mass, for metrology, advancement
spectroscopies and photoelectron-based widespread
spectroscopies implementation
Thermal mechanical Early exploratory phase, Enabled design for Widespread Continued
measurements of in-situ limited capabilities metrology, nano-probe implementation advancement
materials/structures development
(i.e., adhesion, fracture
toughness, CTE, etc.)
Improved and more rapid Integrated FI/FA flow Highly integrated FI/FA Improved automation Continued
FI and FA techniques flow and TPT advancement
for debug of 2.5D/3D
structure failure modes

Highly integrated systems Current 5 years 10 years 15 years

Rapid large-scale imaging X-ray and high- Scaling of X-ray and high- Continued advancement Continued
speed scan probes in speed scan probes in advancement
microwave and THz microwave and THz
Chemical mapping for Invention Invention Widespread use Continued
organic and inorganic advancement
composition/residues at
small dimensions

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

Advanced process and integration challenges that are Complexity of the packaging and system process is also
being faced by the advanced manufacturing of transistors introducing critical challenges with the prediction and control
and memory devices has also resulted in many metrology of thermal mechanical risks. Lowering the thermal mechanical
challenges. These same challenges are also seen within risk requires significant innovation, including the ability to
the packaging and highly integrated systems segment, measure those properties in the integrated systems.
particularly with the introduction of advanced packaging
options like wafer-level assembly and other heterogeneous The fault isolation and failure-analysis flows will need to
integration schemes. Increased complexity and reduced introduce more sophisticated test and measurement methods
features sizes are driving the need for innovation to detect to continue successfully isolating failures and determining
and classify deeply buried defects non-destructively with high root causes of those failure modes. KGD becomes an
coverage and velocity. Similarly, new materials are demanding increasingly important requirement to ensure high yield and
more sophisticated and sensitive chemical measurements performance in high-volume manufacturing in packaging. At
for both composition control and residue identification the system level this requires board-level sensing and failure
and mitigation. prediction. AI/ML methods will be critical in all aspects of
these characterization and metrology challenges.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 187
 Figure 10.2: Schematic illustrations of Wafer to Wafer and Die to Wafer process
flows in 3DI with associated metrology. Figure adapted from S. Arkalgud2.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 188
10.5. Acceleration of Metrology through Big Data, Machine
Learning, AI, and Hybrid Metrology
Table 10.3: Comparison of capabilities with different time scales for Big Data, ML, and hybrid metrology

Metrology Technology Current 5 years 10 years 15 years

Big data for fab Fab-wide defect Ru -to-run Fab-wide defect Correlation with TBD
metrology detection equipment level metrology packaging metrology
based on sensor/ correlated with
stand- alone physical and
metrology electrical metrology

ML analysis for fab Data analysis for ML metrology ML-based run-to-run Correlation with TBD
metrology data patterning equipment recipes packaging metrology

ML correlation between Process level IC level Fab-wide defect Correlation with TBD
physical and electrical metrology packaging metrology
correlated with
physical and
electrical metrology

Open software Open-source ML Concept level TBD TBD TBD

platforms for data codes not specific
analysis and ML analysis to semiconductor
of fab data metrology

Open software for Open-source ML Concept level TBD TBD TBD

metrology recipe codes not specific
development to semiconductor
metrology
Training for big data General training Concept level TBD TBD TBD
and ML for ML not specific
to semiconductor
metrology

Process developed and ready for manufacturing. Additional development work needed. Major development effort needed for HVM.

The increased complexity of the research, development, from standalone measurements, sensors, and in-fab electrical
and manufacturing of integrated circuits and packaged testing can be used to provide improved run-to-run control,
systems is driving the necessity of new information systems including feed-forward and feed-backward approaches to
for metrology. As the volume of data increases due to the process control. Measurement recipe development is already
addition of manufacturing steps, Big Data methodology will advancing from routine multi-point measurements at the
require accelerated improvement. Here, the complexity is same location on a wafer to strategically determined locations
greatly increased by the need to analyze measurement data and measurement procedures through ML. This advance
from previous manufacturing cycles and correlate this with is in its early stages, and there is room for considerable
current manufacturing data and failure analysis data from improvement and widespread application. Open-source
previously manufactured ICs. software would aid training.

Predictive analysis of the immense variety of physical The application of ML and AI to physical materials
and electrical measurement methods can be accelerated characterization is an exciting and rapidly advancing area
through ML and AI. ML and AI analysis of the information of research. Open-software platforms for data analysis

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 189
and ML-based interpretation of data from materials
characterization methods are appearing through research
10.6. State of the Art /
at National Laboratories and academia. The open-source Product Examples
platforms that already exist for ML (such as FCU-Net) are
Fab Metrology for Process Development and
being applied to well-known measurement methods such as
Manufacturing
electron microscopy. This is a critical advancement that will
push measurement analysis that could normally take years Metrology capabilities have progressed significantly to
into much shorter times. One example is py4DSTEM from the meet the requirements of advanced node development and
National Center for Electron Microscopy (NCEM), part of the manufacturing. Along with continued improvements in optical,
Molecular Foundry user facility .
8, 9
e-beam, and X-ray-based system resolution and throughput,
materials analysis methods have been developed to meet
As electrical defects become increasingly difficult and newer materials-based manufacturing requirements14. Highly
expensive to diagnose, ML and AI can accelerate improved automated factory systems are beginning to utilize ML/AI
correlation between in-fab physical measurement capabilities to better link process, e-test, and metrology data15.
data, including physical defect detection, and location
with electrical test data. This correlation includes post- EUV patterning has been successfully introduced, including
manufacturing electrical test data and returned product- the corresponding metrologies necessary for implementation
failure analysis. and control16. Defect inspection steps utilize a broader
range of optical phenomena17 and more advanced CDSEM
Hybrid metrology is typically defined as the combination capabilities18. CDSAXS has been introduced into process
of various characterization and metrology techniques to development and manufacturing, particularly for high-aspect-
obtain deeper insights about the functioning of the systems ratio hole/trench memory applications19.
under study, ideally beyond what is obtainable through the
individual techniques. This approach is being developed in Continued Moore’s Law scaling has been realized by continued
both characterization labs and within the fab metrology improvements in patterning and geometric device scaling, as
space. The latter typically couples a high throughput well as the introduction of new materials. These materials can
technique, such as optical critical dimension (OCD) significantly boost performance parameters (e.g., increased
measurements, with slower but more accurate methods, mobility through strain enhancement, higher k capacitors,
such as SEM and TEM10, 11. In the former, more sophisticated lower resistance liners and metals for interconnects, and novel
approaches are being developed, including conductive low k interlayer dielectric systems). These material systems
atomic force microscopy (CAFM) inside a scanning electron require new metrology capabilities during both process
microscopy , as well as STM or APT inside a TEM .
12 13
development and manufacturing. For process development,
this includes the adoption of newer analytical methodologies
Critical to this hybrid approach is the use of ML and AI to like Atom Probe Tomography (APT) and Scanning Probe
enable and improve convergence and to accurately identify Methods (SPM), such as nm-scale IR. Also, in order to support
process/test sensitivities from the Big Data generated by these new materials, several traditionally lab-based
the metrologies. One can also consider the use of ML and methods have been introduced into fab metrology, including
AI to improve the intrinsic hardware performance of these AFM, XPS, Raman, X-ray diffraction, and fluorescence 20.
metrology platforms, reducing the variation and improving Several more are in development by various OEMs.
sensitivity of the hybridized data. Ensuring high precision
and high stability of each metrology technique is a priority, Advanced Packaging (AP) involves TSV formation, wafer or die
as is traceability of the measurements using a chain of tests stacking and thinning, and conventional packaging. Current
or a reference value. Another consideration is the different metrology techniques in use are CSAM for void detection at
quantities delivered by different techniques when measuring a bond interfaces, IR for overlay measurement, and various
similar object, a phenomenon often termed as divergence. This other methods, including crack-length measurement, die shear
is exacerbated by the inherent error sources of each setup, test, and four-point bend for bond energy measurement.
which vary from one machine/sample system to another. Defect monitoring in TSVs involves destructive techniques
like SEM and TEM. Voids are mostly monitored with CSAM,
which requires immersing the bonded wafers or dies in water.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 190
CSAM provides nm scale z-height resolution, but μm scale problems with yield and reliability, and subsequent lab-based
x-y resolution for detecting these voids. It is unable to detect methods further segment the root cause of these parametric
voids between bonded metal structures. IR is typically used for and physical failures. Fault-isolation methods have transitioned
overlay measurements, although continued scaling is pushing from IR-based into the visible to improve resolution with a
the need for resolution improvements and wafer shape subsequent development of novel sample preparation methods
measurements. Bond energy measurements are typically to enable these new methods24. Physical-failure analysis
destructive and are subject to variability induced by operators, employs a fuller range of lab capabilities to isolate and identify
protocols, and resolution. The increased adoption of fusion increasingly smaller and more complex defect modes25.
and hybrid bonding is driving greater AFM usage for critical
surface roughness and bond pad recess measurements.
10.7. Limitations with Current
Lab Characterization in Support of Process
Development and Manufacturing
Technology
Challenges within existing optical and electron beam methods
Lab-based characterization capabilities have significantly
used to measure patterned features at future reduced pitches
improved for supporting early research and process
create serious obstacles to current metrology capabilities. This is
development. Continued improvements in resolution, sensitivity,
further complicated by an increase in aspect ratio, especially for
and the development of novel probes/detection have allowed for
3D memory devices, as well as the complexity of gate-all-around
measurements of material properties in highly complex systems.
devices like nanowire/nanosheet FETs and future devices like
Some examples include 4D scanning transmission electron
forksheet FET stacks and complementary nanowire/nanosheet
microscopy (STEM), atom probe tomography (APT), and
FETs (CFETs). New methods have been introduced that increase
scanning probe microscopy (SPM) methods such as NanoIR
the range of optical scatterometry from the visible wavelength
and Scanning Microwave Impedance Microscopy (sMIM).
range to the IR or to EUV. Wafer-shape measurement to
monitor nm scale distortion is also gaining importance26.
Along with fundamental capability improvements, lab systems
Other CD-methods such as CDSAXS have also been developed.
have also become more automated, with both full wafer
Advances in electron beam methods like CDSEM are expected to
capability and high throughput design. This has introduced
continue, and further improvements will be critical to enabling
capabilities in the “near-fab” space for process debug and
manufacturing of advanced structures.
control, helping bridge the lab-to-fab capability gap. Some
examples include the development of 300mm characterization
Characterization of buried interfacial properties continues to be
platforms like DIB, SIMS, XPS and SPM20.
a difficult challenge. As film thickness decreases, the properties
of film stacks are increasingly dominated by interfacial layers.
In addition to the packaging metrology techniques listed
Microscopy methods such as cross-sectional, high-resolution
above, stress measurement is of immense importance in
STEM/TEM can provide higher spatial resolution, but they
packaging. Moire techniques are used to study package-
are destructive characterization methods. Advances in
level stress behavior21, whereas micro-Raman can be used to
sample preparation, electron beam-based characterization,
monitor TSV-induced stresses in silicon22. Also, most of the
and spatial resolution are expected to continue, as are the
techniques listed above are either destructive (SEM, TEM,
increased implementation of ML and AI data-analysis methods.
bond energy) or slow (CSAM, AFM) and need innovations to
Non-destructive characterization methods also require
move them into HVM.
advancement, including EUV and X-ray-based methods.

Failure Analysis for Wafer-level and Packaging

Measurement of dimensionally dependent materials properties,
A fundamental requirement for success in advanced such as complex refractive index and resistivity, is a key
process development and manufacturing is the capability requirement, but the capabilities to do so are currently limited.
to locate, identify, and root-cause defects throughout the NIST and DOE laboratory competencies can greatly enhance
development and manufacturing flow. For this purpose, these difficult measurements.
there have been significant developments and capabilities
established for electrical test, fault isolation, and failure The potential for ML and AI to enable statistically significant
analysis23. Wafer and package-level e-tests are used to screen measurement of in-die non-repeating structures needs to

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 191
be investigated. Another crucial need is for reduced time-to- Direction and Potential Solutions
measurement for all materials characterization methods.
The trend of lab-based techniques being pursued for inline
process control will continue as the process materials

10.8. Challenges, Future and complexity increase. This can be viewed as a lab-to-
fab transition. Similarly fab metrology attributes, velocity,
Needs, and Possible Solutions coverage, and automation will be increasingly ported onto
lab platforms. This convergence is supported by the concept
Challenges and Future Requirements
of the previously described “hybrid metrology”. This concept
There are significant challenges and gaps in metrology involves using the output of multiple data methods in
and characterization capabilities to meet future process a holistic manner in which the data is hybridized, often
development and manufacturing requirements in both enabled by advanced AI/ML algorithms and data treatment.
fab and packaging areas. These challenges are driven by Using these methods, one can envision more advanced and
increasingly complex stacked and 3D architectures where deeper metrologies, pushing the resolution, sensitivities,
atomic-level process control is required. Systems are also speed, etc. beyond what is capable by a single technique.
becoming highly integrated, providing metrology challenges The techniques and tools do not need to be on the same
throughout the device and packaging manufacturing flow, as platform. In its full implementation, the lab-to-fab separation
well as within defect identification and mitigation. can be overcome, while also providing increased coupling to
process, e-test, and simulation data.
Rapid atomic-scale characterization capability is needed for
both characterization and metrology. Device performance As previously mentioned, a fuller range of the EM spectrum
and integrity are increasingly dictated by single-atomic-layer needs to be exploited, e.g., EUV-based metrologies, mm
interactions, so their measurement and control are crucial. wave radiation, hard X-rays for sub-Angstrom metrology,
This requires improving the productivity of TEM-based etc. Also, beyond photons, alternative probes need further
methods to increase sample coverage and provide more development. This includes utilizing the unique properties
statistically valid results. 3D methods (TEM, APT, X-ray) need of electron beams, ions, and other probes, coupled with
to be further developed and scale to nm and below, ideally advanced detection systems. Many of these activities will
non-invasively to preserve the structures of interest. be driven by the technology systems under investigation,
including magnetic probes, spin-based measurements, etc.
Fab metrology also requires innovations to provide process
control of increasingly complex 3D structures. These are To date, in-situ metrology is a nascent technology, not
challenges that encompass lithography, deposition, and etch readily adopted due to complexity and impact to process tool
processes. Critical defect sizes are becoming smaller, and performance. However, with continued advances in metrology
advanced patterning processes like Directed Self Assembly capabilities, incorporating more of these methods during
(DSA) require spatial and chemical information at the nm- process steps (deposition, etch, etc.) should be considered.
scale. Better coverage and higher throughput demand Dynamic measurement capability can lead to further
improved resolution and sensitivity. improvements in targeting and lowering process variation,
leading to better yields and performance.
The increased cost and complexity of the process pushes the
need for greater in situ electrical characterization to detect Lastly, a major consideration is the potential of utilizing
issues earlier in the process flow. KGD is a critical requirement the full range of available data, design, process, electrical,
in packaging, and innovative probes are needed that relate and metrology, all coupled with simulation. An ideal
electrical and physical properties. Metrology sensitivity must situation is a predictive outcome of the process flow and
be scaled to capture progressively smaller process variations system performance, with feedback loops into design without
which are limiting performance and reliability. From a fab running any actual process. This can dramatically shorten
automation perspective, advanced algorithms and AI/ML development time and allow for innovation. Metrology
methods are required to fully correlate process, metrology, will play a crucial role as part of the simulation ecosystem
and electrical test, coupled with more advanced simulation providing validation of this methodology.
capability. This combination can be viewed as a holistic
approach where design, process, and yield/performance/
reliability are more tightly entwined.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 192
Contributors
Alain Diebold (SUNY Poly) – Chair Kris Bertness (NIST) Thomas LeBrun (NIST)

Markus Kuhn (Rigaku) –Vice Chair Matt Kelly (IPC) Kashyap Yellai (SRC)

Sitaram Arkalgud (TEL) Mario Lanza (KAUST)

References for Chapter 10

1
https://www.nist.gov/news-events/news/2022/09/nist-report-outlines-strategic-opportunities-us-semiconductor-manufacturing
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S. Arkalgud, The Era of Advanced Packaging and Hybrid Bonding, IEDM Tutorial, Dec 2022.
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https://www.nist.gov/laboratories/tools-instruments/synchrotron-ultraviolet-radiation-facility-surf-iii
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https://www.nist.gov/mml/bnl
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https://www.nist.gov/laboratories/tools-instruments/synchrotron-ultraviolet-radiation-facility-surf-iii
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https://www.nist.gov/cnst
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https://www.nist.gov/programs-projects/boulder-microfabrication-facility
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B. Savitzky, et. al., py4DSTEM: A Software Package for Four-Dimensional Scanning Transmission Electron Microscopy Data Analysis, Microscopy
and Microanalysis (2021), 27, 712–743.
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For example: S. Kalinin, et. al., Deep Learning for electron and scanning probe microscopy: From materials design to atomic fabrication, MRS
Bulletin 47, (2022), pp 931-939.
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T. Kagalwala, A. Vaid, S. Mahendrakar, M. Lenahan, F. Fang, P. Isbester, M. Shifrin, Y. Etzioni, A. Cepler, N. Yellai, P. Dasari, C. Bozdog, “Measuring
selfaligned quadruple patterning pitch walking with scatterometry-based metrology utilizing virtual reference,” J. Micro/Nanolith. MEMS
MOEMS 15(4), 044004 (2016).
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D. Dixit, N. Keller, Y. Lifshitz, T. Kagalwala, A. Elia, V. Todi, J. Fronheiser, A. Vaid, “Nonconventional applications of Mueller matrix-based
scatterometry for advanced technology nodes,” J. Micro/Nanolith. MEMS MOEMS 17(3), 034001 (2018).
12
C. Wen, X Jing, F.F. Hitzel, C. Pan, G. Benstetter, M. Lanza, In situ observation of current generation in ZnO nanowire based nanogenerators
using a CAFM integrated into an SEM, ACS Applied Materials & Interfaces, 11 (17), 15183-15188, 2019.
13
Y. Yang, Y. Takahashi, A. Tsurumaki-Fukuchi, M. Arita, M. Moors, M. Buckwell, A. Mehonic, A. J. Kenyon, Probing Electrochemistry at Nanoscale:
In Situ TEM and STM Characterizations of Conducting Filaments in Memristive Devices, J. Electroceram. 2017, 39, 73-93.
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https://www.novami.com/nova-technology/x-ray-photospectroscopy-xps/
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https://www.intel.com/content/dam/www/central-libraries/us/en/documents/increase-product-yield-and-quality-with-machine-learning-paper.pdf
16
Turkot, Britt & Carson, Steven & Lio, Anna & Liang, Ted & Phillips, Mark & McCool, Brian & Stenehjem, Eric & Crimmins, Tim & Zhang, Guojing &
Sivakumar, Sam. (2016). EUV progress toward HVM readiness. 977602. 10.1117/12.2225014.
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Chen, H. & Gao, F. & Huang, K. & Zhang, Z. & Shi, Y. & Xu, Y. (2015). OCD measurement of defocus and dose in EUV lithography. 10.1109/
CSTIC.2015.7153452.
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Zhigang Wang, Yoshinori Momonoi, Katsumi Setoguchi, Makoto Suzuki, Satoru Yamaguchi, “What is prevalent CD-SEM’s role in EUV era?,” Proc.
SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 1095914 (29 March 2019).
19
Fan, M., Ranjit, R., Thurber, A., and Engelhard, D., “High resolution profiles of 3D NAND pillars using x-ray scattering metrology”, in Metrology,
Inspection, and Process Control for Semiconductor Manufacturing XXXV, 2021, vol. 11611. doi:10.1117/12.2585217.
20
https://semiengineering.com/speeding-up-the-rd-metrology-process/
21
H. Ding et al., IEEE Transactions on Components and Packaging Technologies, Vol. 25 (4) December 2002
22
I. DeWolf, Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits, Semiconductor Science and Technology, Vol
11 (2), 1996].
23
T. Rodgers, A. Gu, G. Johnson, M. Terada, N. Cohan, V. Viswanathan, M.W. Phaneuf, J. de Fourestier, E. Ruttan, S. McCracken, S. Costello,
A.M Robinson, A. Gibson, A. Balfour; “A Correlative Microscopic Workflow For Nanoscale Failure Analysis and Characterization of Advanced
Electronics Packages.” Proceedings of the ISTFA 2022. ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing
and Failure Analysis. Pasadena, California, USA. (pp. pp. 319-323). ASM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 193
24
https://patents.google.com/patent/US20150002182A1/en

Tong, Xianghong & Chuang, Wen-hsien & Ryu, Hyuk & Joshi, Prasoon & Xu, Di & Cook, Steven & Huening, Jennifer & Wang, Yunfei & Zhao, Shuai
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& Deshpande, Piyush & Ma, Zhiyong. (2019). Silicon Device Backside De-Processing and Fault Isolation Techniques. 10.31399/asm.tb.mfadr7.
t91110323.

Nathan Ip, Multi-physics Simulation of Wafer-to-Wafer Bonding Dynamics at the 72nd Electronics Components and Technology Conference
26

(ECTC 2022).

(Return to TOC)

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 194
Chapter 11

Workforce Development
11.1. Introduction the American Semiconductor Academy (ASA). All studies
have converged on the same essential components: pipeline
The current talent pool and the pathways for creating and development; inclusion; curriculum development; knowledge,
supporting a U.S. domestic workforce for microelectronics skills, and abilities (KSA) aligned with critical job functions;
and advanced packaging technologies (MAPT) fall far short of access to state-of-the-art education and training facilities; and
projected needs for the nation. While this is part of the pervasive tools for authentic KSA development, experiential learning,
STEM workforce gap in the U.S., it has reached a critical point and hiring. Recently created industry-university teams pursuing
with respect to U.S. leadership in MAPT R&D, IC design, and CHIPS Act funds are reviewing needs and best practices toward
manufacturing, resulting in considerable national security risks. developing strategies for implementing them at scale, from
With the CHIPS and Science Act making $50B investments in national to local and with different target groups, jobs, and
the U.S., the current pipeline for workers across the spectrum of education requirements. All agree that effective WFD will
education levels is insufficient by at least an order of magnitude require combining forces as a national community, leveraging
for the next decade across all educational levels. Estimates for funding to support what has been shown to be effective and
the size of the workforce gap for MAPT vary. As an example, the testing what can possibly be effective at the necessary scale.
Semiconductor Industry Association (SIA) with Oxford Economics
estimated in their 2021 Report1 that, to support the incentive What differentiates the SRC MAPT WFD Roadmap from other
fund investments, the CHIPS and Science Act will create an roadmaps is the focus on addressing three specific, critical areas
additional 89,250 direct jobs and 176,000 supply chain (indirect) rather than general needs and approaches for MAPT WFD.
jobs in fab operation plus 20,000 direct jobs and 18,000 indirect
jobs in R&D. These positions do not reflect the additional 1. Supply/demand modeling of the needs across all MAPT
associated impacts of the CHIPS R&D programs. areas, from research and development to manufacturing,
including a timeline for when and where employees
In spite of differences between estimates, all agree that the will be needed and specific KSA for specific industry
gap is substantial and the pipeline insufficient, and it will jobs. Aggregate national numbers and generic KSAs
require focus and time to fill at all levels across the U.S. Several are insufficient input for creating models for effective
organizations have been studying and mapping workforce education and training programs and implementing them to
development (WFD) needs, including the President’s Council of meet local WFD needs. Having jobs available is the first part
Advisors on Science and Technology (PCAST), the Department of the implied social contract among students, educators,
of Defense (DoD), the National Institute of Standards and and employers: students commit to learning, educators
Technology (NIST), the National Science Board, SEMI, and commit to teaching, and employers ask for specific KSA to

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 195
 be taught for specific jobs. The Supply/Demand Modeling whether they’re enrolled in technical and career education
sections recommends efforts to capture the quantitative (vocational programs), community colleges, or four-year
detail necessary to fulfill this social contract. and graduate programs; and engaging with veterans and
displaced workers to make them aware of how their current
2. Models for effective engagement to give students career
skills can be repositioned or augmented for jobs in the
pathways in MAPT, not simply the list of ingredients
microelectronics industry. This not only requires awareness
for good programs (e.g., curricular content, mentoring,
programs, but also intentional deployment of the most
research projects, hands-on, internships, scholarships, and
effective models of engagement for guiding them from
teacher training). Effective models and programs combine
awareness to commitment to MAPT careers.
to create optimal ROI for students, companies, educational
institutions, and other ecosystem stakeholders. This will
There are recommendations throughout the three sections
constitute a “whole-of-nation” and “all-hands-on-deck”
and in the conclusions of this chapter to address the MAPT
approach that can be implemented locally. Note that the
WFD requirements and needs for a robust U.S. semiconductor/
term “student” applies to any individual at any stage in
microelectronics industry at scale. Note that the MAPT WFD
their career, including current and recent members of the
roadmap cuts across all the areas and sectors represented in
MAPT workforce and those changing careers. This section
the MAPT Roadmap as individual chapters.
describes how to develop plans for leveraging existing
successful programs that address regional and local needs,
Meeting the Microelectronics and Advanced Packaging WFD
evaluating new programs that are needed, and identifying
challenge will require well-developed, effective pathways for
which programs can and cannot effectively be scaled for a
students to obtain MAPT jobs. The figure below illustrates
national impact.
possible career paths that lead to the creation of a well-
3. Winning hearts and minds of individuals across the U.S. functioning pipeline for MAPT WFD. (Note that SEMI has set
for the necessary pursuit of educational opportunities quantitative goals for each of these pathways for SEMI-led
that lead to MAPT industry jobs. This includes working programs as shown in the left column.) For each of these
with K-12 students and teachers to spark an interest in pathways, sustained outreach and student support are going
microelectronics and STEM; incentivizing students across to be necessary to fill the student pipeline, including, but not
educational levels to pursue microelectronic careers, limited to, mentoring, research experiences, and internships.

Figure 11.1: SEMI Foundation’s Workforce Development Path, from excitement to engagement

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 196
11.2. Supply/Demand Modeling MAPT workforce talent pool and the requisite KSA based on
company, regional, and national needs must be developed at
It is difficult to develop WFD action plans and programs given a granular level. This will serve as a tool to facilitate objective
the uncertainty and aggregate nature of the assessments of decision-making by policymakers, academic institutions, and
MAPT WFD needs that currently exist. This is especially true industry partners on where to invest to meet specific MAPT
right now, with recent layoffs by prominent companies in the WFD needs, as well as by students on where to direct their
MAPT ecosystem. Detailed models and data of the potential futures. The specificity of the career paths and granularity

Figure 11.2: Different university majors are required for high-volume semiconductor manufacturing, design engineering, and R&D constructed
using data from Roadmap partners. This is a Sankey diagram in which the heights of the left-hand colored boxes for each major are
quantitative, with the total height for all majors equaling 100% of the jobs. On the right, the fraction of jobs in each of the three categories
are represented by the heights of the three boxes, with students from different majors represented in each as required by the jobs.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 197
of the data required are illustrated in Figure 11.3: Workforce Talent Flow Pipeline, with numbers specifically for EE/ECE graduates.
Figure 11.2 in which the many different
academic majors needed for jobs in high-
volume semiconductor manufacturing,
design engineering, and R&D are shown
for BS, MS, and PhD degrees. Community
college training and career and technical
education (CTE) have similar mappings
into technician and operator jobs. Though
similar quantification for technicians and
operators were not available at this time,
they account for an estimated 70% of
the jobs in high-volume manufacturing.
Detailed supply/demand models must
be supported by quantitative data and
analysis obtained through public/private
collaboration, including capturing the
mapping that is being done within
individual companies, across the
industry, and by educational institutions
and groups. The two important tools
proposed for development include a
Workforce Development Pipeline Model
and a KSA Matrix.

Workforce development
pipeline (WFD) model
The pipeline model is represented by
a diagram (Figure 11.3) with nodes
denoting the present population at
each stage of education, including high
school, university, postgraduate study,
and employment, with transition points
illustrating where the MAPT pipeline
shrinks and where additional candidates To ensure a steady supply of skilled workers, the semiconductor industry must reinforce
enter the pipeline. The model includes the workforce ecosystem through various talent pathways, strengthening talent
transitions from each stage to the next pipelines and pools, as well as crossing disciplines as the needed KSA changes over time.
(e.g., annual college graduates going to
industry or postgraduate study). Figure 11.3 illustrates the “leaky” pipeline, i.e., that decreasing number of U.S.
university undergraduate and graduate students stay in the Semiconductor
Further, this model provides detail to Workforce Development Pipeline in the disciplines of electrical engineering
allow analysis of the demographics and (EE) and electrical and computer engineering (ECE). This was chosen as an iconic
geographic location at each stage in the example of a leaky MAPT WFD pipeline, given the well-established decrease in
pipeline, as this information will be critical students choosing EE and ECE for university degrees. From top to bottom, more
in understanding the most impactful than 4.6M U.S. students enter high school. Upon graduation, approximately 8,000
ways to stimulate the development of the go directly into the MAPT workforce, while an overwhelming number choose other
future semiconductor industry workforce. workforce areas. Of the remaining 2M+ high school graduates, 577,000 enter four-
The model requires continuing validation year colleges and universities as STEM majors. Additionally, students enter college
and updating to align with the dynamics from other sources each year, including 2,000 veterans, 515,000 transfers from
of the industry. two-year community colleges and 59,000 international students. Upon graduation

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 198
with an undergraduate degree, about 6,000 enter the MAPT it’s to make sure that their curricula, training, experiential
workforce. Approximately 222,000 U.S. college and university learning, and internship programs prepare students well for
graduates in STEM continue to graduate school, joined by MAPT careers. For employers, it’s to inform educators and
130,000 international students and another 2,000 veterans. It students of the KSA needed for the jobs they will offer (now
is critical to note the importance of international students in and in the future) and to provide opportunities for students
the graduate-level STEM workforce—of the 5,000 graduate- to acquire these KSA through internships, apprenticeships,
level students entering the semiconductor workforce, 65% and mentoring. It is only possible to develop broader and
of them are international students. In total, from high school deeper MAPT talent pools aligned to job opportunities if
through graduate school, approximately 19,000 students students, educators, and employers together apply the KSA
pursue careers in the semiconductor workforce out of more matrix as guidance. Building students’ technical KSA can come
than a total 5 million students in the pipeline. from a wide range of sources, but this is often not enough. The
Roadmap team reported that in their companies students are
KSA matrix frequently hired according to their potential contribution
based on their ability to think critically, analyze and solve
The term Knowledge, Skills, and Abilities (KSA) refers to a
problems, and learn new subjects as problem complexity
combination of qualifications required for a person to perform
increases. Meaningful industrial internships in manufacturing
a specific role with specific tasks. Organizations require
and R&D can help develop these skills and create strong ties
several technical and non-technical core competencies to
between students and MAPT companies, leading directly to
fulfill the roles associated with the semiconductor value
career pathways.
chain. These can be classified broadly into R&D, Design, and
Manufacturing. Personnel with the required KSA are integral to
Figure 11.4 is a conceptual KSA matrix, constructed by mapping
key departments such as Engineering, Information Technology,
respective KSA to the roles performed in specific jobs requiring
Human Resources, Finance, Legal, Sales and Marketing, Safety
EE and ECE backgrounds. (Similar KSA matrices will be needed
and Compliance, and Industrial and Public Relations.
for all the roles needed for high-volume manufacturing,
design engineering, and R&D, as shown in Figure 11.2.)
A KSA matrix maps broad job functions to the KSA required
Semiconductor roles (jobs) are indicated vertically with skills
to perform specific job functions along with the relative
horizontally and color-coded as to level of need, with white
importance of each skill to each job function. There are
indicating not needed. Additionally, arrows highlight those
multiple purposes in defining MAPT KSA, all are linked to
skills with expected increasing importance and need for the
the aforementioned “social contract” between students,
semiconductor industry over the next five to 10 years. A more
educators, and employers. For students, it is to intentionally
detailed list of roles and skills is in the appendix of this chapter.
acquire the skills they need to be successful in a MAPT career.
For educators, from high school through graduate school,

Figure 11.4: Semiconductor KSA Matrix Concept

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 199
Scoring is based on the importance and frequency of the KSA training, and workforce development”, including developing
used at different levels of expertise. Preliminary clustering tools to standardized KSA for cybersecurity jobs, a supply/
analysis on the KSA x role matrix can be used to identify demand model for jobs, and a mapping of education and training
groups of job functions, which in turn can be used to identify providers. (https://www.nist.gov/itl/applied-cybersecurity/nice/
pathways to obtain associated KSA and the corresponding resources). Given the magnitude of the MAPT WFD needs in the
jobs. Across the MAPT workforce, some roles may be based on next one to five years, the MAPT community should learn from
KSA learned predominantly in traditional academic disciplines, NICE about what has and has not worked in its partnerships
such as EE/ECE, materials science and engineering, chemical across government, academia, and the private sector, and then
engineering, civil engineering, and environmental engineering, focus on using the Supply/Demand modeling and the KSA
while others will be based on interdisciplinary or cross- matrices to accelerate the pace of MAPT WFD.
disciplinary KSA, such as data science, artificial intelligence,
machine learning, sustainability, and automation. Recommendations

• Develop quantitative supply/demand modeling for MAPT

Example of cross-discipline KSA: Sustainability
WFD from development to manufacturing, including a
A resilient workforce with the right knowledge, skills, timeline for when and where employees are needed. This
and abilities (KSA) will be needed to create a future of should include models integrated with specific KSA for
energy-efficient computing and sustainable technologies, specific jobs within the industry and be linked to education
materials, and manufacturing. For all the energy efficiency and training program outcomes.
and sustainability challenges described in Chapter 2,
• Validate the model against new data periodically to
teams of people with combinations of KSA are needed to
update/correct.
solve them. Depending on the specific problem and scope
identified , the disciplines needed will include engineers of all • Validate the model with industry needs and gaps.
types (automation, chemical, civil, electrical, environmental,
• Develop community-driven (government, industry,
industrial, maintenance, manufacturing, materials,
academia) model use and impact.
mechanical), toxicologists, ecologists, chemists, physicists,
mathematicians, statisticians, data scientists, economists, • Update the KSA for the evolution of job requirements,
climate scientists—the list goes on. A key result of the including but not limited to AI, machine learning,
roadmap is the recognition that, for all of these disciplines, sustainability, and automation.
sharing a baseline of sustainability knowledge and practice will
• Analyze the matrix for gaps and common trends to
be critical to solving these problems, including discovering and
leverage for engagement models.
creating sustainable materials, processes, technologies, and
systems. This knowledge must be integrated into disciplinary • Prioritize areas of need.
coursework while students are first becoming subject matter
• Update/maintain the matrix based on changing needs
experts as undergraduates, or else it will never become part of
and roles over time.
the working-level KSA of the MAPT workforce. The KSA must
then be deepened and put into practice in more advanced • Identify and engage an owner to drive model development,
courses, MS degrees, research, on-the-job training, and dissemination, and maintenance to keep up with the
industrial practice. Within multidisciplinary teams, the gaps, dynamics of the semiconductor industry.
sustainability and otherwise, must be identified and filled to
create optimal solutions. At the moment, environmental and Assuming that high fidelity supply/demand models and KSA
EHS impacts are generally an afterthought, considered once are developed to identify MAPT jobs now and in the future,
the design is set, materials and processes are selected, and how are these to be used? The next two sections of the
end-of-life fate is already engineered. roadmap address these specific questions:

• How can the KSA gap be filled for existing (and future)
Other frameworks exist for which linkages have been forged
students in a way that produces motivated, industry-
between the KSA and career opportunities in STEM. For
ready students?
example, for more than 10 years, the NIST National Institute for
Cybersecurity Education (NICE) has been working “to energize, • How can the number of students in the MAPT pipeline be
promote, and coordinate a robust community working together increased by winning the hearts and minds of students?
to advance an integrated ecosystem of cybersecurity education,

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 200
11.3. Models for Effective Building Communities and Pipelines: Develop sustainable,
effective engagement opportunities to connect industry
Engagement employees with instructors and students in K-12 environments,
community colleges, and universities.
Identifying needs and gaps through effective modeling
provides guidance toward areas of focus to engage students
Community engagement between industry, schools, and
with effective programs. There is a need to engage students
communities is a powerful way to interest students and adults
and the transitioning workforce to consider careers in
in MAPT careers, particularly by introducing them to working
STEM fields, particularly the MAPT industry, and to do so
professionals who can share stories about their personal
in a way that builds and sustains a broad and diverse talent
careers and education pathways. These professionals can bring
pipeline to meet the workforce needs. There are many
practical real-world applications, challenges, experiments,
existing engagement models and programs across the country
and activities into classrooms, and can lead internship,
to leverage talent, but even more successful methods need
apprenticeship, coaching and mentoring programs in the
to be identified. The engagement models should focus on the
communities. One of the priorities should be to develop a series
following five areas:
of ongoing engagement opportunities for industry employees,
1. Driving awareness, understanding, and relevance teachers, counselors, and students. Examples include:

2. Building communities and pipelines • A career ambassador program that companies can participate
in which provides training, tools, and interaction opportunities
3. Creating diverse talent pipelines
for industry employees to lead classroom discussions.
4. Strengthening industry diversity practice
• Leverage existing work-based learning experiences that
5. Scaling effective engagement initiatives for impact can be replicated across other companies nationwide, for
example Micron Foundation’s Job Shadow and Chip Camp
Driving awareness, understanding, and relevance: Widen programs for high school students that provide virtual and
the pipeline by increasing overall industry, career, and in-person immersions.
employer awareness for U.S. students, teachers, professors,
• Support of Heroes Connect webinars organized by Heroes
counselors, and parents, as well as helping veterans, women,
MAKE America, highlighting semiconductor companies
underrepresented people of color, and rural residents see the
and career opportunities to transitioning service members
relevance of MAPT careers to themselves, their families, and
and veterans.
their communities.
• Industry-led awareness programs, such as Semiconductor
Building industry, career, and employer awareness with a more Day at Ohio State and a women-focused event at University
diverse range of students and adults is a key workforce priority of Cincinnati, that inform communities where semiconductor
for the industry. It is imperative to address both awareness of industry has not had a large footprint.
the industry and its image to compete with adjacent industries
that are vying for the same talent. Multiple programs, activities, Creating diverse talent pipelines: Reach diverse talent
and channels are needed to reach K-12 and university/college pipelines by linking programs from high schools, vocational
students, older adults needing to reskill or upskill, veterans, schools, and community colleges with underserved, tribal, and
women returning to work, and more. Examples of some rural student populations, as well as those transitioning from
potential programs which can be scaled include: other industries.

• Industry image and awareness campaign—A series of

A focus on underserved, tribal, and rural student populations
national and regional media activities that highlight
will grow the overall size of the semiconductor talent pool.
the industry.
In addition to prioritizing these programs, talent diversity
• SEMI High-tech U and related initiatives—Programs that programs should also be combined with longer-term
encourage industry employee engagement in classrooms investments and commitments in these communities to fully
and teacher training, as well as tools to help families support students’ needs in other areas that contribute to
understand the industry, its companies, and its wide overall success.
range of career opportunities.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 201
To ensure the widest possible pool of talent is captured, these Industry and education need multiple strategies to address
stronger linkages will be forged between high schools, career these systemic problems including: addressing bias in company
and technical education schools, military training programs, cultures; framing job opportunities to be more welcoming to a
community colleges, and four-year universities, relying on solid diverse array of candidates; representing women and people
industry engagement and support. of color in marketing and communications; and developing
leadership and promotion practices to ensure that women and
Examples of required efforts include: people of color have clear pathways to advancement. Tools and
support available to companies include:
• Gathering data to identify these schools across the nation,
examining existing programs, adopting best practices, and • SEMI organization’s Roadmap to Diversity, Equity, and
finding key local contacts to start the collaboration process Inclusion, and DEI Toolkit, which supports industry to
state by state. improve diversity.

• Aligning high-school courses and content with community • Webinars, training, and research on DEI.
college certificates and programs.
• Mentoring programs for industry women and people of
• Expanding dual-credit programs, investigating course color to create one-on-one bonds with women and people
credits for conducting research with university faculty, and of color in Grades 7-12, illustrating, “I can do it too!”
identifying more transferable credit courses.
• An expansion of programs like the Annual SEMI “Women in
• Expanding traditional community-college programs into Semiconductors” program led by industry professionals to
more semiconductor-aligned areas. focus on strategies for women to succeed in semiconductor
manufacturing, including leadership strategies.
• Partnering with professional teacher associations
(e.g., NSTA, CSTA) to advocate for more STEM teacher
Scaling effective engagement initiatives for impact:
investments and incentives to recruit more diverse groups
into the profession. Understand and quantify the ROI for different effective
models, including mentorship, apprenticeship, internships,
• Incentivizing access through industry-sponsored university
and curriculum alignment, so that investment choices and
scholarships.
commitments can be made by different stakeholders.

Strengthening industry diversity practices: Change industry

There are many existing initiatives focused on increasing
practices to help recruit, hire, retain, and promote a more
engagement of students and older adults to pursue careers
diverse workforce.
in the semiconductor industry, but many of the programs
lack the reach required to make an impact on the workforce
In the last 12 months, there were more than 84,000 job
demand.What is needed is a way to broaden the impact of
openings reported by SEMI member companies, with an
those programs by more seamlessly connecting the demand
estimated additional 70,000 to 90,000 MAPT jobs expected
(the semiconductor companies) with the supply (the talent pool
in the coming three years, particularly with new fabs coming
and educational institutions). A global, online, open-source
online. The industry cannot afford to exclude any potential
platform must be established that can serve as an aggregated
talent. Women hold only 25% of computing-related jobs (with
resource bringing together students, employers (the MAPT
just 3% of those jobs held by Black women). Women are only
industry), professional societies, industry groups, educators
14% of our engineering workforce and only 22% of C-Suite
(K-12, community colleges, and four-year colleges/universities)
leaders. Black people comprise less than 5% of the tech
and workforce training providers (see Figure 11.5).
workforce. Latino people make up 7%. Furthermore, there
are zero Black CEOs among Fortune 500 tech companies, and
Through early and large-scale adoption of the MAPT industry
83% of tech executives are white.
and industry groups (e.g., SEMI, SRC, SIA), this platform would
be well-positioned to attract existing large-scale repositories
These inequities result in decreased innovation, productivity,
of career guidance resources, MAPT curriculum content,
competitiveness, and profitability. With the U.S. shifting
internship, co-op, and apprenticeship opportunities, virtual
toward a more ethnically and culturally diverse population,
and online training resources, and relevant certificate-based
the semiconductor industry must attract more diverse talent
programs. For key MAPT workforce development resources
to address current and future workforce shortages and reach
where existing repositories are lacking, it is recommended
its full potential.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 202
that such repositories be established and incorporated within institutions, and government. This cannot be a passive site but
this portal. With sufficient participation by the MAPT industry, rather an active and engaging platform.
industry organizations, and key national/regional MAPT
WFD organizations (e.g., NSF, US Deparment of Labor, NIIT, Recommendations
Department of Defense), such a portal could serve as a primary
• Establish and curate a global, online, open-source platform
entryway to pursue semiconductor careers for students
where semiconductor companies, professional societies
and the transitioning workforce. This would allow these
and industry groups, universities and community colleges,
talent pools to learn about the industry and would provide
and K-12 educators can develop and post career guidance
resources—either directly or through partner organizations—
resources, curriculum content, internship, co-op, and
for training and development. It will also reduce barriers to
apprenticeship opportunities, virtual and online training,
engagement, support sharing of best practices, empower
and certificate programs.
teachers and parents, and facilitate crucial connections to build
the workforce of the future. • Create incentives for collaboration and require clear metrics
to show and improve effectiveness.
Portal data analytics will provide valuable information on
• Add new program content or updates to existing content as
the effectiveness of specific programs to reach the target
needed so the site remains current.
audiences and drive the development of new initiatives and
content. Government support to fund the development • Use web analytics to measure the effectiveness of portal
of open-source content will be critically important, as well content to support the workforce objectives.
as ongoing support to build, expand, maintain, and curate
• Provide sustained government funding for the development
the site. For this platform to be effective, it will require
of open-source content, as well as ongoing support to build,
resources beyond CHIPS Act funding and active engagement
expand, maintain, and curate the site.
with industry, research institutions, academia/education

Figure 11.5: Semiconductor KSA Matrix Concept

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 203
11.4 Winning Hearts and Minds Some middle schools and high schools augment academic
instruction with Career and Technical Education (CTE), but the
Meeting the workforce needs of the U.S. MAPT industry extent to which this occurs varies from state to state and even
requires developing a system that will attract and support school to school in the same region. Advance CTE, a nonprofit
enough students who are interested in pursuing the organization that represents state directors and leaders of
education and training necessary to qualify for jobs in the CTE, provides access to a plethora of online resources for
industry. Even as early as elementary school, students make designing, assessing, and marketing CTE programs to students
a series of decisions about career path decisions, whether and their families (www.careertech.org). Industry engagement
they recognize the significance of those decisions at the time is critical to developing meaningful CTE experiences and
or not. For example, the level of middle-school mathematics helping students understand how their studies can lead to job
to which a student is assigned can determine whether the opportunities at all levels.
student can pursue a four-year undergraduate STEM degree.
Many factors can influence these transition points and Regardless of access to CTE, students should be given
decisions, and there are significant factors and combinations opportunities to begin exploring career options as early as
of factors that lead students to leave the STEM and MAPT possible, not just immediately prior to graduation. Decisions
pipelines. Creating workforce development programs for will be influenced by teachers, school counselors, family,
STEM and MAPT is predicated on the belief that effective and friends, which speaks to the need for STEM ecosystems
strategies can be identified to change student decisions, that highlight microelectronics and engage individuals both
recognizing that what has worked in the past is not working within and outside the formal education system. Afterschool
now at the scale necessary and will likely not work any programs, community groups, museums, and libraries can play
better in the future. important roles in sparking interest in STEM and MAPT and
forming opinions about STEM and MAPT career paths. Social
MAPT WFD: A special subset of issues within media, internet resources, and other virtual environments can
STEM education also provide opportunities to reach students who may not have
access to quality in-person experiences.
The development of core skills needed to participate in the
semiconductor workforce and other STEM careers begins
Currently missing from the understanding of how students
in middle school and continues throughout high school.
make choices away or toward MAPT careers is hearing the
The Nation’s Strategic Plan for STEM Education, Charting a
voices of today’s students. Past surveys of college graduates
Course for Success: America’s Strategy for STEM Education,
have garnered a deep understanding of the factors that affect
published in December 2018, urges the formation of a STEM
students’ college experiences and what action can be taken
Education Ecosystem that consists of multi-sector partners
to improve them. For example, the 2015 Gallup-USA Funds
united by a collective vision of supporting participation in
Minority College Graduates Report, based on the Gallup-Purdue
STEM through the creation of accessible, inclusive STEM
Index studies, showed that black graduates from a HBCU were
learning opportunities spanning all education stages and
more likely to strongly agree than black graduates of other
career pathways. THE MAPT industry needs a MAPT Education
institutions that (1) their colleges prepared them for life after
Ecosystem if it is going to meet the long-term WFD needs.
graduation, (2) they had a professor who cared about them
as a person, (3) they had a professor who made them excited
Building a successful MAPT Educational Ecosystem
about learning, and (4) they had a mentor who encouraged
requires engagement with and understanding of the
them to pursue their goals and dreams, with the largest gap
K-12 education systems. Currently, students gain little
being for having a professor who cared about them as people
exposure to microelectronics and semiconductors in their
(58% vs. 25%). In a more recent Gallup Alumni survey, “college
K-12 experiences. Fortunately, there is an ongoing evolution
graduates are almost twice as likely to be engaged at work if
of K-12 STEM education, from siloed discipline-specific
they had a mentor who encouraged them to pursue their goals
activities to a more integrated approach that offers excellent
and dreams,” and “graduates are 1.4 times more likely to be
opportunities for introducing K-12 students to semiconductors
thriving in five key elements of wellbeing if a professor cared
and microelectronics. Activities that highlight the connection
about them as a person.” Having current, in-depth results in
of technology to solving complex real-world problems with
the context of STEM and MAPT education, training, and careers
social or personal implications for students are thought to be
for different universities and colleges, as well as from students
particularly effective in broadening participation in STEM.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 204
with different backgrounds, could be invaluable in making the Area of immediate need: Post-secondary, career,
right choices and investments for increasing the effectiveness and technical education
of MAPT WFD programs.
Post-secondary career and technical education (CTE) is
important for training technicians and operators for the
Recommendations
MAPT industry. However, the pipeline is insufficient to
• Support the Nation’s Strategic Plan for STEM Education meet current needs, and the gap between the needed
by building and supporting regional MAPT education workforce and the pipeline continues to grow. New
ecosystems which include microelectronics awareness strategies are needed to close the gap. The CTE programs
and that bring together learners, families, educators, offered in a given region often depend on local workforce
communities, and employers. Ensure microelectronic/ needs, but they are typically limited by the size of the local
semiconductor awareness and impact are addressed in population interested in such jobs and resources available to
this program. close the KSA gaps. The content of CTE programs is frequently
informed by the CTE National Career Clusters Framework.
• Engage individuals who are knowledgeable about age-
Developed to guide curriculum design and instruction, the
appropriate and culturally sensitive pedagogy with
framework maps 79 career paths within 16 career clusters,
practitioners in the semiconductor field to develop learning
including STEM, Manufacturing, and Information Technology,
experiences that can be delivered in both formal and
which are particularly relevant to the MAPT industry. Efforts
informal settings.
are underway to modernize the framework with input from
• Ensure that the global, online, open-source platform a variety of stakeholders, and this may provide the industry
recommended above is effective at “winning students’ with an opportunity to ensure that future CTE offerings are
hearts and minds” for a wide range of education well-aligned with industry KSA. Effective campaigns to recruit
levels, geographical locations, and demographics; have students through awareness, understanding, and relevance
mechanisms and incentives for students, teachers, industry, will be critical to success of CTE programs.
and others to use and share materials on the platform to
attract and retain student interest. Recommendations

• Develop and provide training programs for middle and • Work with local and regional CTE providers to shape the
high school teachers that show how examples and activities post-secondary programs available to students.
featuring semiconductors can be incorporated into the
• Map current CTE competencies to desired MAPT KSA.
curriculum.
• Engage with local and regional CTE providers to support
• Develop and deliver authentic career exploration programs
their recruiting efforts through awareness, understanding,
(summer camps, shadowing experiences, career and
and relevance campaigns; develop industry-specific and
technical training programs, and summer employment).
even company-specific content that complements existing
• Provide students with opportunities to earn high school and programs and strengthens ties between students and
college credit while learning about the semiconductor and prospective employers.
advanced packaging industry.
• Provide scholarships and internships to incentivize students
• Develop and deliver national image and awareness to complete industry-specific training.
campaigns to introduce high school students and
influencers (teachers, school counselors, and family College Pipeline
members) to opportunities in the semiconductor industry.
A student who chooses to enroll in a STEM discipline in a
• Create a marketing and branding toolkit that can be readily community college or university is well on their way along
adapted by different members of the ecosystem for a career path that could lead to employment in the MAPT
different audiences and programs. industries. However, as highlighted earlier, a significant
percentage of students entering STEM disciplines drop
• Conduct a new ”Gallup like”survey to identify the most
out in the first few years. Thus, we cannot assume those
important factors in student success and why students choose
entering will make it through to industry hires. There is a
or do not choose STEM and MAPT as career paths, with the
plethora of factors that contribute to students switching out
goal of identifying where action can make the most difference.
of STEM majors or even leaving higher education altogether2.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 205
For some students, it is simply a matter of economics and effective, raising awareness, understanding, and relevance of
family commitments—they simply cannot afford to continue MAPT career paths before enlistment and during deployment
their studies. Studies have shown that approximately 70% can potentially have a significant effect on recruiting veterans
of the college students leaving STEM disciplines report as they leave the military.
financial concerns as a contributing factor in their decision to
Recommendations
switch majors, and 10% report it as a primary factor2. Others
conclude that a STEM career is not for them, often based • Develop an awareness program for members of the military
on misconceptions about future careers and on the lack of and soon-to-be veterans that highlights microelectronics job
a supportive community. Financial incentives and exposure opportunities and training resources.
to experiences that reinforce that STEM careers can make a
• Develop a “map” of military experience, expertise, and KSA
difference in the world, foster a sense of belonging, and lead
that are applicable to the semiconductor industry roles and
to rewarding careers are all effective ways to reduce leaks in
jobs at all educational levels.
the MAPT pipeline.
• Ensure there are effective training programs and placement
Only a few academic programs in the U.S. focus specifically on services to transition from military to semiconductor jobs.
semiconductor science and microelectronic engineering, and
• Understand the constraints and barriers to military veterans
most of these are graduate programs for master’s and doctoral
pursuing these job opportunities and training programs and
students. As previously noted, enrollment in EE/ECE, which is
find ways to eliminate them.
especially important to the MAPT industry, has been declining
over the past decade. Meeting the workforce demands of
Diversity, Equity, and Inclusion
the MAPT industry requires expertise from many disciplines,
yet few students enrolled in these majors will get significant Key to any successful enterprise is diversity of thought,
exposure to their field during their studies. perspective, and ideas, all of which require a diverse employee
population. Despite gains in academic attainment over the
Recommendations past decade, Black, Hispanic and women workers continue
to be underrepresented in the STEM workforce excluding
• Conduct survey and focus group studies of current college
health-related and social/behavioral science occupations3
students to understand industry awareness, barriers to
Understanding the institutional, social, economic and
entry, and the types of incentives that will attract students
academic barriers that underrepresented groups experience
to the careers in the industry.
in STEM education and the workplace is critical to promoting
• Incentivize interest in the semiconductor industry by DEI in the MAPT workforce. In 2021, the National Science
providing work-based learning (WBL) opportunities, such as and Technology Council’s Committee on STEM Education
scholarships, internships/coop, apprenticeships, fellowships, Committee examined these barriers and compiled evidence-
and other forms of experiential learning. based best practices that promote diversity and inclusion in
STEM. Many of the report’s examples, categorized broadly in
• Support professional student clubs and sponsor
terms of STEM Pathways, Access and Recruiting, Achievement
competitions to encourage extracurricular interests aligned
and Advancement, and Retention, can be adapted to address
with the industry needs.
the specific needs of the MAPT industry4.
• Build “Change the World” awareness and motivation by
implementing programs with examples of microelectronics Recommendations
impact to the environment and society—now and in the future.
• Develop a national awareness and information program to
reach diverse populations, many of whom may not be aware
Military Service Pipeline
of the MAPT opportunities available to them.
Military veterans are an additional source of potential talent
• Support for evidence-based practices that promote
to feed into the semiconductor industry. Many veterans are
diversity, equity and inclusion in STEM education leading
not aware of how their military experience can be applied
to MAPT careers.
toward employment in microelectronics. Providing detailed
information and job opportunities to those leaving the military, • Support evidence-based practices that promote diversity,
as well as providing the training to build the necessary KSA, equity and inclusion with the MAPT industries.
can add to the potential MAPT workforce. To be even more

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 206
11.5. Conclusion: Semiconductor Workforce Development Must
Be a Holistic Effort
The preceding discussion highlights the many facets of MAPT 3. Winning hearts and minds
workforce development required to meet the increasing Winning the hearts and minds of students and prospective
demands of the microelectronics industry. Three specific employees requires developing awareness and excitement
areas were addressed, all of which are required to build and of the semiconductor industry, along with its global
maintain an effective workforce necessary for the expanding impact. Increasingly, students are interested in careers
U.S. MAPT industry. that can “change the world” and are impacted by what
they hear, see, and experience starting at a young age.
1. Accurate supply/demand modeling
Thus, building awareness and excitement starts with STEM
To best plan for the workforce needs, an effective supply/
education, but it must go beyond existing programs to add
demand model is imperative, including KSA, timelines,
more emphasis on microelectronics and semiconductors.
and numbers, as well as pathways specific to national and
regional areas and different demographics. Without such
There is a crisis situation for technicians and operators,
a model as highlighted, there is no clarity as to where,
which has a unique combination of challenges. The pipeline
when, and how to target the workforce pipeline with
to be developed is hyperlocal, i.e., employees typically come
the needed KSA in order to evolve with the industry.
from the local community where the jobs are located. The
2. Models for effective engagement pipeline, however, is currently small and static for such
Effective engagement methods need to be identified along jobs, so technician and operator jobs are currently going
with a cost/impact estimation (leveraging the supply/demand unfilled, and the number of such jobs is expected to grow
model) that can be scaled for significant impact. There are significantly in communities across the U.S. as the CHIPS
already many very good examples in pockets across the U.S., Incentive Funding is released.
which should continue, but many are not scalable to have
The time to act is now!
nationwide industry impact as needed for the future.
There needs to be continued analysis to identify gaps/
opportunities and make the improvements to meet demand.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 207
Contributors
Carol Handwerker (Purdue University) – Chair Robert Geer (SUNY Poly) Colin McAndrew (NXP)
(through 7/30/2023)
Kai Glass (SRC) Chris Mitchell (IPC)
Jim Wieser (Texas Instruments) –Vice Chair
Jacqueline Hall (SRC) Melinda Murdock (Intel)
Doreen Edwards (RIT) –Vice Chair
David Hernadez (IPC) Umit Ogras (UW-Wisconsin)
Michaela Amoo (Howard University)
Jayashree HV (Qualcomm) Debo Olaosebikan (Kepler Computing)
Shyam Aravamudhan (N.C. A&T State
University) Angela Hwang (Synopsys) Chris Olsen (Applied Materials)

Navid Asadi (University of Florida) Hensu Jang (SK hynix) Mark Oneill (Innovation Impact Partners)

Harish Balan (Synopsys) Jack Judy (University of Florida) Mark Poliks (SUNY Binghamton)

Eric Batten (Texas Instruments) Mohamed Kassem (eFabless) Madhukar Rao (Innovation Impact Partners)

Khaled Benkrid (Arm) Lionel C. Kimerling (MIT) Janine Rush-Byers (Micron Technology)

Aditi Bhandari (Texas Instruments) Shari Liss (SEMI) Alan Seabaugh (University of Notre Dame)

Ambika Carter (GlobalFoundries) Jyoti Malhotra (NIST) JIhoon Seo (Clarkson University)

Ramesh Chauhan (Qualcomm) Gabriele Manganaro (MediaTek) Nitin Shah (MITRE)

Katy Crist (TEL) Amy Marconnet (Purdue University) Greg Snider (University of Notre Dame)

Sean Eilert (independent) Arturo Mateos (Northrop Grumman) Quinn Spadola (NNCO)

Mark B. Fuselier (Micron) Amrita Mathuriya (Kepler Computing) Kashyap Yellai (SRC)

Willie May (Morgan State University) Zoran Zvonar (Analog Devices)

References for Chapter 11

“Chipping In – The Positive Impact of the Semiconductor Industry on the American Workforce and How Federal Incentives Will Increase
1

Domestic Jobs” SIA-Impact_May2021-Final_May-19-2021. https://www.semiconductors.org/wp-content/uploads/2021/05/SIA-Impact_

May2021-FINAL-May-19-2021_2.pdf

Elaine Seymour and Anne-Barrie Hunter, editors. Talking about Leaving Revisited : Persistence, Relocation, and Loss in Undergraduate STEM
2

Education. Cham :Springer, 2019

PEW Research Center, April 2021, “STEM Jobs See Uneven Progress in n Increasing Gender, Racial and Ethnic Diversity,”
3

“Best Practices for Diversity and Inclusion in STEM Education and Research: A Guide by and for Federal Agencies,” A report by the Interagency
4

Working Group on Inclusion of STEM Federal Coordination in STEM Education Subcommittee, Committee on STEM Education of the National
Science and Technical Council, September 2021.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 208
 Draft timeline summary

Key WFD Focus 1 Year 3 Years 5 years 10 years

Supply/Demand • Develop a community • Map KSA and jobs to • Update mapping • Update mapping
Modeling to drive the local, regional, and of KSA and jobs to of KSA and jobs to
development of national education and regional needs. regional needs.
supply/demand training needs/jobs. • Update models • Update models
pipeline model and • Adjust models to to incorporate to incorporate
KSA framework to incorporate workflow workflow changes workflow changes
accelerate MAPT WFD. changes as a result based on needs and based on needs and
• Industry-aligned and of automation, AI, methodologies. methodologies.
validated MAPT KSA business models, • Validate that supply/ • Validate that supply/
for specific job types and supply chain demand modeling, demand modeling,
linked. development. KSA matrix, links to KSA matrix, links to
• Set priority list • Validate that supply/ education and training education and training
for validated data demand modeling, have impact using have impact using
collection over time. KSA matrix, links to metrics. metrics.
education and training
• Conduct initial impact
have impact using
scenario analysis.
metrics.
• Develop metrics for
utility of approach in
MAPT WFD.
Winning Hearts • Develop and launch • Measure effectiveness • Assess progress
and Minds MAPT awareness of MAPT awareness and effectivenss
campaign aimed campaign and refine. of national MAPT
at K-12 students, ecosystem. Identify
• Assess progress
teachers, and families. and disseminated best
on regional MAPT
practices.
• Engage existing STEM ecosystems.
regional STEM Identify best practices
ecosystems and build plans for
to understand scaling successful (or
challenges and promising) models.
identify opportunities • Results from Gallup
to leverage existing survey incorporated
networks to build into MAPT “winning
MAPT STEM hearts and minds”
ecosystem. strategies and WFD
• Develop plan and programs.
secure funding to
support.
• Develop plan driving
a “whole of nation”
approach, including
underrepresented
groups, HBCUs and
MSIs, CCs, colleges
• MAPT Impact –
“change the world”
campaign initiated.
• Gallup survey
designed and funded.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 209
 Draft timeline summary (cont.)

Key WFD Focus 1 Year 3 Years 5 years 10 years

Effective • Existing program • Selected programs • Ongoing assessment • Ongoing assessment
Engagement metrics evaluated operational. of platform of platform
for effectiveness and effectiveness with effectiveness with
• New programs
prioritized for scaling. new content and new content and
developed and pilots
technologies added technologies added
• Gaps in existing in evaluation. Industry
as they become as they become
programs determined engaged in K-12
available, including available, including
with industry engaged awareness to meet the
updated existing updated existing
in filling the gaps. U.S. workforce needs.
content. content.
• Clear metrics for • Results-driven
success defined for strategies developed
WFD programs and and tested to increase
investment. the number of
individuals prepared to
• Industry supported
work in the MAPT.
mentorships,
scholarships, • Assess the scaling
apprenticeships, effectiveness of
internships-in-place. programs for MAPT
education and training
• Goals, metrics, and
platform.
organization defined
for online, open- • Communication/
source education and marketing plan
training platform. established and
underway.
• Develop design
and assessment • MAPT education and
framework and training platform
operational process online covering:
for online, open- industry awareness
source platform. and promotional
material mentorships,
• Incorporate Industry,
scholarships and
community colleges,
internships
universities, and
nonprofits for • Open-source K-12
content. materials; online
• Identify approaches certificate programs
apprenticeships
to mentoring,
and earn-and-learn
community support,
programs and
and other services
to introduce and • Teacher training and
retain students in the best-practice sharing.
pipeline. • Web analytics used to
• Web analytics used to monitor effectiveness
monitor effectiveness of components of the
of the platform. platform.

Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 210
Appendix
Supply/Demand Modeling resources:
KSA matrix details
Full list of roles & specialized skills in semiconductor industry

Winning Hearts and Minds resources:

STEM ecosystem Career and technical education

• ERIC - ED590474 - Charting a Course for Success: America’s • What we know about Career and Technical Education in high
Strategy for STEM Education. A Report by the Committee school (brookings.edu)
on STEM Education of the National Science & Technology
• Advanced CTE Website Home | Advance CTE (careertech.org)
Council, Executive Office of the President, 2018-Dec

• STEMM Opportunity Alliance Veterans

• FACT SHEET: Biden Harris Administration Announces Bold • NSF 101: Expanding pathways to STEM careers for veterans |
Multi-Sector Actions to Eliminate Systemic Barriers in NSF—National Science Foundation
STEMM | OSTP | The White House

Broadening participation in STEM

• Encouraging Girls in Math and Science

• Broadening Participation in STEM | CADRE (cadrek12.org)

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Challenge Promising Technology Key Finding Trend Need for Foundational Capabilities 211