Energy-Efficient Design of Approximated Full

Adders
Pedro Aquino Silva and Cristina Meinhardt
Departamento de Informática e Estatı́stica, PPGCC, Universidade Federal de Santa Catarina, Brazil
[email protected], [email protected]

Abstract—This work analyses a set of approximate full adder blocks [6]. The literature shows that many works explore AC
circuits in 7nm FinFET device technology in order to identify how on arithmetic blocks at architectural or Register-Transfer Level
energy-efficient these designs are for different voltage operation (RTL) [3] [5] [7] [8]. However, few works investigate AC
points. The behavior in a specific environment with voltage
scaling is compared to conventional exact adders. The results techniques applied to the transistor level of full adders. There
allow designers access to the pros and cons of each design in is a lack of electrical level evaluation of approximated tech-
error-tolerant applications. Considering the impact on delay and niques, and voltage scaling approaches applied together in the
power consumption, approximate XNOR and PTL based FAs same circuit, furthermore considering a multigate technology
showed increase in PDP for all voltages applied. However, Mirror nanometer node.
Adder inspired approximate designs showed a reduction in PDP
at 0.4V. The PDP for buffer approximated FAs remained constant This work provides a comparison of a set of FA circuits
throughout voltage scaling. at a FinFET nanometer technology. The main goal is to
Index Terms—approximate computing, full adder, low-power identify how these designs behave in a specific environment
compared to conventional exact adders, when combining AC
I. I NTRODUCTION
techniques and voltage scaling [9], analyzing performance,
Approximate Computing (AC) is an emerging research area power consumption, and Power-Delay Product (PDP). This set
capable of providing excellent results on energy savings [1], of information contributes to designers better understanding
which exploits the fact that many applications do not have of the AC full adder alternatives and choosing the most
exactness as the central requirement. In the last years, AC appropriate adder for a specific application.
has been explored in hardware and software development
for different contexts, including video and sound processing, II. A PPROXIMATE F ULL A DDERS
Internet of Things (IoT) devices, fault-tolerant environments,
computer vision, machine learning and sensor networks [2]. The FA is the base of most arithmetic operations, such as
There are many error-free computations where exploring subtraction, multiplication and division, and, as such, is the
AC enlarges the design space with the addition of quality main cell of the Arithmetic Logic Unit (ALU) of computing
metrics [3]. Some of the opportunities for Approximate Com- systems. While the functioning of an adding cell is not very
puting are applications that [3] [4]: complicated, taking into account the frequency of its use, the
1) process noisy real-world data, such as those coming electrical behavior of FAs becomes critical for the performance
from sensors, or IoT uses; of the system. These circuits consist of three inputs, the two
2) have final results which will be perceived by human bits from the operands (A and B) and a carry-in (Cin), and two
senses, as many problems in Inference and Vision; and outputs. The sum (S) output is given in the Equation 1, and
3) are based on inherently imprecise algorithms, in which the carry out (Cout) is described in the Equation 2. Various
the concept of a correct result is replaced by a range transistor arrangements implement 1-bit adders. Each design
of acceptable results, for example, recognition, data has advantages and disadvantages regarding the area, delay,
analysis, and machine learning. and power consumption.
The primary motivation for the development of AC solutions In this work, eight different full adder topologies were
is the increased demand for low-power designs [5]. Nowadays, chosen and analyzed. Two of them are exact full adders,
in deep nanotechnology designs, battery life is a significant namely the Exact Mirror Adder (EMA) and Exact XNOR
factor to be considered. Many applications involve a large Adder (EXA) [10], respectively Figs. 1 and 2. The other
number of arithmetic operations that explore in-depth the topologies are three approximations based on the EMA, pre-
adding modules. The add operation is, as such, the main sented in Figs. 3(a), 3(b) and 3(c), and two simplifications of
arithmetic function in computer systems and the base of the the EXA [11], whose circuit is shown in Figs. 4(a) and 4(b).
most commonly used arithmetic blocks. Thus, a digital system Finally, a simple buffer approximate FA (BXFA) is the also
has the 1-bit full adder (FA) as one of the most critical basic evaluated where the Sum output is defined by propagating
blocks of an arithmetic unit. the A input, and the Carry-out output follow the B input. To
The performance of a FA cell is a vital point to be decouple the output from the input, in the BXFA insert two
improved to achieve low-power, fast operations on arithmetic inverters in cascade from the selected input to the output.

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 fails for the same two input vectors that AXA3, but it provokes
S = A ⊕ B ⊕ Cin (1) only three output errors as the ED in total. The most critical
inputs are 010 (except the AXA2 topology) and 100 (except
Cout = (A · B) + (A ⊕ B) · Cin (2) the AMA1 and BXFA topology).

TABLE I: Truth tables for an exact adder and the evaluated

approximations.
INPUT EXA SMA AMA1 AMA2 AXA2 AXA3 BXFA
A B Cin S Cout S Cout S Cout S Cout S Cout S Cout S Cout
000 0 0 0 0 1 0 0 0 1 0 0 0 0 0
001 1 0 1 0 1 0 1 0 1 0 1 0 0 0
010 1 0 0 1 0 1 0 0 0 0 0 0 0 1
011 0 1 0 1 0 1 1 0 0 1 0 1 0 1
100 1 0 0 0 1 0 0 1 0 0 0 0 1 0
101 0 1 0 1 0 1 0 1 0 1 0 1 1 0
110 0 1 0 1 0 1 0 1 1 1 0 1 1 1
111 1 1 1 1 0 1 1 1 1 1 1 1 1 1
ED - - 2 1 3 1 3 2 4 0 2 0 4 2

Fig. 1: Exact Mirror Adder (EMA). TABLE II: Transistor and error count for each approximate
topology
Topology Transistor count Failure inputs Fail count
SMA 16 010, 100 2
AMA1 11 000, 010, 111 3
AMA2 11 010, 011, 100 3
AXA2 6 000, 001, 100, 110 4
AXA3 8 010, 100 2
BXFA 8 001, 010, 101, 110 4

III. M ETHODOLOGY
The goal of this work is to show the energy-efficiency of
AC FAs design. For this, the reduction in power consumption
Fig. 2: Exact XNOR Adder (EXA). provided by the use of approximate FA cells is evaluated for
different voltage points, while observing the impact on delay.
The most traditional architecture is the Mirror CMOS In particular, the effects of AC combined with the savings
EMA, chosen as a base for comparison between the stud- known to be provided by voltage scaling techniques [9] are
ied topologies. It is composed of 24 transistors structured explored, in order to find the overall most efficient low-power
in logically complimentary pull-up and pull-down networks. adder cells within acceptable accuracy restraints.
The advantages of this circuit are good conductibility and The topologies are described under the model provided by
robustness when working with small technologies and lower the 7nm FinFET ASAP7 PDK [13], and simulated in HSPICE.
tension. However, the EMA shows high input capacitance, and All designs adopt three fins, as recommend by the design rules
the impact of the pull-up network makes the circuit’s operation provided by the ASAP7. The nominal supply voltage for these
slower [12]. On the other hand, the EXA uses Pass Transistor devices are 0.7V [13]. The voltage was reduced in steps of
Logic (PTL) to reduce the number of transistors, having ten 0.1V until the noise levels were too great to provide correct
devices in total. This circuit was chosen as an example of functioning, or the delay was too large to be used in operation.
low-power and area-efficient design in FAs [10] [11]. The threshold voltage is approximately 0.3V, thus, we define
The approximations exploit the relaxation of numerical ac- as near-threshold operation the results obtained for voltages
curacy and were designed with diminished logical complexity between 0.4V and 0.2V. In order to emulate a more realistic
to reduce the number of transistors and power consumption. scenario, two inverters were used as a load in each input and
Therefore, they present differences in their truth tables, as both Cout and Sum outputs of the FAs circuits are connected
shown in Table I, along with the error distance (ED) as a to a FO4 inverter.
figure of merit to compare the AC FAs. The input vectors The experiment considers the exhaustive evaluation of all
that generate failure when compared to the exact full adder transition arches of each FA Truth Table. Thus, complementary
implementations are summarized in Table II. Notably, the to the error-distance and the critical delay, the power con-
BFXA is the topology that produces the largest number of sumption is determined by the average power result for all the
errors while the AXA3 is the topology with least error- transition arcs. This work also considers a figure of merit the
inducing input vectors with only an ED of two. SMA also product of power consumption and critical delay Power-Delay

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 (a) Simpĺified Mirror Adder (SMA). (b) Approximate Mirror Adder 1 (AMA1) (c) Approximate Mirror Adder 2 (AMA2)

Fig. 3: Approximate FAs inspired by the EMA.

(a) Approximate XNOR Adder 2 (AXA2). (b) Approximate XNOR Adder 3 (AXA3)

Fig. 4: Approximated FAs based on the EXA

Product (PDP) for the eight adders under nominal and later TABLE III: Effects of Voltage Scaling on Power (nW)
with reducing voltages. Topology 0.7 V 0.6 V 0.5 V 0.4 V 0.3 V
EMA 772.15 509.54 334.19 197.54 105.58
IV. E FFECTS OF VOLTAGE S CALING T ECHNIQUE SMA 539.93 357.10 231.50 136.73 71.85
When applying voltage scaling in conjunction with full AMA1 659.75 435.60 271.08 159.93 84.95
AMA2 418.31 263.40 171.83 102.30 52.95
adders developed in an Approximate Computing design space, EXA 271.92 175.02 109.23 61.29 31.66
the evaluated topologies showed some advantages and disad- AXA2 128.18 85.90 57.25 33.36 17.98
vantages, as present the Table III, the Table IV, and the AXA3 60.90 40.32 27.45 16.40 8.89
BXFA 279.53 176.25 114.50 66.67 35.20
Fig. 5. There was evident improvement in power consumption,
the main focus of the voltage reduction technique, shown in
TABLE IV: Effects of Voltage Scaling on Delay (ps)
Table III. All designs appear to be good candidates to voltage
scaling, with an average reduction in power dissipation of Topology 0.7 V 0.6 V 0.5 V 0.4 V 0.3 V
EMA 12.28 13.80 24.01 42.51 122.80
34% for each topology when stepping from 0.7V to 0.6V. SMA 13.07 14.34 19.46 35.28 117.30
In near-threshold operation of 0.3V, the power consumption AMA1 9.45 11.74 16.27 29.69 98.76
reduced on average by 86.69%, being lowest in the AXA3 AMA2 8.72 9.52 13.22 25.64 81.62
EXA 52.60 104.80 220.50 495.20 714.20
design (8.89nW, in absolute value). Although BXFA does not AXA2 57.40 116.30 248.50 546.20 828.40
stand out in terms of power reduction, it shows the best result AXA3 40.49 84.25 188.30 412.10 418.00
for delay at near-threshold voltages. Thus, voltage scaling BXFA 6.42 8.14 10.72 23.04 63.25
successfully obtained results in energy saving when using
these AC adder cells.
The most significant drawback of voltage scaling is the were also the worst-performing when considering timing anal-
increased critical delay in all FA architectures. The XNOR- ysis, as shown in Table IV. Overall, the adders analyzed are,
based adders are by design optimized for low-power operation on average, 9.32× slower in near-threshold operation (0.3V),
and have the disadvantage of more considerable delay when with the worst-case found in the AXA2, which has a delay of
compared to the Mirror Adder versions. XNOR topologies 13.37× that found in nominal voltage operation.

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 Since voltage scaling presents such advantages and draw- was well adapted for operation in all voltages applied, and is
backs, Power-Delay Product (PDP) will be used as a metric to also a good option when considering PDP.
trace a relation between the gains in power and the increase Some approximate circuits studied will not provide better
on the delay. All circuits showed rise in PDP when comparing power efficiency when reducing the operation voltage, es-
operation in near-threshold and nominal voltages. Notably, the pecially when considering the increase in critical delay. In
XNOR-based FAs showed continuous increase up until 0.4V, near-threshold operation (0.3V), none of the circuits, except
as seen in Fig. 5. the BXFA, showed improvement in Power-Delay Product,
The best alternative considering both power and delay is the having a 37% increase on average. Notably, the XNOR adders
BXFA, that reaches the best results for all evaluated cases. This are not well suited to voltage reduction, as there was no
topology keeps the PDP practically constant independently of reduction in PDP whatsoever for none of the voltages applied.
the voltage applies, as the reduction in power consumption As future work, this project will investigate the impact of
was proportional to the increase in delay, especially when adopting these approximated full adders on n-bit adders and
compared to the variations in PDP seen in the other adders. error-free applications, such as Machine Learning and video
Therefore, despite the ED, the BXFA is an interesting ap- applications.
proach for applications that require a good trade-off between
ACKNOWLEDGEMENT
power and delay.
The second best option observing PDP is the AMA2 op- This study was financed in part by the Coordenação de
erating in 0.5V, that is, 2.27aJ. However, for applications Aperfeiçoamento de Pessoal de Nı́vel Superior - Brasil CAPES
considering the error-distance, the power reduction and the - Finance Code 001, the National Council for Scientific and
PDP, a good solution could be exploring the AXA3 circuit at Technological Development – CNPq and the Propesq/UFSC.
nominal or at 0.4V (lowest power, but high delay). R EFERENCES
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