Computer Engineering Department

CMPE361: Computer Organization

Lab 3.1: Datapath Design
Deadline: 24 November 2024, 23:59PM

1. Introduction
In this lab, you will build the datapath of a MIPS single cycle processor (SCP) as shown in Figure
1 using system Verilog. You will use MARS simulator for writing, executing, and testing the
programs. Before starting this lab, you should be very familiar with the single-cycle
implementation of the MIPS processor described in Section 7.3 of your text, Digital Design and
Computer Architecture. The single-cycle processor schematic is given in Figure 2. This version of
the MIPS single-cycle processor can execute the following instructions: add, sub, and, or, slt, lw,
sw, beq, addi, and j.

Figure 1: Block representation of single-cycle MIPS processor

1
 Jump MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
0 25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0 Result
1 A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
PCJump 15:11
1
WriteReg4:0
PCPlus4
+

ImmExt
4 15:0 <<2
Sign Extend PCBranch

+
27:0 31:28

25:0
<<2

Figure 2: Schematic of single-cycle MIPS processor

Note that SystemVerilog modules for basic building blocks, needed for constructing the datapath,
are given in the text book. You are supposed to study them on your own and use them as needed.
The datapath has quite a few submodules. Make sure you understand why each submodule is there
and where each is located on the MIPS single-cycle processor schematic. You’ll notice that the
ALU module is not defined. Use the ALU module you designed in Lab 1.2. Be sure the module
name matches the instance module name (ALU), and make sure the inputs and outputs are in the
same order as in they are expected in the datapath module.

2. Assignment
Design the datapath that supports following instructions: addi, add, sub, and, or, slt, lw, sw, beq,
and j. The skeleton for required module containing the port list of the datapath, as shown in the
Figure 1, is given below:
module datapath(
input logic clk, reset,
input logic memtoreg, pcsrc,
input logic alusrc, regdst,
input logic regwrite, jump,
input logic [2:0] alucontrol,
output logic zero,
output logic [31:0] pc,
input logic [31:0] instr,
output logic [31:0] aluout, writedata,
input logic [31:0] readdata);
//complete the module
endmodule

2
You are required to complete the module and submit it. Note that the instruction and data memories
are not part of the datapath. After completing the datapath module you should test it for all ten
instruction (i.e. addi, add, sub, and, or, slt, lw, sw, beq, and j). A sample testbench is given below:
// Code your testbench here
module tbDataPath();
logic clk, reset, memtoreg, pcsrc, alusrc, regdst, regwrite, jump;
logic [2:0] alucontrol;
logic zero;
logic [31:0] pc, instr, aluout, writedata, readdata;
int errors = 0;
datapath dut(clk, reset, memtoreg, pcsrc, alusrc, regdst,regwrite, jump, alucontrol, zero, pc, instr, aluout, writedata, readdata);

initial begin
// reset the pc
clk=1; reset=1;
{regwrite,regdst,alusrc,memtoreg,pcsrc,alucontrol,jump}=9'bxxxxxxxxx;
readdata=32'd54;
#5
$strobe("aluout = 0x%x, zero=0b%b, writedata = 0x%x, pc = 0x%x", aluout, zero, writedata, pc);
#5

//addi $s0,$0,5
clk=0; reset=0; instr=32'h20100005; {regwrite,regdst,alusrc,memtoreg,pcsrc,alucontrol,jump}=9'b101000100;
#5 clk=1;
#5
$strobe("aluout = 0x%x, zero=0b%b, writedata = 0x%x, pc = 0x%x", aluout, zero, writedata, pc);
#5

//addi $s1,$0,10
clk=0; instr=32'h2011000a; {regwrite,regdst,alusrc,memtoreg,pcsrc,alucontrol,jump}=9'b101000100;
#5 clk=1;
#5
$strobe("aluout = 0x%x, zero=0b%b, writedata = 0x%x, pc = 0x%x", aluout, zero, writedata, pc);
#5

//add $t0, $s0,$s1

clk=0; instr=32'h02114020; {regwrite,regdst,alusrc,memtoreg,pcsrc,alucontrol,jump}=9'b110000100;
#5 clk=1;
#5
$strobe("aluout = 0x%x, zero=0b%b, writedata = 0x%x, pc = 0x%x", aluout, zero, writedata, pc);
#5

//j next (to address 1c)

clk=0; instr=32'h08100007; {regwrite,regdst,alusrc,memtoreg,pcsrc,alucontrol,jump}=9'b000010001;
#5 clk=1;
#5
$strobe("aluout = 0x%x, zero=0b%b, writedata = 0x%x, pc = 0x%x", aluout, zero, writedata, pc);
#5

//No op (repeats the previous)

#5 clk=0;
#5 clk=1;
$strobe("aluout = 0x%x, zero=0b%b, writedata = 0x%x, pc = 0x%x", aluout, zero, writedata, pc);

end
endmodule

3
Note that the first instruction in the testbench resets the PC to 0. The following table could be used
to compute the 32-bit instruction and other control signals for the execution of the instructions:
Assembly code Machine code {regwrite, regdst, alusrc, memtoreg, pcsrc, alucontrol, jump}
addi $s0,$0,5 0x20100005 101000100
addi $s1,$0,10 0x2011000a 101000100
add $t0, $s0,$s1 0x02114020 110000100
j next 0x08100007 000010001

3. Submission and Evaluation

Place all your module files in a SINGLE folder, name it as StudentName_ID_Lab3p1, compress
it as .zip and upload to the LMS. Your module will be evaluated with an evaluation testbench to
check the correctness of your design (for all ten instructions) using Aldec Riviera Pro 2023.04
simulator.
The lab submission will be evaluated out of 100. Important considerations for the lab evaluation
are:
1. Correctness of the module
2. Plagiarism (a submission that is copied from any other sources will result 0 grade)

There will be no individual quiz for this lab assignments. However, it will be included in quiz 3.