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Week 10 PMRF

The document discusses the calculation of subthreshold leakage currents for various technology nodes, specifically focusing on 65nm and NANO technologies. It includes parameters such as subthreshold slope, body effect coefficient, and leakage current values for NMOS and PMOS transistors. Additionally, it touches on the design and analysis of VLSI subsystems and various CMOS latch configurations.

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R INI BHANDARI
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14 views11 pages

Week 10 PMRF

The document discusses the calculation of subthreshold leakage currents for various technology nodes, specifically focusing on 65nm and NANO technologies. It includes parameters such as subthreshold slope, body effect coefficient, and leakage current values for NMOS and PMOS transistors. Additionally, it touches on the design and analysis of VLSI subsystems and various CMOS latch configurations.

Uploaded by

R INI BHANDARI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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pees kie! =. 1) For 65nm technology node, find the subthreshold leakage current for a stack 1 point oa eee r am anae m Mp ubthreshold slope = 100mVidecade = S cee cee aenen io) ze — Body effect coefficient = 0.066 = Ky m - ore a oar we Weta) Heo 4 ter 7 oot, Pde boo sa WC trinie, ~ SHA, 0.2988 |; 0-06 60-9) (Vey -Va - Yho om wer ao, fe mms T (ona) + OCYRo Tog= Tey ol a ae 36 = lo CA drome IL e tow te Ty co (ep Des) AR Tey lo oN yy okt yy ro le fot) = 2884 are stay O-\ act >@ aa rae fe arerenet 7 £ tl My-0-Non) OD Isha = 75 fe ont ol (y-t dwt ol (wry)-0-08yy = o-\yce'l HAh2ECVY + Orly =O 2“@ Now, feos aquation ®omd G-we get- Be oye Cia Onl Vy - orf D> pp boNa + Olry Fol =© wg @ and ©. ce get, Mé Cre S&B ) Bees ain \ ot em GFZ B we 0:00 6429 V Seer : aS Gls) See eee (0° POG 726) =O 2504 The BI : aL (2 2678 =| o-] Cutan) =Tq [oor ') ee Tesh = Lege lo 2) Fin the same as question] fer NANO loge oF 100" ands = 5.63 na Mod tA \ on 2.05 nA 4 \ Nop VE 4 Ole o 845 codthnitnit098ssesment=177 FW oACr ofr Design and Analysis of VLSI Subsystems -- Unit = 6.066 ny 8) 1.568 nA = -Na- 0: Vx) —~ 0°66 CVn) os wy | Ea Oat) ont er to Toy = Typ [goer ) 0 otf core) = pra! 36 © ad (& Free © oO Tasty Tub, = Fade fol Se on (0-3 +Val— 6:0 66Vq = alvn-0'l D y= £92 _ @. of K29vV eee a Fro. @, Scones a xl) eo a ee picuie = SROSiD lo) oN = Seam (O18) T 0°6294 19% He! 3). Given that Ijete for NMOS is 6.3 nA, find the gate leakage current for the NAND logic “1 10". Use the parameters mentioned in question (1). Sr ta, bd wen = Ny | —] QR x as i ee a See EN ty tw 7 Et = da al CORE aye Meare 2815 nA »: SoA (= :). Ga, =O 2 ea On; o Be = 1Cus We) tubo I) lo Ss Ey Ona. eon ~ ood (2°) =T, |o i o-( SINE moo Paty loan Gon Glo )4 = 315404 4) For 65 nm technology node, find the subthreshold leakage current for a 2-NOR, loge 11" ven that Subthreshold slope = 100mV/decade = S AIS DIBL coefficient = 100mVV <= Body effect coefficient = 0.066 = “Ke? Subthreshold leakage curent for asingle NMOS transistor = 8.630 = Gu ny = 4p. op Stine ermntrrameusienne em oe ae Sy - 4.415 nA MA aan — * 4.65 nA > \ —4 je 3 a 7 a [aes oo o ee 7" tpt (ea 6) - HM) Sub = k we wi aot (aden) ~ ie = Ty i ye ~y wor Oo ) (a Doel (ra-° -') Kalb Run = % ifs ee) oe Gace ot De oot ges = Ly | or 28) Fem Q onl D- vead own, o.\™ = (a ‘) Pee Gung vy) 0-066 @ ) a eb C6 D>vaCit+ of +? eatod 066) = ites > a= molaliSean So nel eae) ee Poise By lee (2: Ba) Is es pe eeean mem omeeenerec meters tees rae; specications eae No aes L Mrmmanacatrtonhy = Somio® x 12 x0-02 5 (aptod+ 50 x10° transistors = Ny Ws eee - OOS, 25% :tow age devcna > Heyl ST [io 5%: High leakage devices > Lavo VT I Memory devices consist of: lettre eskage for High Vy = 10 num Sa eamisos = Ny - Tsuy p= 21s oy actor = 002 vi {tO Ln ntage docs > Pagla VT 0.08 w 1 oi as ( St 75mg = Now oy ih o20w = agentes x 4X 00%, Be SE a = > Se ; A _ =) o2its +r | Bree nea at Keubmn ices A ee ee eee Ww = Sal [osensS xan cee) ae + Colo x 1269 284A) =m Dynio® + set] Se pe Sie east « Tyte keoteg c osc d puna = (Bub + Tost) y sat pons Some 5) 4p Ca kt eae) Z a Ss (An NMOS pass transistor acting as a CMOS latch i only sensitive to input noise. F- NG; (i) An transmission gete acting as a CMOS latch attains full swing, T.. Ypnolse— ST (i) An ern blr acting a a CMOS chs en eanatnn onp rai g~” LP~OTSES Place \oa-ME (iv) A buffer inverter acting as a CMOS latch is only sensitive to input noise, _—__ NG a True; True; Tue; False — 1; Fal ° 2 Sor 5 Jo 6) Select the correct option: ne Co > 4 6 om A 17) Solet the correct option: point (0Te switching resistance is low in Inverted Butter & ence delay is ow. [_ (i) Logica effort ofthe tristate inverter is lesser than that of the inverter-butfer = {89 CMOS Latch with ouput feedback ang input Inverter ha ouput sta but is nena to 2 | SS ee eT ee ‘True; True; True; False es 2) treo DS] 6 y bee A 4 - oo ele Oy Fon Sighe NOt, Pn ee ee +p 2 a S D = Edam et Reg, (J = By Pp forty ee Gee POD. Sey oo. 2 sz crear me ? A ry sez i eee coong |) (A Jam latch saves 2 tansistrsin the feedback path. “T— (A Jamb late increases clock load. F= 9) For 65 nm technology nove, find the subthreshold leakage current for a2-NOR logic10" given that: Nee Cony) CH) a Ae Sc a (a ore rer) solid = if lo o-( Peo (ic) = Ty Jo =u = 0952? (o3» 4) = 4 bé8 She Te Tp 4: bint 10) For 65 ren technology node fn the subtrshol akage cuentora2-NOR 1 point vy lsie“00, gen nat DD Subtostod slop = f00n\/decade 6a DIB satel « 10m Bos et cncrt = 005 o 4 Subthreshold leakage cutent for a single NMOS transistor = 5.63 nA, ) ‘Subthreshold leakage curent for a single PMOS Wansistor = 9°3 0K 7 AoPigl or ae a oe at 82 ma oo 6-9)4 o1C1-2 -D 0.06662) =9)t Cine a oor ana, s sub = Te, lo CT = 14 @ s. 6a ca Ty e ee sea * Tout tintretd dodod = 2Tiuby = = [h2ent ew >

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