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Kapak

The document presents the results of Experiment #4 in Logic Circuit Design Laboratory, focusing on half adders and full adders. It includes truth tables for both circuits, detailing the inputs and corresponding outputs for various combinations. The half adder and full adder are analyzed with specific input values and their resultant sum (S) and carry-out (Co).

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Joseph Öztürk
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11 views8 pages

Kapak

The document presents the results of Experiment #4 in Logic Circuit Design Laboratory, focusing on half adders and full adders. It includes truth tables for both circuits, detailing the inputs and corresponding outputs for various combinations. The half adder and full adder are analyzed with specific input values and their resultant sum (S) and carry-out (Co).

Uploaded by

Joseph Öztürk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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GAZI UNIVERSITY FACULTY OF

ENGINEERING DEPARTMANT OF
ELECTRICAL AND ELECTRONICS
ENGINEERING

Logic Circuit Design Laboratory

CANER ACAR 201110026

YUSUF ERKAN 201110086

Experiment #4
Half adder
A=0 B=0 S=0 Co=0

A=1 B=0 S=1 Co=0

A=0 B=1 S=1 Co=0


A=1 B=1 S=0 Co=1

The truth table of half adder

Inputs Outputs

A B S Co

0 00
0

1 00
1
1 01
0
0 11
1 FULL ADDER
A=0 B=0 Ci=0 S=0 Co=0
A=1 B=0 Ci=0 S=1 Co=0

A=0 B=1 Ci=0 S=1 Co=0

A=0 B=0 Ci=1 S=1 Co=0


A=1 B=1 Ci=0 S=0 Co=1

A=1 B=0 Ci=1 S=0 Co=1


A=0 B=1 Ci=1 S=0 Co=1

A=1 B=1 Ci=1 S=1 Co=1

The truth table of full adder


A B Ci S Co
0 0 0 0 0

1 0 0 1 0

0 1 0 1 0

0 0 1 1 0

1 1 0 0 1

1 0 1 0 1

0 1 1 0 1
1 1 1 1 1

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