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Exp No 6

The document is a lab workshop manual for an ARM Based SoC Design course at the National Institute of Electronics and Information Technology, Calicut. It focuses on the design of multiplexers as combinational circuits, detailing software requirements and providing specific boolean expressions to implement using Verilog HDL. The manual outlines various modeling techniques including dataflow, behavior, and structural modeling for the design tasks.

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31 views3 pages

Exp No 6

The document is a lab workshop manual for an ARM Based SoC Design course at the National Institute of Electronics and Information Technology, Calicut. It focuses on the design of multiplexers as combinational circuits, detailing software requirements and providing specific boolean expressions to implement using Verilog HDL. The manual outlines various modeling techniques including dataflow, behavior, and structural modeling for the design tasks.

Uploaded by

Anonymous c75J3yX33
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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NATIONAL INSTITUTE OF ELECTRONICS AND INFORMATION

TECHNOLOGY, CALICUT

Lab Workshop Manual

Lab Workshop on ARM Based SoC Design

Contact Point for the Lab

Mr. Sreejeesh SG

Senior Technical Officer

Email: [email protected]

Ph.: 9447769756 (WhatsApp Preferred)

Prepared by Sreejeesh SG Lab Manual/Verilog HDL

i
Circuit Simulation Lab:6
Multiplexers

Introduction
The purpose of this experiment is to introduce the design of simple
combinational circuits, in this case multiplexers. A multiplexer is a digital
circuit, which is used to select a single input from the multiple input lines.

Software tools Requirement


Modelsim (Siemens)

Xilinx Vivado
Logic Diagram

4:1 Multiplexer

Truth Table

Implement the boolean expression F(A, B, C) = ∑ m(2, 3, 6, 7) using a

Lab Manual-Verilog/ FPGA


multiplexer.

Implement the boolean expression F(A, B, C) = ∑ m(0, 1, 3, 5, 7) using a


multiplexer.

Describe the above in Verilog HDL and capture the Waveforms

1. Dataflow modeling

2. Behavior modeling

3. Structural modeling (Use the gates for designing the Mux)

4. Design the above two problems using structural modeling –


use Muxes as components

Lab Manual-Verilog/ FPGA

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