A low-complexity soft-decision decoding architecture for

the binary extended Golay code

Patrick Adde, Raphaël Le Bidan

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Patrick Adde, Raphaël Le Bidan. A low-complexity soft-decision decoding architecture for the binary
extended Golay code. ICECS 2012: IEEE International Conference on Electronics, Circuits, and
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 A low-complexity soft-decision decoding
architecture for the binary extended Golay code
Patrick ADDE et Raphael LE BIDAN
* Institut Mines-Télécom/Télécom-Bretagne; CNRS Lab-STICC UMR 3192
Technopôle Brest Iroise, CS 83818 29238 Brest Cedex 3
Université Européenne de Bretagne, France
email: [email protected]
Abstract — The (24, 12, 8) extended binary Golay code is algorithm introduced in [9][10]. This algorithm is
a well-known rate-1/2 short block-length linear error- dedicated to rate-1/2 linear codes having a generator
correcting code with remarkable properties. This paper matrix composed of an invertible sub-matrix for the
investigates the design of an efficient low-complexity redundancy part. A double re-encoding process
soft-decision decoding architecture for this code. A
inspired by Chase’s algorithm [11] is used to create a
dedicated algorithm is introduced that takes advantage
of the code’s properties to simplify the decoding process. list of candidate codewords among which the most
Simulation results show that the proposed algorithm likely is retained as the decoder decision. A few
achieves close to maximum-likelihood performance with number of error patterns were shown to be usually
low computational cost. The decoder architecture is sufficient to achieve close to maximum-likelihood
described, and VLSI synthesis results are presented. (ML) performance for short block codes.
The remainder of the paper is organized as follows.
I. INTRODUCTION Section II discusses different approaches to encode
Forward Error Correction has become an important the (24,12) Golay code. Section III introduces the
practical mean for improving the bit error rate (BER) principle and performance of the proposed soft-
performance of digital communication and storage decision decoding algorithm. The design of an
systems. The (23,12,7) binary Golay code is a perfect hardware-efficient decoder architecture with near-ML
binary triple-error-correcting code introduced in 1949 performance is developed in Section IV. Conclusions
[1] with remarkable mathematical properties. The follow in Section V.
addition of an overall parity-check bit yields the rate-
1/2, self-dual (24,12,8) extended binary Golay code II. ENCODING THE (24,12,8) GOLAY CODE
which has found numerous practical applications Since the proposed soft-decision decoder performs
either as a standalone code (for example on the 1977 several re-encoding of the received data sequence, we
Voyager spacecraft mission [2]) or as an inner code in first review different ways to encode the Golay code.
concatenated coding systems [3]. The binary (23,12,7) Golay code can be described
A number of hard-decision algebraic decoding in cyclic form as a quadratic residue code with
algorithms have been investigated over the years (see generator polynomial g(x)=x11+ x9+ x7+ x6+ x5+ x+1
e.g. [2],[4],[5]). In contrast to hard-decision decoders [4]. Thus a 11-stage shift-register followed by an
which operate on binary values, soft-decision accumulator can be used to perform systematic
decoders directly process unquantized (or quantized encoding of the (24,12,8) extended Golay code in 24
on more than two levels in practice) samples at the clock periods.
output of the matched filter, thereby avoiding the loss Another approach directly implements with logic
of information. Over the Additive White Gaussian gates the product of the binary data vector d with the
Noise (AWGN) channel, soft-decision decoding may generator matrix G of the code. Since the extended
offer up to 3 dB coding gain over hard-decision Golay code is a self-dual code, the generator matrix
decoding, but at the cost of increased computational Gd in canonical form can be written as
complexity. Soft-decision decoding algorithms for the Gd = [I12, P]
extended Golay code have also received a lot of where I12 is the 1212 identity matrix corresponding
attention (see [6] and references therein, or [7][8] for to the 12 information bits d, and where P is a 1212
more recent results). Yet very few decoder invertible binary matrix that generates the 12 parity-
architectures have been published ([6] is a notable check bits p. The corresponding codeword c then
exception). This paper addresses the challenging issue reads c = (d, p). From the self-dual property of the
of designing a low-complexity (less than 5,000 gates) extended Golay code, P satisfies the property P-1 = Pt.
soft-decision decoder architecture with near-optimal Thus, in just the same way that the 12 information
performance for the (24,12,8) code. coordinate d are used to compute the parity bits p
The proposed approach is based on the decoding using the generator matrix Gs=[I12, P], the 12 parity
coordinates p may also be encoded using the
alternative generator matrix Gp = P-1  Gd = [Pt, I12] Had Had Had
to obtain the information vector d.
A third method uses the Cortex construction.
Cortex codes are a family of rate-1/2 self-dual linear
block codes first introduced in [12]. As shown in Fig. Had Had Had
1, they combine a very short mother code E with a
sequence of permutations to produce the parity bits. If
the mother code is self-dual, the resulting Cortex code Fig.3: Cortex encoding architecture for the (8,4,4) extended
Hamming code
inherits from the self-dual property [13].

I
-tionally intractable for most codes of practical
E N
E E interest. Brute-force ML decoding of the extended
T Golay code requires correlating the received word
E E E E
R with each of the 212 = 4096 candidate codewords,
L which is computionally feasible yet intensive. A
E
A smarter approach would be to apply a variant of the
V Viterbi algorithm to the 12-sections 16-state tail-
E E E E
R biting trellis representation of the Golay code
introduced in [7]. However, in spite of its apparent
Fig.1: General Cortex encoding scheme build from simplicity, this approach is not the most attractive one
elementary code E when low-complexity (low gate count) and very high
The Cortex structure corresponding to the data rate are sought. For these reasons, we have
extended Golay code is shown in Fig. 2. It is based on chosen to focus rather on the simple and efficient
the (8,4,4) extended Hamming code (denoted H). The algorithm introduced in [10] This algorithm can be
12 information bits d are divided into 3 blocks of 4 applied to any self-dual codes, and is particularly
bits. Each block is encoded by the (8,4,4) code to attractive for short codes for which it offers near-ML
produce 4 parity bits (systematic bits are discarded). performance at low decoding complexity.
The sequence of 12 parity bits is then shuffled by a The algorithm operates as follows. A list of VTs
suitable permutation function, and the whole process candidate codewords is obtained by applying binary
is repeated 3 times in order to generate the parity bits test patterns to the k message bits obtained by taking a
p. The codeword is finally obtained by concatenating hard-decision on the received information sequence,
the 12 systematic bits d with the 12 final parity bits p. and then re-encoding the resulting candidate
sequence. As suggested by Chase in [11], the VTs test
patterns attempt to correct the most likely errors
H H H P patterns confined in the least reliable positions in the
D A received information sequence. The same procedure
A R is applied in parallel to the k parity bits, by inverting
T H H H I the encoding equations in order to re-compute the k
A T message bits from the k parity bits. This produces a
Y second list of VTp candidate codewords. The decoder
H H H
finally selects the candidate codeword at minimum
Fig.2: Cortex Architecture for the extended Golay Code Euclidean distance (maximum correlation metric)
from the received word.
Interestingly, the (8,4,4) extended Hamming code Bit Error Rate (BER) performance vs. Signal to
used as a building block for obtaining the extended Noise Ratio (SNR) of this algorithm for the (24,12,8)
Golay code in Cortex form may also be described as a extended Golay code using 8-bit quantization is
Cortex code. The corresponding Cortex architecture presented in Fig.4 for different numbers VT = VTs +
is shown in Fig. 3 [12]. It is based on the (4,2,2) VTp of test patterns. Binary Phase-Shift-Keying
Hadamard code (Had). (BPSK) transmission over AWGN is assumed.. For
In this paper, we choosed to implement the Cortex comparison purpose, ML performance of this code is
architecture for encoding the (24,12,8) Golay code. also shown. We observe that 32 (16+16) test patterns
are sufficient to obtain close to ML performance
III. NEAR MAXIMUM-LIKELIHOOD SOFT-DECISION (within 0.1 to 0.2 dB) in the simulated BER range.
DECODING OF THE GOLAY CODE
The optimized architecture introduced in the next
ML soft-decision decoding is known to offer the best section uses a total of 48 (24+24) test patterns,
decoding performance but is usually computa- thereby virtually achieving ML performance. These
results demonstrate the attractive trade-off between rate remains a challenging issue. Here, we describe a
performance and complexity provided by this digital implementation tailored to the soft-decision
algorithm. decoding algorithm investigated in the previous
Section. The decoder operates on soft inputs
0 1 2 3 4 5 6 7 quantized on q=3 bits (+ sign bit). A total of VT =
1,00E+00
VTs+VTp = 24+24 = 48 candidate codewords is used
1,00E-01
to generate the decoder decision. The 224 error
patterns are chosen so as to correct the most likely
1,00E-02 errors located in the Lrs = Lrp = 5 least reliable
positions in both the information and parity parts of
1,00E-03
the received vector. The corresponding architecture is
inspired by [14] and is shown in Fig. 6. It consists of
BER

1,00E-04
four main blocks: reception, processing, transmission
1,00E-05 and control.
VTs=4096(ML)

1,00E-06 VT=(16+16)
Control
VT=(8+8)

1,00E-07 VT=(2+2) Counter

Signal Signal
VT=32 Signal
1,00E-08
Eb/N0 in dB Received Error
word Patterns D Metrics Decoded
DBMF Direct Selection
Fig.4: BER performance of the considered soft- encoder compute PISO
wor
Compa-
decision decoder for the (24,12,8) code Reliability Least Error rator
register
Reliable
Patterns P Serial
Bits
RBMF Reverse Transmissio
encoder
The influence of input quantization on the BER
Addition and
performance is studied in Fig. 5. We observe that q=3 SIPO
bits (sign-bit excluded) are sufficient to obtain near- Sign
Memory
Reception
Processing block
Reliability
ML performance (within 0.3 dB at most) with the block

low-complexity algorithm based on 48 error patterns. Fig.6: Proposed soft-decision decoding architecture

Quantification Golay
Inside the reception block, the n=24 soft symbols of
ML 48v 4MF q=7 48v 4MF q=4 48v 4MF q=3
the received word are processed sequentially. This
0 1 2 3 4 5 6 7 8 block first identifies successively the Lrs and Lrp least
1,00E-01
reliable positions within the systematic and parity
1,00E-02
parts of the received word, respectively. In parallel, a
serial-in parallel-out (SIPO) shift-register memorizes
1,00E-03
sequentially the 24 soft samples of the received word.
The processing block comprises three main tasks.
1,00E-04
First, error patterns are generated from the sign bits of
1,00E-05 the received word by testing different combinations
BER

of 0s and 1s in the least reliable bit positions. Then,

1,00E-06
these error patterns are added (modulo-2) to the
1,00E-07
information/parity sequence and the resulting
sequence is re-encoded to produce a codeword which
1,00E-08 is scored (correlation metric). Finally, a selection
function (comparator) identifies the most likely
1,00E-09
codeword within the input list of 48 candidate
1,00E-10 codewords. Note that this process is realized in
Eb/N0 e n dB
parallel for the information and the parity parts of the
Fig.5: Performance of the considered soft-decision received word. Moreover, the metric of each
decoding algorithm vs. the number q of bits used for candidate codeword is computed on-the-fly from the
quantization (sign bit excluded) 24 soft symbols provided by the SIPO shift register,
Finally, the transmission block is composed solely
IV. SOFT-DECISION DECODER ARCHITECTURE of a parallel-in serial-out (PISO) shift register, used to
In spite of its short block length, designing low- deliver sequentially the decoded message (systematic
complexity soft-decision decoding architectures for bits of the decoder decision) at the decoder output.
the Golay code that are amenable to very high data The three previous blocks are supervised by a
control block. In our design, this task is realized by a VI. CONCLUSION
5-bit counter that generates the required control
signals. Soft-decision decoding of Golay codes has been
As shown in Fig. 6, the soft decoder architecture is investigated and a decoder architecture has been
structured in two pipelined stages: reception and described. The proposed approach relies on a
processing transmission. The first stage sequentially dedicated decoding algorithm which exploits the code
processes the 24 received soft symbols in 24 clock properties to achieve near-ML performance using a
periods. In the second stage, the 24+24 candidate small number of error patterns. The simulation results
codewords are generated, scored and compared in a and the hardware complexity of the prototype
total of 24 clock periods, thanks to parallel demonstrate the practicality and the benefits of the
processing. Finally, the 12 decoded information bits proposed decoding algorithm.
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