ưVIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

FACULTY OF COMPUTER SCIENCE AND ENGINEERING


LAB 3 REPORT
CLASS CC04 – GROUP 7
SUBJECT:

DIGITAL SYSTEM
Instructor: Nguyễn Thiên Ân
Student’s name Student’s ID

Vũ Đức Việt Anh 2352074

Nguyễn Hoài Nam 2352776
Nguyễn Đỗ Khánh Trình 2353237
Phạm Minh Hiếu 2352334
1. Check list :
Before class:
Number To-do Content Check
1. The area of the Lab is clear and empty
2. The KIT was self-test and there are no problems
3. Inputs and outputs work normally
4. Measure the DC Voltage of VCC of KIT = 5V

After class:
Number To-do Content Check
1. All wires are unplugged and sorted
2. All ICs are released before being put out of
breadboard
3. All ICs are sorted and put into their boxes (of
types)
4. Clean up and return the KIT
5. Clean up and return VOM
6. Clean up and return Oscilloscope (if it is used)
7. Clean up the work area
2.3 Exercise:
2.3.1: Design, simulate and implement a D Flip-flop using J-K Flip-flops (allowed to use
other logic gates if necessary)

 we use the K-map to find the boolean expression of J and K in terms of D:

D\Q 0 1

0 0 x

1 1 1

D\Q 0 1

0 x 1

1 x 0

*Notes: From the truth table and K map above, we can conclude that: D = J and
D’ = K
So, to Element a D Flip-flop by a J-K Flip-flop. We just need to make two
inputs of a J-K Flip-flop have different values (High/Low or Low/High) at the
same time in every testing time.
In this situation, the J and K input will have the different value at every time.
So, they will connect to the same switch on Tickit but there will be a NOT gate
before connecting to the K input (SW0 for example).
Following this solution, with each same value of D and K, it will release the
same output. (It means D and K have the same input value).
Design:
J – K Flip-flop that element as a D Flip-flop

BUT1

CLK1

Q’

BUT2

J-K Flip-flop
Truth table:
J-K Flip-Flop

Input Output
Input from Switch
Clock D (SW Q Q’
J K
value)
↑ 1 1 0 1 0
↑ 0 0 1 0 1
↓ or stable 1 1 0 Qo Q’o
↓ or stable 0 0 1 Qo Q’o

Logisim Circuit Design:

U1
5V – U1:4
GND – U1:11
U2:10 – U1:3
SW0 – U1:14
BUT1 – U1:2
CLK1 – U1:1
LED0 – U1:12
LED1 – U1:13

U2

GND – U2:7
5V – U2:14
SW0 – U2:11
U2:10 – U1:3
2.3.2 Design, simulate and implement the following logic circuit.

Design:
 Logisim circuit design:

Netlist:
GND – U1:7
5V – U1:14
CLK1 – U1:3
U1:2 – U1:6 GND – U2: 7
U1:6 – LED0 5V – U2:14
U1:5 – U1:11
U1:9 – U2:3
U1:8 – U1:12 U2:2 – U2:6
U1:8 – LED1 U2:6 – LED2
U1:9 – U2:3 U2:5 – LED3

a. Assume that QA, QB, QC are connected to the LEDs. What is the
phenomenon of the
LEDs? What is the difference among LEDs?
 Answer: The lights 1 2 3 corresponding to QA QB QC change according
to the up counting circuit principle
From 0 to 7, we have changes as follows:

QC QB QA
(LED2) (LED1) (LED0)
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
From the table above, we see that the frequency of LED 1 is 2 times greater than
the frequency of LED 2 and 4 times LED frequency 3.
=> This is a circuit that counts up from 0 to 7.

b. How many minimum D Flip-flops required to build a circuit in which the

output
frequency is 16 times less than the Clock In frequency?
 Answer: Through the above experiment we can see that for every D flip
flop, the output frequency of the last D flip flop will be 2n less (n is the
number of D flip flops used) than the input frequency.
Therefore, to have an output frequency less than 16 times the equivalent of 2 4
input frequencies, at least 4 D flip flops or 2 7474 ICs are needed.
2.3.3 (Advance) Given the circuit and waveform as follows.

a. Design and simulate the circuit in Logisim.

b. Complete the timing diagram for A, B, and z based on the given waveform
PRE’ CLR’ CLK J K Q Q’

0 1 X X X 1 0

1 0 X X X 0 1

1 0 X X X 1 1

1 1 ↓ 0 0 No change

1 1 ↓ 1 0 1 0

1 1 ↓ 0 1 0 1

1 1 ↓ 1 1 Toggle