VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

FACULTY OF COMPUTER SCIENCE AND ENGINEERING

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LAB 4 REPORT
CLASS CC04 – GROUP 7
SUBJECT:

DIGITAL SYSTEM
Instructor: Nguyễn Thiên Ân
Student’s name Student’s ID
Vũ Đức Việt Anh 2352074
Nguyễn Hoài Nam 2352776
Nguyễn Đỗ Khánh Trình 2353237
Phạm Minh Hiếu 2352334
1. Check list :
Before class:
Number To-do Content Check
1. The area of the Lab is clear and empty
2. The KIT was self-test and there are no
problems
3. Inputs and outputs work normally
4. Measure the DC Voltage of VCC of KIT = 5V

After class:
Number To-do Content Check
1. All wires are unplugged and sorted
2. All ICs are released before being put out of
breadboard
3. All ICs are sorted and put into their boxes (of types)
4. Clean up and return the KIT
5. Clean up and return VOM
6. Clean up the work area
2.3 Exercises
2.3.1 Design and simulate a Full Adder built from Half Adders in
Logisim.
Half table:

INPUTS OUTPUTS

A B SUM CARRY

0 0 0 0

1 0 1 0

0 1 1 0

1 1 0 1

Full table:

INPUTS OUTPUTS

Cin A B SUM = A ⊕ B ⊕ Cin COUT = Cin.( A ⊕ B) + A.B

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
From the truth table above, the logic of the full adder can be implemented. We
can observe that the output S (SUM) is the result of an XOR operation between
input CIN (carry-in) and the output SUM of the half adder, combined with input
A and B.

Note: COUT (carry-out) will only be high (1) if at least two inputs among the
three inputs is high. This implies the presence of a carry from the previous
addition.

The circuit diagram of a Half Adder:

The circuit diagram in Logisim evolution:

2.3.2.Design, simulate and implement a 4-bit Ripple Carry Adder
using IC 7483
To implement a stacked N-bit addition, we need N Full Adder
circuits. The IC 7483 integrates 4 Full Adder circuits, so using only 1
IC 7483 is sufficient when implementing a 4-bit Ripple Carry Adder.
Note that the Cout (carry-out) of the Full Adder for the most
significant bit (MSB) will be connected to an LED to represent the
result value exceeding 15.
The logic symbol and pinout of IC 7483:
Simulate IC 7483 by Logisim:

2.3.3. Design, simulate and implement a MOD-10 Asynchronous

UP Counter using J-K Flipflops (IC 7473).
To design an up-counter modulo 10 (counting from 0 to 9 and then back to
0), at least 4 J-K flip-flops connected asynchronously are needed because
the counter requires 4 bits. This implies using 2 IC 7473 edge-triggered
flip-flops. Each IC 7473 has 2 J-K flip-flops corresponding to 2 active-low
CLR (clear) gates. When all CLR gates are activated, the counter will be
reset to 0. The solution idea is that we need to design a logic expression
with inputs being the output bits of the 4 flip-flops and the outputs
connected to the CLR pins of the flip-flops. This is done so that when the
counter reaches 10, the CLR pins are immediately activated, resetting the
counter to 0.
With the foundation above, we have the table of changes in bit values as
follows:

D C B A Z (CLR) Status

0 0 0 0 1 0

0 0 0 1 1 1

0 0 1 0 1 2

0 0 1 1 1 3

0 1 0 0 1 4

0 1 0 1 1 5

0 1 1 0 1 6

0 1 1 1 1 7

1 0 0 0 1 8

1 0 0 1 1 9

1 0 1 0 0 Return to 0

1 0 1 1 x Optional

1 1 0 0 x Optional

1 1 0 1 x Optional

1 1 1 0 x Optional

1 1 1 1 x Optional
Note: QD, QB, QC, QA are the output Q of the corresponding flip-flops
for the D C B A bits (with D being the MSB, and A being the LSB).
Then, we use K-map to simplify the expression:

DC/BA 00 01 11 10

00 1 1 1 1

01 1 1 1 1

11 x=1 x=1 x=0 x=0

10 1 1 X=0 0

After simplification, the logic expression going into the CLR pins is Z =
D’ + B’ = (BD)’.

Circuit diagram design:

Logisim Design

2.3.4. What is the difference between asynchronous and

synchronous counters?
1. Synchronous Counter:
- In synchronous counters, all flip-flops receive clock signals
simultaneously.
- State updates occur at the same time, typically on the rising or
falling edge of the clock signal.
- This simultaneous updating ensures predictability and speed,
avoiding issues related to varying propagation delays.

2. Asynchronous Counter:
- Asynchronous counters, or ripple counters, operate with each
flip-flop being clocked by the output of the previous flip-flop.
- Clock signals ripple through the stages, and each flip-flop is
triggered by the changing output of the previous stage.
 - Asynchronous counters are simpler in design but can be slower
and less predictable due to cumulative propagation delays.

In summary, the key distinction lies in the clock signal application:

- Synchronous: Simultaneous clocking of all flip-flops.
- Asynchronous: Sequential clocking, with the signal rippling through
stages.
The choice depends on factors like speed, complexity, and
synchronization requirements, with synchronous counters being faster
and more predictable in applications where precise timing is crucial.
2.3.5.What is the procedure to design a synchronous counter?

1. Determine Counter Specifications:

- Define specific counter requirements, including the number of bits
(MOD value), counting sequence (binary, Gray code), and additional
features like clear or enable inputs.

2. Choose Flip-Flop Type:

- Select the type of flip-flops (D, JK, T) based on design
requirements and component availability.

3. Create State Diagram:

- Develop a state diagram representing the counting sequence and
transitions between states, with each state corresponding to unique
flip-flop output combinations.
4. Determine Flip-Flop Inputs:
- For each state, determine values to load into flip-flop inputs (D, J,
K, or T) to ensure correct transitions.

5. Implement Next-State Logic:

- Use combinational logic (AND, OR, NOT gates) to create
next-state logic, determining inputs for flip-flops based on the current
state.

6. Create Common Clock Signal:

- Design and incorporate a common clock signal for synchronous
operation, ensuring simultaneous state changes in all flip-flops.

7. Connect Flip-Flops and Next-State Logic:

- Connect flip-flops to the common clock signal and outputs of
next-state logic, ensuring correct loading based on logic output.

8. Add Clear and Enable Inputs (if needed):

- Include clear and enable inputs, if necessary, for counter reset or
temporary counting suspension.

9. Simulate and Test:

- Simulate the counter to validate expected behavior. Test with
various clock frequencies and inputs to ensure accurate counting.
10. Implement the Counter:
- Physically implement the counter using selected flip-flops and
logic gates. Ensure proper connections, clock signal distribution, and
power considerations.

11. Test in Hardware (if applicable):

- Conduct real-world testing if the counter is implemented in
hardware, ensuring functionality aligns with intentions.

12. Debug and Optimize:

- Debug any issues arising during testing and optimize the design as
needed. This may involve logic adjustments or additional feature
incorporation.