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hw3 - Cse490 590 sp2025

The document outlines Homework 3 for CSE 490/590 Computer Architecture, covering various topics such as instruction execution, memory hierarchy, cache performance metrics, and cache policies. It includes problems related to branch prediction, average memory access time, cache hit/miss rates, and comparisons between write-back and write-through cache policies. Additionally, it addresses specific scenarios involving direct-mapped and set associative caches, as well as calculations for miss rates and CPI adjustments.

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hohije3405
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16 views4 pages

hw3 - Cse490 590 sp2025

The document outlines Homework 3 for CSE 490/590 Computer Architecture, covering various topics such as instruction execution, memory hierarchy, cache performance metrics, and cache policies. It includes problems related to branch prediction, average memory access time, cache hit/miss rates, and comparisons between write-back and write-through cache policies. Additionally, it addresses specific scenarios involving direct-mapped and set associative caches, as well as calculations for miss rates and CPI adjustments.

Uploaded by

hohije3405
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CSE 490/590 Computer Architecture Spring 2025 Homework 3 (not graded)

1.
Consider the following list of instructions. Assume that the initial values for $s1, $s2, $s3, $s4, and $s5
are all 0:
loop: ADDI $s2, $s1, -2
BNE $s5, $s2, target1
ADDI $s3, $s3, 0
target1: ADDI $s1, $s1, 1
ADDI $s4, $s1, -3
BNE $s5, $s4, loop

Assume that we have a 1-bit branch predictor that stores the result of the last branch and makes the
prediction based on the result. Show the results of all predictions throughout the execution. (Use T/N to
represent Taken/ Not Taken)

Branch Prediction (T/N) Actual Result (T/N)

1st BNE->target1 N T
CSE 490/590 Computer Architecture Spring 2025 Homework 3 (not graded)

1. Consider the following list of instructions. Assume that the initial values for $s1, $s2, $s3, $s4, and
$s5 are all 0:
loop: ADDI $s2, $s1, -2
BNE $s5, $s2, target1
ADDI $s3, $s3, 0
target1: ADDI $s1, $s1, 1
ADDI $s4, $s1, -3
BNE $s5, $s4, loop
Assume that we have a 1-bit branch predictor that stores the result of the last branch and makes the
prediction based on the result. Show the results of all predictions throughout the execution. (Use T/N
to represent Taken/ Not Taken)

Branch Prediction (T/N) Actual Result (T/N)

1st BNE->target1 N T
CSE 490/590 Computer Architecture Spring 2025 Homework 3 (not graded)

2. Assume the presence of the following memories in a MIPS system:


L1 cache
L2 cache
Main Memory
Hard drive
Show the memory hierarchy and order them in terms of
a. Speed
b. Memory capacity (Size)
c. Cost per byte
3.
a. If a direct mapped cache has a hit rate of 95%, a hit time of 4 ns, and a miss penalty of
100 ns, what is the AMAT?
b. If replacing the cache with a 2-way set associative increases the hit rate to 97%, but
increases the hit time to 5 ns, what is the new AMAT?
c. If an L2 cache is added with a hit time of 20 ns and a hit rate of 50%, what is the new
AMAT?

4. Suppose that in 1000 memory references there are 40 misses in the first-level cache and 20
misses in the second-level cache.
a. What are the local and global miss rates for each level of cache?
Assume the miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of
the L2 cache is 10 clock cycles, the hit time of the L1 cache is 1 clock cycle, and there are
1.5 memory references per instruction.
b. What is the average memory access time?

5.
a. What is write back cache? Discuss both the advantages and disadvantages of using the
write-back policy.
b. What is write through cache? Discuss both the advantages and disadvantages of using the
write-through policy.

6. Here is a series of address references given as word addresses: 2, 3, 11, 16, 21, 13, 64, 48, 19,
11, 3, 22, 4, 27, 6 and 11. Consider a word-addressable cache.
Assuming a Direct-mapped cache with 16 one-word blocks that is initially empty, label each
reference in the list as a hit or a miss.
a. For each of these references, identify the binary address, the tag, and the index.
b. What is the hit rate?
7. A processor with Instruction cache miss rate of 2% and Data cache miss rate of 4% and costs
10 cycles to access either of the caches. 40% of the instructions to be executed are Load and
Store Instruction. The CPI with ideal cache (no misses) is 2.
CSE 490/590 Computer Architecture Spring 2025 Homework 3 (not graded)

a. Compute the actual CPI


b. Consider the datapath was improved so that the CPI can be reduced from 2 to 1.5 (all the
other specs remain the same). Compute the actual CPI and compare it with (a)

8. Consider a direct-mapped cache of 128 blocks and each block can hold 16 words. The total
memory capacity is 8 GByte with 8Byte word sizes. It is a word addressable memory.

a. What is the address format?


b. If we change the cache to a 4-way set associative cache, what is the new address format?

9. a) Consider a main memory size of 4 Bytes. Each block in the cache can hold only 1 word
(here 1 word = 1 Byte). Find the miss rate for the address references 0 4 0 4 0 4 0 4 in a
direct mapped cache.
b) Consider a main memory size of 4 Bytes. Consider a 2 way set associative cache which
are initially empty. Each block in the cache can hold only 1 word (here 1 word = 1 Byte).
Find the miss rate for the same address references (0 4 0 4 0 4 0 4).
c) Compare (a) and (b) and list the advantages of associative cache.

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