COMPUTER LABORATORY MANUAL

Computer Architecture and Logic Design

(EE – 122)
Spring 2023

DEPARTMENT OF COMPUTER SOFTWARE ENGINEERING

Military College of Signals
National University of Sciences and Technology
www.mcs.nust.edu.pk

Computer Architecture Logic Design Lab Manual 1

 PREFACE
This lab manual has been prepared to facilitate the students of software engineering in studying insight
into working of computer systems. The obvious objective of studying computer architecture is to learn
how to design one. Writing machine dependent software such as compilers, operating systems, and device
drivers, need knowledge of possible structural and functional organization of computer architectures. A
software engineer or scientific programmer interested in high performance studies computer architecture
to learn how to design programs to gain maximum performance from a given architecture. Working with
systems that involve a variety of interfaces, equipment and communication facilities require knowledge of
computer organization.
PREPARED BY
Lab manual is prepared by Lecturer Rabia Khan and Demonstrator Kabeer Ahmed, updated by Mehreen
Ahmed under the supervision of Head of Department Dr. Adil Masood Siddiqi in year 2016.
GENERAL INSTRUCTIONS
a. Students are required to maintain the lab manual with them till the end of the semester.
b. All readings, answers to questions and illustrations must be solved on the place provided. If more space
is required then additional sheets may be attached. You may add screen print to the report by using the
‘Print Screen’ command on your keyboard to get a snapshot of the displayed output.
c. It is the responsibility of the student to have the manual graded before deadlines as given by the
instructor
d. Loss of manual will result in re submission of the complete manual.
e. Students are required to go through the experiment before coming to the lab session. Lab session details
will be given in training schedule.
f. Students must bring the manual in each lab.
g. Keep the manual neat clean and presentable.
h. Plagiarism is strictly forbidden. No credit will be given if a lab session is plagiarised and no re
submission will be entertained.
i. Marks will be deducted for late submission.
j. In the exercises, you have to put the output in your Lab report.
k. Name your reports using the following convention:
Lab#_Rank_YourFullName
(1) ‘#’ replaces the lab number.
(2) ‘Rank’ replaces Maj/Capt/TC/NC/PC
(3) ‘YourFullName’ replaces your complete name.
l. You need to submit the report even if you have demonstrated the exercises to the lab engineer/instructor
or shown them the lab report during the lab session.
VERSION HISTORY
Date Update By Details
July 2013 Lec Ayesha Naseer First Version Created
Sep 2014 Lec Ayesha Naseer Second version created. Labs improved
Sep 2015 Kabeer Ahmed Labs improved &Updated exercises
Sep 2016 Kabeer Ahmed Labs improved &Updated exercises
Sept 2017 A/P Mobeena Shahzad/LE Marium Labs added &Updated exercises
June 2019 A/P Mobeena Shahzad/LE Marium Labs Added. Updated Rubrics
Feb 2020 A/P Mobeena Shahzad/LE Marium Updated CLOs
Feb 2022 A/P Mobeena Shahzad/LE Laraib Labs improved & Updated Rubrics
Feb 2023 Dr Yawar Abbas/Dr. Kabeer Ahmed Re-designed a combined lab manual (COA and DLD)

Computer Architecture Logic Design Lab Manual 2

 Department of Computer Software Engineering
Lab Rubrics
Group 32: Programming Tasks
Criteria Unacceptable Substandard Adequate Proficient
(Marks=0) Marks=1 Marks=2 Marks=3

The program execution let to

R1 inaccurate or incomplete results. The program was correctly The program was correctly
The program failed to produce
Completeness It was not correctly functional or functional and most of the functional, and all the features
the right accurate result
And Accuracy not all the features were features were implemented were implemented
implemented

Student successfully figures

The student fails to figure out Student successfully figures out
R2 out most of syntax and Student successfully figures out all
the syntax and semantic few of syntax and semantic
Syntax and semantic errors of the syntax and semantic errors of the
errors of the incorrect errors of the program with
Semantics program with minimum program without any guidance
program extensive guidance
guidance
Student has demonstrated on
Student has basic knowledge
Student failed to demonstrate Student has basic understanding, accurate understanding of the lab
R3 of understanding. Provides
a clear understanding of the but asked questions were not objective and concepts. All the
Demonstration fundamental answers to
assigned task answered. questions are answered
asked questions
completely and correctly

R4 The code is readable only by

The code is poorly organized The code is fairly easy to The code is exceptionally well
Complexity and someone who knows what it is
and very difficult to read read organized and very easy to follow
Readability supposed be doing

Complete working program is

R5 copied indicating no effort on Most of working program is Most of working program is
Complete working program is
Perseverance student’s part resulting in a copied. Minor contribution by contributed by the student.
contributed by the student
and plagiarism total score of zero for all the student Minor copied components
rubrics

Computer Architecture Logic Design Lab Manual 3

 Department of Computer Software Engineering
Lab Rubrics
G-29 Digital Logic and Design

Criteria Unacceptable Substandard Adequate Proficient

(Marks=0) Marks=1 Marks=2 Marks=3

R1 Shows little Demonstrates Demonstrates commitment

Actively helps to identify group goals
Contribution/Group commitment to group commitment to group to group goals and carries
and works effectively to meet them
Participation goals and fails to goals, but has difficulty out assigned roles
in all roles assumed
perform assigned roles performing assigned roles effectively

R2
Thoroughly and accurately identifies
Does not demonstrate Identifies some Accurately identifies most
all components involved,
Able to Identify the an understanding of the components but lacks components but may miss
demonstrating a deep
Components components involved. accuracy or completeness. some minor elements.
understanding of the task.

R3
Unable to deduce the Produces a partially Deduces a correct logic Consistently deduces optimized logic
Able To Deduce The logic diagram or correct logic diagram but diagram for most inputs but diagrams for any input,
Optimized Logic Diagram produces an incorrect fails to optimize it may overlook optimization demonstrating a high level of
For Any Input diagram. effectively. opportunities. understanding and efficiency.

R4
Partially implements or Implements and Implements and demonstrates the
Unable to implement or
demonstrates the task demonstrates the task task flawlessly, showcasing thorough
Able To Implement And demonstrate the task
with significant errors or adequately, but with minor understanding and proficiency in
Demonstrate The Task effectively.
omissions. errors or inefficiencies. execution.

Computer Architecture Logic Design Lab Manual 4

 The student has basic The student has demonstrated on
R5 The student failed to The student has moderate
knowledge of accurate understanding of the lab
demonstrate a clear knowledge of
understanding but asked objective and concepts. All the
Presentation Skills understanding of the understanding. Answer to
questions were not questions are answered completely
assigned task the question are basic
answered. and correctly

Group 4: DLD, Applied Physics, BEE and Digital Electronics

Criteria Unacceptable Substandard Adequate Proficient
(Marks=0) Marks=1 Marks=2 Marks=3

The system execution let to

R1 The system was correctly
The system failed to inaccurate or incomplete results. The system was correctly functional,
Completeness and functional and most of the
produce the right It was not correctly functional or and all the features were
Accuracy features were
accurate result not all the features were implemented
implemented
implemented

The student has demonstrated on

R2 The student failed to The student has moderate
The student has basic knowledge accurate understanding of the lab
demonstrate a clear knowledge of
of understanding but asked objective and concepts. All the
Demonstration understanding of the understanding. Answer to
questions were not answered. questions are answered completely
assigned task the question are basic
and correctly

R3
Inappropriate Correct measurement
Measurement/ Partly correct measurement Competent measurement
measurement techniques are
techniques are demonstrated, techniques are demonstrated, with
Techniques/ Data techniques are demonstrated, with partly
with partly valid data valid and accurate data
Validation demonstrated valid data

R4
Shows little commitment Demonstrates
Demonstrates commitment to Actively helps to identify group goals
to group goals and fails commitment to group
Contribution/ group goals, but has difficulty and works effectively to meet them
to perform assigned goals and carries out
Group participation performing assigned roles in all roles assumed
roles assigned roles effectively

Computer Architecture Logic Design Lab Manual 5

 R5 Inappropriate
Good troubleshooting
troubleshooting Acceptable troubleshooting Excellent troubleshooting
techniques are
Troubleshooting techniques are techniques are demonstrated techniques are demonstrated
demonstrated
demonstrated

Computer Architecture Logic Design Lab Manual 6

 Department of Computer Software Engineering
Lab Rubrics
Group 4A: OPEN ENDED LAB (Computer Architecture and Logic Design)

Criteria Deficient Fair Good Excellent

(Marks=0) (Marks=1) (Marks=2) (Marks=3)
Hypothesis is clearly stated, specific, and
Hypothesis
No hypothesis is Hypothesis is vague or not Hypothesis is stated but lacks testable, showing a clear understanding of the
Formulation
formulated. clearly stated. clarity or specificity. relationship between cache size and computer
Clo 3 c-4
system performance.
Experimental plan is
Experimental plan is partially Experimental plan is well-defined, including
Experimental incomplete or lacks key
No experimental complete, but some appropriate benchmarks, a wide range of
Design components, such as
plan is provided. components are not clearly cache sizes, and enough trials to ensure
Clo 4 p-3 benchmarks, cache size range,
defined or lack detail. reliability.
or number of trials.
Experiment is partially Experiment is properly conducted with
Experiment Experiment is conducted but
No experiment is conducted with some consistent execution and control measures in
Execution lacks proper execution or
conducted. inconsistencies in execution place.
Clo 4 p-3 control.
or control.
Data collection is thorough, accurate, and
Data collection is partially
Data Collection properly analyzed, with appropriate statistical
No data is collected Data collection is incomplete complete and analyzed, but
and Analysis methods used to draw conclusions about the
or analyzed. or lacks accuracy. with inconsistencies or
Clo 4 p-3 effect of cache size on computer system
inaccuracies.
performance.
Report is well-structured, complete, and
No report is . Report is partially complete
Report and Report is incomplete or lacks includes clear findings and conclusions
provided, or lacks with some components
Conclusions clarity in findings or supported by the data, demonstrating a
required missing or lacking clarity in
Clo 3 c-4 conclusions. thorough understanding of the effect of cache
components. findings or conclusions.
size on computer system performance

Computer Architecture Logic Design Lab Manual 7

 Mapping of CLOs to Program Learning Outcomes
PLOs/CLOs CLO1 CLO2 CLO3 CLO4
PLO 1 (Engineering Knowledge) √
PLO 2 (Problem Analysis)
PLO 3 (Design/Development of Solutions) √
PLO 4 (Investigation) √
PLO 5 (Modern tool usage) √
PLO 6 (The Engineer and Society)
PLO 7 (Environment and Sustainability)
PLO 8 (Ethics)
PLO 9 (Individual and Team Work)
PLO 10 (Communication)
PLO 11 (Project Management)
PLO 12 (Lifelong Learning)

Computer Architecture Logic Design Lab Manual 8

 Lab Experiments CLO Mapping
S No List of Experiments CLO R-G
1 DIGITAL LOGIC GATES 4 4
2 BOOLEAN ALGEBRA 4 4
3 USING NOR/NAND ICS 4 4
4 USING KARNAUGH MAP 4 4
5 DESIGN OF ADDER AND SUBTRACTOR 4 4
6 ENCODER AND DECODER 4 4
7 INTRODUCTION TO EMU8086 AND REGISTERS 4 1
8 INPUT/ OUTPUT SINGLE AND MULTI-DIGIT NUMBER 4 1
9 ARITHMETIC INSTRUCTIONS 4 1
10 EXPLORING FLAG REGISTER 4 1
11 BOOLEAN OPERATORS 4 1
12 PROCEDURES IN ASSEMBLY 4 1
13 OPEN ENDED LAB - OEL
14 DECISION INSTRUCTIONS 4 1
15 IMPLEMENTATION OF LOOP STRUCTURES 4 1
16 LAB EXAM/ PROJECT - 1

Computer Architecture Logic Design Lab Manual 9

 List of Experiments
EXPERIMENT 1 – DIGITAL LOGIC GATES..........................................................................................10
EXPERIMENT 2 – BOOLEAN ALGEBRA..............................................................................................14
EXPERIMENT 3 – USING NOR/NAND ICS............................................................................................22
EXPERIMENT 4 – USING KARNAUGH MAP.......................................................................................26
EXPERIMENT 5 - DESIGN OF ADDER AND SUBTRACTOR.............................................................29
EXPERIMENT 6 - ENCODER AND DECODER.....................................................................................36
EXPERIMENT 7 – INTRODUCTION TO EMU8086 and REGISTERS..................................................43
EXPERIMENT 8 –INPUT/ OUTPUT SINGLE AND MULTI-DIGIT NUMBER....................................46
EXPERIMENT 9 – ARITHMETIC INSTRUCTIONS...............................................................................51
EXPERIMENT 10 – EXPLORING FLAG REGISTER.............................................................................56
EXPERIMENT 11: BOOLEAN OPERATORS..........................................................................................61
EXPERIMENT 12: PROCEDURES IN ASSEMBLY................................................................................64
EXPERIMENT 13: OPEN ENDED LAB...................................................................................................67
EXPERIMENT 14 – DECISION INSTRUCTIONS...................................................................................69
EXPERIMENT 15 – IMPLEMENTATION OF LOOP STRUCTURES...................................................73

Computer Architecture Logic Design Lab Manual 10

 MARKS
Student Name: _____________ Course: ________

Subject: Computer Architecture and Logic Design (CALD)

Sr Total Obt. Instructor

Marks Obtained
No Date Experiment Marks Marks Sign
R1 R2 R3 R4 R5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Grand Total

Computer Architecture Logic Design Lab Manual 11

 EXPERIMENT 1 – DIGITAL LOGIC GATES
Objective
 To study the basic logic gates: AND, OR, INVERT, NAND, and NOR.
 To study the representation of these functions by truth tables, logic diagrams and Boolean
algebra.
 To observe the pulse response of logic gates.

Time Required : 3 hrs

Programming Language : NIL
Software Required : Circuit Maker 2000
Hardware Required : Heath Kit Digital Trainer
IC Type 7400 Quadruple 2-input NAND gates
IC Type 7402 Quadruple 2-input NOR gates
IC Type 7404 Hex Inverters
IC Type 7408 Quadruple 2-input AND gates
IC Type 7432 Quadruple 2-input OR gates
INTRODUCTION

‘Anything that make sense is called logic’. Circuit that takes the logical
decision and the process are called logic gates. Each gate has one or more
input and only one output. Digital circuits have two discrete voltage levels to
represent the binary digits (bits) 1 and 0. All digital circuits are switching
circuits. Instead of mechanical switches, they use high-speed transistors to
represent either an ON condition or an OFF condition. Various types of logic,
representing different technologies, are available to the logic designer. The
choice of a particular family is determined by factors such as speed, cost,
availability, noise immunity, and so forth. The key requirement within each
family is compatibility; that is, there must be consistency within the logic
levels and power supplies of various integrated circuits made by different
manufacturers. The experiments in this lab book use primarily transistor-
transistor logic, or TTL. The detailed performance characteristics of TTL
depend on the particular subfamily. However, all TTL is designed to operate
from a 5 V power supply, and the logic levels are the same for all TTL
integrated circuits.

Important Logic Gates

AND GATE

The AND gate performs a logical multiplication commonly known as AND

function. The output is high when both the inputs are high. The output is low
level when any one of the inputs is low.

OR GATE

Computer Architecture Logic Design Lab Manual 12

The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level
when both the inputs are low.

NOT GATE (Inverter)

The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

IN LAB

PROCEDURE

 Connections are given as per circuit diagram.

 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

AND Gate:

SYMBOL:
PIN DIAGRAM:

Computer Architecture Logic Design Lab Manual 13

OR Gate:

NOT Gate:

SYMBOL PIN
DIAGRAM

Computer Architecture Logic Design Lab Manual 14

POST LAB

Review Question

Verify all the gates

Using given Resources, Implement NAND and NOR functionality.
Implement the function F= X’Y’Z + X’YZ + XY’ using gates.
Show Experimentally that
 X + XY = X
 X(X +Y) =X By duality
Verify it using gates

Show truth table of both these parts

If more than two input AND & OR gates are available, how will you connect its inputs so that they work
as 2 input gates? Perform it for 3 and 4 input AND & OR gates.

Practice given circuit and draw a truth table for each circuit. Construct boolean expressions for
all outputs.

Computer Architecture Logic Design Lab Manual 15

Construct a circuit of the following expressions and draw the truth table:

F1=ABC

F2=A+B+C

Web Resources
https://www.techtarget.com/whatis/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-
XNOR#:~:text=There%20are%20seven%20basic%20logic,NAND%2C%20NOR%2C%20and%20XNOR.
http://www.uop.edu.pk/ocontents/Lec-10-universal%20gates.pdf

Videos Resources
https://www.youtube.com/watch?v=La9Nk6iwHvU
https://www.youtube.com/watch?v=-MqHBjJpAiE

Computer Architecture Logic Design Lab Manual 16

 EXPERIMENT 2 – BOOLEAN ALGEBRA
Objective
 To verify the rules and regulations of Boolean Algebra
 To simplify and modify Boolean logic functions by means of Demorgan’s theorem.
 To design and implement a logic circuit

Time Required : 3 hrs

Programming Language : NIL
Software Required : Circuit Maker 2000
Hardware Required : Heath Kit Digital Trainer
7400 Quadruple 2 input NAND gates.
7402 Quadruple 2 input NOR gates
7408 Quadruple 2 input AND gates
7432 Quadruple 2 input OR gates
7404 Hex inverters
7411 Triple 3-input AND gate

INTRODUCTION

PRE-LAB

De Morgan Theorems:

 (X + Y) ’ = X’. Y’ ……………… (a)

 (X.Y)’ = X’ + Y’ ……………… (b)

Other Important Theorems

Distributive

 Distributed over Multiplication X(Y + Z) = XY + XZ

 Distributed over Addition X + (Y.Z) = (X + Y). (X+Z)

Associative

 Addition X + (Y+Z) = (X+Y) + Z

 Multiplication X(YZ) = (XY)Z

Computer Architecture Logic Design Lab Manual 17

Laws of Boolean Algebra
There are six types of Boolean algebra laws. They are:
● Commutative law
● Associative law
● Distributive law
● AND law
● OR law
● Inversion law

Those six laws are explained in detail here.

Commutative Law
Any binary operation which satisfies the following expression is referred to as a
commutative operation. Commutative law states that changing the sequence of
the variables does not have any effect on the output of a logic circuit.
● A. B = B. A
● A+B=B+A

Associative Law
It states that the order in which the logic operations are performed is irrelevant as
their effect is the same.
● ( A. B ). C = A . ( B . C )
● ( A + B ) + C = A + ( B + C)

Distributive Law
Distributive law states the following conditions:
● A. ( B + C) = (A. B) + (A. C)
● A + (B. C) = (A + B) . ( A + C)

AND Law

These laws use the AND operation. Therefore, they are called AND laws.
● A .0 = 0
● A.1=A

Computer Architecture Logic Design Lab Manual 18

 ● A. A = A
●

OR Law
These laws use the OR operation. Therefore, they are called OR laws.
● A +0=A
● A+1=1
● A+A=A
●

Inversion Law
This law uses the NOT operation. The inversion law states that double inversion of
a variable results in the original variable itself.
●

Universal Gates:

NAND and NOR gates are called universal Gates because they can be used in
combination to perform the function of other basic logic gates and
implement any Boolean function. NAND gates is also called NOT – AND and
NOR gate is called NOT – OR gate. Pin diagram of both gates is given below.

Computer Architecture Logic Design Lab Manual 19

NOR gate as AND gate:

NAND gate as OR gate:

Computer Architecture Logic Design Lab Manual 20

 Exclusive Or Gate Using NAND and NOR gate:

XOR gate using NOR gate, Q = AB’ + BA’

XOR gate using NAND gate, Q = AB’ + BA’

Computer Architecture Logic Design Lab Manual 21

 Exclusive NOR gate using NAND and NOR gates:

XNOR gate using NOR gates, Z = AB + A’B’

XNOR Gate using NAND gates, output = AB + A’B’

1. A+0 = A

2. A+1 = 1

3. A .0 = 0

4. A .1 = A

5. A+A = A

6. A+A’ = 1

7. A.A = A

8. A.A’ = 0

9. (A’)’ = A

10. A+AB = A

Computer Architecture Logic Design Lab Manual 22

11. A+A’B = A+B

12. (A+B)(A+C) = A+BC

13. A’. B’ = (A+B)’

14. A’+B’ = (A.B)’

IN LAB

Procedure:

1. Mount 7404, 7432 and 7408 0n the trainer kit

2. Connect 5v Vcc and Ground terminal from the kit to all the IC’s
3. Take 2 wires and connect them to 2 Dip Switches on the trainer named
X and Y
4. Connect both these inputs to OR gate and connect the output to
inverter as input.
5. Connect the final output of inverter to LED and you can verify the
Theorem A.
6. Use similar procedure to verify theorem B

Procedure A:
a. Prove OR Law . (A+0=A)
The procedure is:
Connect terminal 2 with the ground and terminal 1 with the switch.

Fig.1 Verifying OR Law

Observations:
The circuit will give high output if the input at terminal 1 is high and vice versa

b. Connect the circuit of Fig.2. Which rule does this circuit illustrate? (A.A=A)

Computer Architecture Logic Design Lab Manual 23

 Fig.2

c. Design a circuit that illustrates rule 10.( A+AB = A) Use clock for A and one of the logic
switches for B. Also draw the logic diagram and its truth table.

OBSERVATION:
The output should be high if and only if A is high

d. Rule 6 illustrates that A+A’ could be replaced with a wire to Vcc. What does rule 8 illustrate?
A.A’ = 0

e. Rule 11 states that A+A’B = A+B.

Prove that these two circuits perform equivalent logic. (Connect two circuits and show that their
outputs are the same).

EXERCISE
Review Questions:

 Verify all these gates and theorems one by one and state their inputs / outputs and truth table.
 Mathematically prove the implementations by using the above given theorem
 XOR gate using NAND and NOR
 XNOR using NAND and NOR
 Implement the following using NAND and NOR IC’s

F = AB + BC + AC, show its truth table as well

Construct and show that the following two circuits give the same outputs for all combinations
of A, B

Web Resources

Computer Architecture Logic Design Lab Manual 24

https://www.techtarget.com/whatis/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-
XNOR#:~:text=There%20are%20seven%20basic%20logic,NAND%2C%20NOR%2C%20and%20XNOR.
http://www.uop.edu.pk/ocontents/Lec-10-universal%20gates.pdf

Videos Resources
https://www.youtube.com/watch?v=La9Nk6iwHvU
https://www.youtube.com/watch?v=-MqHBjJpAiE

Computer Architecture Logic Design Lab Manual 25

 EXPERIMENT 3 – USING NOR/NAND ICS
Objective
 To make AND ,OR,NOT and NAND using NOR IC

Time Required : 3 hrs

Programming Language : NIL
Software Required : Circuit Maker 2000
Hardware Required : Heath Kit Digital Trainer
4001 NOR IC
Connecting wires

INTRODUCTION

1. AND GATE:
We know that AND gate is represented by:
F=A.B
Taking double complement of both sides
(F’)’=[(A.B)’]’
Applying Demorgan’s Law
F= (A’+B’)’

Implement the circuit and verify the truth table of AND gate
2. OR GATE :
We know that OR gate is represented by
F=A+B

Taking double compliment on both sides

(F’)’=[(A+B)’]’
This expression is equivalent to the OR gate

Computer Architecture Logic Design Lab Manual 26

Implement the circuit as shown in the logic diagram and also verify the truth table
3. NOT GATE:
A NOT gate is represented by
F=A’
We know that
(A+A)’=A’
And the left side of the expression shows that it is a NOR gate whose both input terminals are
connected together

Implement the circuit as shown in the diagram , also verify the truth table of the NOT gate
4. NAND:
Expression for NAND gate is:
F=(A.B)’
Taking double complement of both sides
(F’)’=[((A.B)’)’]’
Applying demorgan’s law
F=[(A’+B’)’]’
This is the expression of NAND gate in terms of NOR

EXCLUSIVE OR

Implement the circuit as shown in the diagram also verify its truth table

EXOR:

Computer Architecture Logic Design Lab Manual 27

An XOR gate is made by connecting the output of 3 NOR gates (connected as an AND gate) and
the output of a NOR gate to the respective inputs of a NOR gate. This expresses the logical
fomula (A AND B) NOR (A NOR B). This construction entails a propagation delay three times
that of a single NOR gate.

XNOR

An XNOR gate can be constructed from four NOR gates implementing the expression "(A NOR
N) NOR (B NOR N) where N = A NOR B".This construction has a propagation delay three
times that of a single NOR gate, and uses more gates.

XNOR Construction

REVIEW

NOR gate is a universal gate as it can be used to implement any other gate. So a combinational
circuit can be implemented with only NOR ICs.

Web Resources
https://www.techtarget.com/whatis/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-
XNOR#:~:text=There%20are%20seven%20basic%20logic,NAND%2C%20NOR%2C%20and%20XNOR.
http://www.uop.edu.pk/ocontents/Lec-10-universal%20gates.pdf

Videos Resources
https://www.youtube.com/watch?v=La9Nk6iwHvU
https://www.youtube.com/watch?v=-MqHBjJpAiE

Computer Architecture Logic Design Lab Manual 28

 EXERCISES
Exercise: 5.1 [7]

Construct AND,OR,NOT,NOR,EXOR.EXNOR logical gates using NAND and draw truth tables.

Exercise: 5.2 [8]

Construct circuit diagram of the following expression using only NAND logical gates using NOR
IC and draw truth tables.

F=AC+BC+AD+BD

Computer Architecture Logic Design Lab Manual 29

 EXPERIMENT 4 – USING KARNAUGH MAP
Objective
Design of multiplexer to implement any given boolean function

Time Required : 3 hrs

Programming Language : NIL
Software Required : Circuit Maker 2000
Hardware Required : Heath Kit Digital Trainer
74151 8x1 MUX

INTRODUCTION

Any logic Function can be minimized to a minimum number of literals and terms. It is efficient
to utilize the limited resources to have the functionality. One method of function minimization is
to use the Boolean theorems and identities as discussed in lab 1 and 2.

Karnaugh map or K-map is a map of a function used in a technique used for minimization or
simplification of a Boolean expression. It results in less number of logic gates and inputs to be
used during the fabrication.

Booleans expression can be simplified using Boolean algebraic theorems but there are no
specific rules to make the most simplified expression. However, K-map can easily minimize the
terms of a Boolean function.

K-map is basically a diagram made up of squares. Each of these squares represents a min-term of
the variables. If n = number of variables then the number of squares in its K-map will be 2n. K-
map is made using the truth table.
Rules:

1. No zeros allowed.
2. No diagonals.
3. Only power of 2 number of cells in each group.
4. Groups should be as large as possible.
5. Every one must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.

Computer Architecture Logic Design Lab Manual 30

In Lab:

1. Simplify the following two Boolean functions by means of Karnaugh maps.

F1(A,B) = ∑ m(1 , 2 , 3)
F2 (A, B, C, D) = Σm (0,1,4,5,8,9,10,12,13)
F3 (A, B, C, D)= Σm (3,5,7,8,10,11,13,15)

2. Draw the logic diagrams for outputs F1 and F2 in terms of the inputs A, B, C, and D.
3. Implement and draw the two functions F1 and F2 together by using minimum number of
NAND gates.
4. Connect the circuit and verify it’s operation by preparing a truth table for F1 and F2.

Boolean Functions

1. Derive a truth table for the following Boolean Functions.

F=A’D+B’D+BC+AB’D

2. Draw a Karnaugh map.

3. Combine all the 1’s to obtain the simplified function for F.

4. Combine all the 0’s to obtain the simplified function for F’.

5. Implement both F and F’ using NAND gates and connect two circuits to the same input
switches but to separate output LED’s. Prove that both circuits are complement of each other and
verify the operation of the circuit.

Web Resources
https://www.techtarget.com/whatis/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-
XNOR#:~:text=There%20are%20seven%20basic%20logic,NAND%2C%20NOR%2C%20and%20XNOR.
http://www.uop.edu.pk/ocontents/Lec-10-universal%20gates.pdf

Videos Resources
https://www.youtube.com/watch?v=La9Nk6iwHvU
https://www.youtube.com/watch?v=-MqHBjJpAiE

Computer Architecture Logic Design Lab Manual 31

 EXERCISES

Exercise 4.1:
[15]
1. Construct a truth table for the following Boolean Functions.

F=A’C+A’D+ABC+B’D

2. Draw a Karnaugh map.

3. Combine all the 1’s to obtain the simplified function for F.

4. Combine all the 0’s to obtain the simplified function for F’.

5. Construct both F and F’ using NAND gates and connect two circuits to the same input
switches but to separate output LED’s. Show that both circuits are complement of each other and
verify the operation of the circuit.

Computer Architecture Logic Design Lab Manual 32

 EXPERIMENT 5 - DESIGN OF ADDER AND SUBTRACTOR

OBJECTIVES

 To Design and construct half adder , full adder , half subtractor , full subtractor
 Deduce their logic functions using K-MAPS
 Verify their truth tables using logic gates

COMPONENTS REQUIRED

 Heath Kit Digital Trainer

 7404 hex inverter
 7432 quad two input OR gate
 7408 quad two input AND gate
 7486 quad two input X-OR gate

PRE LAB
INTRODUCTION

Half Adder
 A combinational logic circuit that performs the addition of two single bits is
called Half Adder.
 It is an arithmetic combinational logic circuit designed using XOR & AND
gates to perform addition of two single bits.
 It contains two inputs and produces two outputs.
 Added bits and Outputs are called Sum and Carry, respectively.

Computer Architecture Logic Design Lab Manual 33

FULL ADDER

 Adding of Carry is not possible in Half adder.

 To overcome the above limitation faced with Half adders, Full Adders are
implemented using XOR, AND & OR gates.
 It is an arithmetic combinational logic circuit that performs addition of three
single bits.
 It contains three inputs (A, B, C in) and produces two outputs (Sum and C out).
 Where, Cin -> Carry In and Cout -> Carry Out

HALF SUBTRACTOR

The half subtractor is constructed using XOR and AND Gate. The half subtractor has two input
and two outputs. The outputs are difference and borrow. The difference can be applied using
XOR Gate, borrow output can be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR

The full subtractor is a combination of XOR, AND, OR, NOT Gates. In a full subtractor the logic
circuit should have three inputs and two outputs. The two half subtractor put together gives a
full subtractor .The first half subtractor will be C and A B. The output will be difference output
of full subtractor. The expression AB assembles the borrow output of the half subtractor and
the second term is the inverted difference output of first XOR.

Computer Architecture Logic Design Lab Manual 34

7486 XOR Pin Diagram

IN LAB
LOGIC DIAGRAM

HALF ADDER

TRUTH TABLE

FULL ADDER

FULL ADDER USING TWO HALF ADDER

Computer Architecture Logic Design Lab Manual 35

TRUTH TABLE

HALF SUBTRACTOR

TRUTH TABLE

Computer Architecture Logic Design Lab Manual 36

FULL SUBTRACTOR

Borrow = A’B + A’C + BC

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

Computer Architecture Logic Design Lab Manual 37

Borrow = A’B + A’C + BC

Applications:
1. For performing arithmetic calculations in electronic calculators and other
digital devices.
2. In Timers and Program Counters.
3. Useful in Digital Signal Processing.

POST LAB

Review Questions

 Mathematically prove all the above equations (output equations of half ,full
adder and subtractor ) deduced from their truth table using K-MAP and Boolean
Simplification

Computer Architecture Logic Design Lab Manual 38

  Implement all the circuits on breadboard according to given connections and
verify the truth table.
 Design the truth table and show the circuit diagram of a 4 bit full adder.

Computer Architecture Logic Design Lab Manual 39

 EXPERIMENT 6 - ENCODER AND DECODER

OBJECTIVES

 Design and construct encoder and decoder

 Verify their truth tables using logic gates

COMPONENTS REQUIRED

 Heath Kit Digital Trainer

 Two 7410, 3 I/P NAND gate
 Three 7432, 2 I/P OR gate
 7404 hex inverter

PRE LAB
INTRODUCTION

Binary code of N digits can be used to store 2 N distinct elements of coded information. This is
what encoders and decoders are used for. Encoders convert 2N lines of input into a code of N
bits and Decoders decode the N bits into 2N lines.

ENCODER:

An encoder is a combinational circuit that converts binary information in the form of a 2 N input
lines into N output lines, which represent N bit code for the input. For simple encoders, it is
assumed that only one input line is active at a time.

As an example, let’s consider

Octal to Binary encoder. As shown in the

following figure, an octal-to-binary encoder
takes 8 input lines and generates 3 output lines.

Computer Architecture Logic Design Lab Manual 40

Limitations:
One limitation of this encoder is that only one input can be active at any given time. If more
than one inputs are active, then the output is undefined. For example, if D6 and D3 are both
active, then, our output would be 111 which is the output for D7. To overcome this, we use
Priority Encoders.

Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000 which actually
is the output for D0 active. In order to avoid this, an extra bit can be added to the output, called
the valid bit which is 0 when all inputs are 0 and 1 otherwise.

Priority Encoder:

A priority encoder is an encoder circuit in which inputs are given priorities. When more than
one inputs are active at the same time, the input with higher priority takes precedence and the
output corresponding to that is generated.

Let us consider the 4 to 2 priority encoder as an example.

From the truth table, we see that when all inputs are 0,
our V bit or the valid bit is zero and outputs are not used.
The x’s in the table show the don’t care condition, i.e, it
may either be 0 or 1. Here, D3 has highest priority,
therefore, whatever be the other inputs, when D3 is high,
output has to be 11. And D0 has the lowest priority,
therefore the output would be 00 only when D0 is high
and the other input lines are low.

Similarly, D2 has higher priority over D1 and D0 but lower

than D3 therefore the output would be 010 only when
D2 is high and D3 are low (D0 & D1 are don’t care).

Computer Architecture Logic Design Lab Manual 41

Implementation –
It can clearly be seen that the condition for valid bit to be 1 is that at least any one of the inputs
should be high. Hence,

V = D0 + D1 + D2 + D3
The circuit diagram of 4 to 2 priority encoder is shown in the following
figure.

The above circuit diagram contains two 2-input OR gates, one 4-input OR
gate, one 2input AND gate & an inverter. Here AND gate & inverter
combination are used for producing a valid code at the outputs, even when
multiple inputs are equal to ‘1’ at the same time. Hence, this circuit encodes
the four inputs with two bits based on the priority assigned to each input.

Computer Architecture Logic Design Lab Manual 42

IN LAB
LOGIC DIAGRAM FOR ENCODER

TRUTH TABLE

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0

0 1 0 0 0 0 0

0 0 1 0 0 0 0

0 0 0 1 0 0 0

0 0 0 0 1 0 0

Computer Architecture Logic Design Lab Manual 43

 0 0 0 0 0 1 0

0 0 0 0 0 0 1

DECODER:

A decoder does the opposite job of an encoder. It is a combinational circuit that converts n lines
of input into 2n lines of output. Each input code word produces a different output code word
i.e. there is one to one mapping can be expressed in truth table.
Let’s take an example of 3-to-8 line decoder

Computer Architecture Logic Design Lab Manual 44

LOGIC DIAGRAM FOR DECODER

TRUTH TABLE

INPUT OUTPUT

E A B D0 D1 D2 D3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Computer Architecture Logic Design Lab Manual 45

APPLICATIONS:

 Speed synchronization of multiple motors in industries.

 War field flying robot with a night vision flying camera.
 A robotic vehicle with the metal detector.
 RF-based home automation system.
 Automatic health monitoring systems.

PROCEDURE

 Connections are given as per circuit diagram.

 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

REVIEW QUESTIONS

1. Using logic gates, implement 3x8 Decoder on Heath kit

2. Implement the full adder function (sum and carry) using 3X8 Decoder. Draw the logic
diagram.

POST LAB

3. Implement a 2x4 decoder using two 1x2 decoders on kit.

4. Implement the function [(A xnor C)(A xor C) + AC]’ using 2x4 Decoder
5. Draw the logic diagram of a 4X16 decoder using two 3x8 Decoders
6. Design an encoder using NOR gates only.

Computer Architecture Logic Design Lab Manual 46

 EXPERIMENT 7 – INTRODUCTION TO EMU8086 and REGISTERS
Objective
 Introduction of Emu8086
 To understand how programs are written in Emu8086 using Assembly Language
Time Required : 3 hrs
Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Introduction

Emu8086 is a program that compiles the source code (assembly language) and executes it. You
can watch registers, flags and memory while your program executes. Arithmetic & Logical Unit
(ALU) shows the internal work of the central processor unit (CPU). Emulator runs programs on a
Virtual PC; this completely blocks your program from accessing real hardware, such as hard-
drives and memory, 8086 machine code is fully compatible with all next generations of Intel's
microprocessors.

Where to start?
 Start Emu8086 by selecting its icon from the start menu, or by running Emu8086.exe.
 Select "Samples" from "File" menu.
 Click [Compile and Emulate] button (or press F5 hot key).
 Click [Single Step] button (or press F8 hot key), and watch how the code is being executed.
 Try opening other samples, all samples are heavily commented, so it's a great learning tool.

Directives
ORG 100h is a compiler directive (it tells compiler how to handle the source code). This
directive is very important when you work with variables. It says to compiler that the executable
file will be loaded at the offset of 100h (256 bytes), so compiler should calculate the correct
address for all variables when it replaces the variable names with their offsets. Directives are
never converted to any real machine code.
Why executable file is loaded at offset of 100h? Operating system keeps some data about the
program in the first 256 bytes of the CS (code segment), such as command line parameters and
etc.
Offset is use to get the offset address of the variable in register specified.

MOV instruction
 Copies the second operand (source) to the first operand (destination).
 The source operand can be an immediate value, general-purpose register or memory location.
 The destination register can be a general-purpose register, or memory location.
 Both operands must be the same size, which can be a byte or a word.
Syntax:
mov destination, source

Example:

Computer Architecture Logic Design Lab Manual 47

mov ax, 10 ; puts the value of 10 in the register ax
mov cx, ax ; puts the value contained in the register ax into cx

Register is a series of memory cells inside the CPU itself. Because registers are inside the CPU
there is very little overhead in working with them. There are four general purpose registers, AX,
BX, CX, and DX. These are the registers you will be using often. Each of these general registers
is 16- bit. They also have 8-bit counterparts. AX is 16 bits where as AH and AL is 8bit.
Note: - AH being the high bit, and AL being the low bit. Together AH and AL make AX.

Procedure is a part of code that can be called from your program in order to make some specific
task. Procedures make program more structural and easier to understand. Generally procedure
returns to the same point from where it was called.

 db stands for "define byte" and it's used to define a sequence of bytes.
 In this case, the sequence includes the characters "Hello", "World", followed by a carriage
return (0dh), a line feed (0ah), and a dollar sign ($).
 The carriage return and line feed characters are used to control the cursor position when
printing the message.
 The dollar sign likely marks the end of the message

Computer Architecture Logic Design Lab Manual 48

Registers
Registers are high-speed storage locations directly inside the CPU, designed to be accessed at
much higher speed than conventional memory.
Types of registers
 General purpose Registers
 Segment Registers
 Status Flags Register
 Instruction Pointer

General Purpose Register: Can be divided into Data and Index

 Data Registers: Are used for arithmetic and data movement

AX (Accumulator register)
BX (Base Register)
CX (Counter Register)
DX (Data Register)

 Index Register: Contains the offsets of data and instructions.

BP (Base pointer Register)
SP (Stack pointer Register)
SI (Source Index Register)
DI (Destination Index Register)

CX (Count Register)
 Contains the count for certain instructions e,g shift count, rotate the number of bytes and a
counter with loop instruction.
 Can be accessed as 32 bit (ECX), 16 bit (CX) or 8 bit (CH or CL) register 32 bit
 General Purpose use in ADD, MUL, DIV, MOV
 Special Purpose use in LOOP etc.

Computer Architecture Logic Design Lab Manual 49

Web Resources
http://www.svu.edu.eg/specialunits/acadeet/dwnldFiles/trainMater/provis/emu86_short.pdf
Videos Resources
www.youtube.com/watch?v=pcyvLYb5XDc
www.youtube.com/watch?v=SqcVG6CA4J4

EXERCISES
Exercise 7.1

Copy all example of assembly language one by one in Emu8086 and execute them. Practice all
these examples and show output.

Computer Architecture Logic Design Lab Manual 50

 EXPERIMENT 8 –INPUT/ OUTPUT SINGLE AND MULTI-DIGIT
NUMBER, CHARACTERS & DISPLAY STRINGS
Objective
 To learn about signed and unsigned numbers
 Practice how to Input, Output single and multi-digit number.
 Addition and subtraction of numbers
Time Required : 3 hrs
Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Introduction to Input / Output

 In 8086 assembly language, we use a software interrupt mechanism for I/O.
 An interrupt signals the processor to suspend its current activity (i.e. running your program)
and to pass control to an interrupt service program (i.e. part of the operating system).
 A software interrupt is one generated by a program (as opposed to one generated by
hardware).
 The 8086 INT instruction generates a software interrupt.
 For I/O and some other operations, the number used is 21h.
 A Specific number is placed in the register AH to specify which I/O operation (e.g. read a
character, display a character) you wish to carry out.
 When the I/O operation is finished, the interrupt service program terminates and program
will be resumed at the instruction following int.

Computer Architecture Logic Design Lab Manual 51

Character Input from User
To get the input from keyboard a subprogram at 1h will be called. First 1h will be placed in ah
and then an interrupt 21h generated to call the subprogram. Finally the character will be placed
in al register.

Example:
Mov ah,1h ;keyboard input subprogram
INT 21h ;call the sub program to take character input from the user and store in al

Note:-
 Carriage Return ASCII (0DH) is the control character to bring the cursor to the start of a line.
;display Return
mov dl, 0dh
mov ah, 2h
int 21h ; display Carriage Return

 Line-feed ASCII (oAh) is the control character that brings the cursor down to the next line on
the screen.
;display Line-feed
mov dl, 0ah
mov ah, 2h
int 21h ; display Line Feed

Computer Architecture Logic Design Lab Manual 52

Computer Architecture Logic Design Lab Manual 53
String Output
 A string is a list of characters treated as a unit.
 In 8086 assembly language, single or double quotes may be used to denote a string constant.
 For Defining String Variables following 3 definitions are equivalent ways of defining a string
"abc":
var1 db "abc" ; string constant
var2 db ‘a’, ‘b’, ‘c’ ; character constants
var3 db 97, 98, 99 ; ASCII codes

 The first version simply encloses the string in quotes. (preferred method)
 The second version defines a string by specifying a list of the character constants that make
up the string.
 The third version defines a string by specifying a list of the ASCII codes that make up the
string
 In order to display string using MS-DOS subprogram (number 9h), the string must be
terminated with the ‘$’ character.
 In order to display a string we must know where the string begins and ends.
 The beginning of string is given by obtaining its address using the offset operator.
 The end of a string may be found by either knowing in advance the length of the string or by
storing a special character at the end of the string.

Computer Architecture Logic Design Lab Manual 54

Character storage
 Computer stores binary numbers, so how character ‘A’ and ‘$’ are stored.
 Computer uses character encoding scheme that translate numbers into letters.
 Well-known scheme is ASCII (American Standard code for Information
Interchange)
 ASCII is 7 bit code with range 0 to 127.
Signed Numbers
 Signed byte uses only 7 bits for its magnitude.
 Highest bit is reserved for the sign, where 0 indicates positive and 1 indicates
negative.
Example:
11110110 = - 10
00001010 = + 10
Two’s Complement Notation
 Negative numbers use Two’s complement representation.
 Removes the need for separate digital circuits to handle both addition and
subtraction.
Example: A – B = A + (-B)
To find Twos complement, toggle all bits and add 1.
00000001 = + 1
11111110 (toggle all bits)
+ 1 (add 1)
---------------
11111111 = - 1
Example:
00001010 = + 10
11110101 (toggle all bits)
+ 1 (add 1)
---------------
11110110 = - 10
Two’s Complement of Hexadecimal
 To form the two’s complement of a hexadecimal integer, reverse all bits and
add 1
 Easy way to reverse the bits of a hexadecimal digit is to subtract the digit from
15.
Example:
6A3D --> 95C2 + 1 --> 95C3

Computer Architecture Logic Design Lab Manual 55

Library of common functions - emu8086.inc

To make programming easier there are some common functions that can be
included in your program. To make your program use functions defined in other
file you should use the INCLUDE directive followed by a file name. Compiler
automatically searches for the file in the same folder where the source file is
located.

To use any of the functions in emu8086.inc you should have the following line in
the beginning of your source file:
include 'emu8086.inc'

emu8086.inc also defines the following procedures:

 SCAN_NUM - procedure that gets the multi-digit SIGNED number from the
keyboard, and stores the result in CX register. To use it declare:
DEFINE_SCAN_NUM before END directive.

 PRINT_NUM - procedure that prints a signed number in AX register. To

use it declare: DEFINE_PRINT_NUM andDEFINE_PRINT_NUM_UNS
before END directive.

 PRINT_NUM_UNS - procedure that prints out an unsigned number in AX

register. To use it declare:DEFINE_PRINT_NUM_UNS before END
directive.

Computer Architecture Logic Design Lab Manual 56

Computer Architecture Logic Design Lab Manual 57
Computer Architecture Logic Design Lab Manual 58
 EXERCISES
Exercise 8.1
Write a program that input a character from user is in lowercase, the program will convert it to
uppercase and will display it on console after conversion.

Hint: - The ASCII codes for lowercase letters (a-z) are 97-122. In order to convert a
lowercase letter to uppercase letter, just subtract 32 from its ASCII code.

Exercise 8.2
Write a program that input a character from user. The program will display it ten times on screen
in newline.

Exercise 8.3
Write a program that will display uppercase letters (A-Z), using loop on new line.

Exercise 8.4:
Write a program that takes two numbers from user and display their sum as follows:

Enter first number: 25

Enter second number: 50
The sum of two numbers is: 75

Exercise 8.5:
Write a program that reads five unsigned integers from user and display sum of those
five integers on the screen.

Exercise 8.6:
Write a program that reads a number from the user. The program should then take the
sum of numbers from 1 to that number and print it on screen.

Exercise 8.7:
Write a program that reads a number from the user. The program should take sum of a
number and its negative and print on screen.

Exercise 8.8:
Write a program that takes two numbers from user. The program should display all the
numbers between them. The program should also display the sum of all those numbers.

EXPERIMENT 9 – ARITHMETIC INSTRUCTIONS

Objective

Computer Architecture Logic Design Lab Manual 59

  Use of Arithmetic Operators
 Operation with signed and unsigned values
 Solve mathematical equations

Time Required: 3 hrs

Programming Language: Assembly Language
Software Required: EMU 8086
Hardware Required: NIL

Multiplication Instructions (MUL, IMUL)

There are two versions of multiplication instructions, MUL instruction is for unsigned
multiplication and IMUL instruction is for signed multiplication. These types of operands are
supported by MUL and IMUL:
REG
Memory
REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
memory: variable, [BX], etc...

MUL -Unsigned multiply:

When operand is a byte:
AX = AL * operand.
When operand is a word:
(DX AX) = AX * operand.
Example: Multiply AX by 10h (16 bit)
.data
Var1 dw 2000h
Var2 dw 0010h
.code
MOV ax, Var1
MUL var2 ;DX=0002h, AX=0000h

IMUL -Signed multiply:

When operand is a byte:
AX = AL * operand.
When operand is a word:
(DX AX) = AX * operand.
Example: Multiply AX by 10h (8 bit)
.code
MOV al,1
MOV bl,-1
IMUL bl ;AX=1111111111111111b
;CF=0, OF=0

Computer Architecture Logic Design Lab Manual 60

Division Instructions (DIV, IDIV)
There are two versions of division instructions, DIV instruction is for unsigned multiplication
and IDIV instruction is for signed multiplication. These types of operands are supported by DIV
and IDIV:
REG
memory
REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
memory: variable, [BX], etc...

The dividend is always double the size of divisor. The implicit dividends for these instructions
are as bellow

DIV -Unsigned divide:

When operand is a byte:
AL = AX / operand
AH = remainder (modulus). .
When operand is a word:
AX = (DX AX) / operand
DX = remainder (modulus).
Example: 8 bit division (83h/2=40h, remainder=3)
.code
MOV ax, 0083h ; dividend
MOV bl,2 ; divisor
DIV bl ; AL=40h, AH=03h

IDIV -Signed divide:

When operand is a byte:
AL = AX / operand
AH = remainder (modulus). .

When operand is a word:

AX = (DX AX) / operand
DX = remainder (modulus). .
Example: Divide -48 by 5
.code
MOV ah, 0
MOV al,-48
MOV bl, 5 ; AX=00D0h
IDIV bl ; AL=40h, AH=03h

Computer Architecture Logic Design Lab Manual 61

Result would be wrong. To correct this error, you will have used conversion instruction CBW
(convert byte to word) listed bellow.

Web Resources
http://www.svu.edu.eg/specialunits/acadeet/dwnldFiles/trainMater/provis/emu86_short.pdf

Videos Resources
www.youtube.com/watch?v=pcyvLYb5XDc
www.youtube.com/watch?v=SqcVG6CA4J4

Computer Architecture Logic Design Lab Manual 62

 EXERCISE
Exercise 9.1:
Try to write a program that Multiply two bytes variables Var1=-10 and Var2=2
and stores the result in memory.

Exercise 9.2:
Try to write a program to use the SCAN_NUM to input prompt for values for three variables x, y
and z and the PRINT_NUM to display an appropriate label and value of the expression x – y + 2z –
1.

Exercise 9.3:
Try to write an assembly language program that prompts for and inputs the length, width, and height
of a box and calculates and displays its surface area.
surface area = 2 * (length * width + length * height + width * height)

Exercise 9.4:
Try to write an assembly language program that takes a number from user and finds its factorial.

Exercise 9.5:
Try to write an assembly language program that takes a number from user and prints its table.

Exercise 9.6:
Try to write an assembly language program that takes a number from a user and find its square and
cube.

Exercise 9.7:
Try to write a program that divide word size variables Var1=-500 and Var2=2 and stores the
result in memory.

Exercise 9.8:
Try to write an assembly language program that prompts for inputs %marks of four exams M1,
M2, M3, and M4. Suppose that M4 is a final exam that counts twice as much as the other three.
Calculate the sum (adding the last grade twice) and the average (sum/5). Display the sum and
average on two lines of a message box, each line with an appropriate label.

Exercise 9.9:
Try to write a program that takes input from user in Celsius and Convert the temperature to
Fahrenheit.

Computer Architecture Logic Design Lab Manual 63

 F = (9/5) *C + 32

Exercise 9.10:

Try to write a program that solve the following equation:

4 3
(3 x + x )
z=
( x ¿¿ 2−2 x +1)¿

Computer Architecture Logic Design Lab Manual 64

 EXPERIMENT 10 – EXPLORING FLAG REGISTER

Objective
 Identification of Flag register
 Type of flag register
 Learn which flag bits are affected by different instructions

Time Required : 3 hrs

Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Flag Register
 Determines the current state of the processor.
 They are modified automatically by CPU after mathematical operations, this allows to
determine the type of the result, and to determine conditions to transfer control to other parts
of the program.
 Generally, you cannot access these registers directly.

Status Flags:
The Status flags reflect the outcomes of arithmetic and logical operations performed by the CPU.
You do not need to alter the value yourself.
 Carry flag (CF) is set when the result of an unsigned arithmetic operation is too large to fit
into the destination (unsigned overflow). For example, when you add bytes 255+1 (result is
not in range 0...255). When there is no overflow, this flag is set to 0. This flag uses bit 0.
Example:
mov ah, 253
add ah, 12
These set of instructions will set the carry flag to 1 as the result of an unsigned arithmetic
operation is too large to fit into the destination (ah).
 Parity flag (PF) is set if the least-significant byte in the result contains an even number of 1
bit. Even if result is a word only 8 low bits are analyzed. This flag uses bit 2.
Example:
Mov al, 05 (load 05H in register ax)
This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101, which
contains even number of ones i.e., 2.
 Auxiliary Carry flag (AC) is set when an arithmetic operation causes a carry from bit 3 to
bit 4. (Unsigned overflow for low nibble -4 bits) This flag uses bit 4.
Example:
MOV ax, 2B (load 2BH in register A)
MOV bx, 39 (load 39H in register B)
ADD ax, bx
These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39,
addition of lower order nibbles B and 9 will generate a carry.

Computer Architecture Logic Design Lab Manual 65

 Zero flag (ZF) is set when the result of an arithmetic or logical operation generates a result
of zero. For none zero result this flag is set to 0. This flag uses bit 6.
Example:
mov ax, 10 (load 10H in register ax)
sub ax, 10
These set of instructions will set the zero flag to 1 as 10H – 10H is 00H
 Sign flag (SF) is set when the result of an arithmetic or logical operation generates a
negative result. This flag takes the value of the most significant bit. This flag uses bit 7.
Example:
mov al, 50 (50 is 01010000 which is positive)
mov bl, 32 (32 is 00110010 which is positive)
add al, bl (82 is 10000010 which is negative)
 Overflow flag (OF) is set when the result of a signed arithmetic operation is too large or too
small to fit into the destination (signed overflow). For example, when you add bytes 100 +
50 (result is not in range -128...127). This flag uses bit 11.

Carry Flag:
Control flags control the CPU’s operation.
 Direction Flag (DF) this flag is used by some instructions to process data chains, when this flag
is set to 0- the processing is done forward, when this flag is set to 1 the processing is done
backward. This flag uses bit 10.
 Interrupt enable Flag (IF) when this flag is set to 1 CPU reacts to interrupts from external
devices. This flag uses bit 9.
 TF (Trap Flag) This flag is used to Control Permits operation of the processor in single-step
mode. This flag uses bit 8.

Computer Architecture Logic Design Lab Manual 66

MUL Operators
MUL and IMUL instructions affect CF, OF flags only.
Boolean Operators
AND Instruction
It always clears the overflow and carry flags. It modifies SIGN, ZERO and PARITY flags according
to the value of the destination operand.
OR Instruction
It always clears the overflow and carry flags. It modifies SIGN, ZERO and PARITY flags according
to the value of the destination operand.
XOR Instruction
It always clears the overflow and carry flags. It modifies SIGN, ZERO and PARITY flags according
to the value of the destination operand.
NOT Instruction
NOT instruction does not affect any flags.
NEG Instruction
CF, ZF, SF, OF, PF, AF flags are affected by this instruction.
Test Instruction
FLAGS: CF, ZF, SF, OF, PF, AF.

CMP Instruction
CMP (compare) instruction performs an implied subtraction of a source from destination operand
i.e. Subtract second operand from first for flags only. Neither operand is modified.
CMP instructions affect flags only and do not store a result (these instructions are used to make
decisions during program execution).
FLAGS: CF, ZF, SF, OF, PF, AF.

Examples:
Destination < Source:
mov ax, 5
cmp ax, 10 ;CF = 1
Destination = Source
mov ax, 1000
mov cx, 1000
cmp cx, ax ; ZF = 1
Destination > Source
mov si, 105
cmp si, 0 ; ZF = 0 and CF = 0

Computer Architecture Logic Design Lab Manual 67

 EXERCISE
Exercise: 10.1: [7]

For each add instruction in this exercise, assume that AX contains the given contents before the
instruction is executed. Show the contents of AX as well as the values of the CF, OF, SF, PF, AF
and ZF after the instruction is executed. All numbers are in hex. (Hint: add ax, 45 adds 45 to the
contents of register ax and stores the result back in ax).

Content Instruction Contents CF OF SF PF AF ZF

s of AX of AX
(Before) (After)
0045 add ax, 45
FF45 add ax, 45
0045 add ax, -45
FF45 add ax, -45
FFFF add ax, 1

Exercise 10.2: [8]

In the following instruction sequence, show the values of the Carry, Zero, and Sign flags where
indicated:
mov al, 01001011b
test al, 10100100b ; a. CF= ZF= SF=
mov al, 00000110b
cmp al, 00000101b ; b. CF= ZF= SF=
mov al, 00000101b
cmp al, 00000111b ; c. CF= ZF= SF=

Computer Architecture Logic Design Lab Manual 68

 EXPERIMENT 11: BOOLEAN OPERATORS

Objective
 Learn how to use of Boolean operators

Time Required : 3 hrs

Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Boolean Operators
AND Instruction
AND instruction performs boolean (bitwise) AND operation b/w each pair of matching bits in
two operands and place the result in dest. operand.
AND dest, source
AND instruction can be b/w
AND reg, reg
AND reg, mem
AND reg, imm
AND mem, reg
AND mem,imm
Note: -Operand can be 8, 16 or 32 bits and they must be of same size.

OR Instruction
OR instruction performs boolean (bitwise) OR operation b/w each pair of matching bits in two
operands and place the result in dest. operand.
OR dest, source
OR instruction can be b/w
OR reg, reg
OR reg, mem
OR reg, imm
OR mem, reg
OR mem,imm

Note:- Operand can be 8, 16 or 32 bits and they must be of same size

XOR Instruction
XOR instruction performs boolean (bitwise) XOR operation b/w each pair of matching bits in
two operands and place the result in dest. operand.
XOR dest, source
Note:- XOR instruction uses the same operand combinations as AND and OR instructions.

NOT Instruction
NOT instruction toggles all bits in an operand.

Computer Architecture Logic Design Lab Manual 69

NOT reg
NOT mem
NEG Instruction
Make operand negative (two's complement). Actually, it reverses each bit of operand and then
adds 1 to it. For example, 5 will become -5, and -2 will become 2.
These types of operands are supported:
NEG reg
NEG mem

Activity 6.1 To subtract two numbers using NEG operator

org 100h
.data
num1 db 10
num2 db 5
.code
neg num2
mov al, num1
add al,num2

Test Instruction
TEST instruction performs an implied AND operation b/w each pair of matching bits in two
operands and set the flag accordingly. TEST operand1, operand2

The difference b/w TEST and AND instruction is that TEST Does not modify the destination
operand.

TEST instruction permits the same operand combinations as the AND instruction.

Figure 1 Converting to and from hexadecimal

Computer Architecture Logic Design Lab Manual 70

 EXERCISE
Exercise 11.1:
In the following instruction sequence. Show the changed value of AL where indicated, in binary:
mov a1, 00001111b
and al, 00111011b ;a
mov al, 6Dh
and al, 4Ah ;b
mov al, 00001111b
or al, 61h ;c
mov al, 94h
xor al, 37h ;d

Exercise 11.2:
In the following instruction sequence, show the changed value of registers where indicated, in
hexadecimal:
mov a1, 7Ah
not a1 ;a
mov a1, 3Dh
and al, 74h ;b
mov al, 9Bh
or al, 35h ;c
mov al, 72h
xor al, 0dch ;d

Exercise 11.3:
Write a single instruction that clears the high 8 bits of AX and does not change the
low 8 bits.

Exercise 11.4:
Write a single instruction that sets the high 8 bits of AX and does not change the
low 8 bits.

Computer Architecture Logic Design Lab Manual 71

 EXPERIMENT 12 – PROCEDURES IN ASSEMBLY

Objective
 Learn how to write procedures in Assembly
 Learn how to call procedures

Time Required : 3 hrs

Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Procedures
Procedure is a part of code that can be called from your program to make some specific task.
Procedures make program more structural and easier to understand. Generally, procedure returns
to the same point from where it was called.

name - is the procedure name, the same name should be in the top and the bottom, this is used to
check correct closing of procedures.

Probably, you already know that RET instruction is used to return to operating system. The same
instruction is used to return from procedure (actually operating system sees your program as a
special procedure).

PROC and ENDP are compiler directives, so they are not assembled into any real machine code.
Compiler just remembers the address of procedure.

CALL instruction is used to call a procedure.

Computer Architecture Logic Design Lab Manual 72

The above example calls procedure m1, does MOV BX, 5, and returns to the next instruction
after CALL: MOV AX, 2. There are several ways to pass parameters to procedure, the easiest
way to pass parameters is by using registers.

Web Resources
http://www.svu.edu.eg/specialunits/acadeet/dwnldFiles/trainMater/provis/emu86_short.pdf

EXERCISE
Exercise 12.1:
Write a program in assembly that takes two number from user in a procedure and calculates area
in main procedure.

Exercise 12.2:
Write a program in assembly language that call a procedure to calculate 2 4. (hint: use multiple
calls).

Computer Architecture Logic Design Lab Manual 73

 EXPERIMENT 13: OPEN ENDED LAB

In the context of OBE (Outcome-Based Education) system, an open-ended lab is a laboratory activity that
allows students to design and conduct their own experiments or investigations, without being restricted by
a predetermined procedure or outcome.

In an open-ended lab, students are given a problem or question to investigate, and are then required to
plan and carry out the experiment on their own. This type of lab allows students to apply critical thinking,
problem-solving, and decision-making skills, as they must make their own choices about what data to
collect, what variables to control, and what methods to use.

Open-ended labs can be challenging, as they require students to take greater responsibility for their
learning and may involve more uncertainty and risk. However, they can also be more engaging and
motivating for students, as they allow for greater creativity, exploration, and discovery.

Problem statement: Investigate the effect of cache size on the

performance of a computer system.
Materials and Equipment/PCs Details:

 A computer with a processor that supports different cache sizes (e.g., 2MB, 4MB, MB, 16MB,
32MB etc.)
 Benchmarking software (e.g., linepack, antutu, geekbench, SPEC CPU, or any other that you
familiar with)
 Performance measurement tools (e.g., perf)
 Any other you think as important.

Procedure and methodology: (CLO3=10 Marks, CLO4=10 Marks)
1. Formulate a hypothesis about how the cache size will affect the performance of the computer
system. CLO3, Cog 4
2. Plan an experiment to test your hypothesis. Consider factors such as the types of benchmarks to
use, the range of cache sizes to test, and the number of trials to perform. CLO4, P-3
3. Conduct the experiment by running the benchmarks on the computer system with different cache
sizes (you can use lab pcs, your own laptops, Mac system, all with different specs). CLO4, P-3
4. Collect performance data using the measurement tools. CLO4, P-3
5. Analyze the data to determine the effect of cache size on performance, and to validate or refute
your hypothesis. CLO3, Cog 4
6. Write a report summarizing your findings and conclusions. CLO3, Cog 4
7. Draw a complete working diagram (flow chart, algorithm, architectural diagram) to describe the
flow of processes. CLO3, Cog 4

Computer Architecture Logic Design Lab Manual 74

Deliverables:

OEL Proposal CLO3

OEL Diagrams, flow charts etc. CLO3

Benchmarking CLO4
(tools)/simulation parameters
(tabular form)/Results

Demo/Report and one pager CLO3, CLO4

summary

In this open-ended lab, You are free to design Your own experiments, choose benchmarks, and collect
data. You must use critical thinking and problem-solving skills to determine the best approach for testing
hypothesis. The open-ended nature of the lab allows for creativity and exploration, while still providing a
clear problem statement and objectives.

Computer Architecture Logic Design Lab Manual 75

 EXPERIMENT 14 – DECISION INSTRUCTIONS
Objective
 Learn how to control the flow of program.
 Learn how to transfer control conditionally and unconditionally.
 Learn how to implement if statement

Time Required : 3 hrs

Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Unconditional JUMP Instructions

The JMP instruction causes an unconditional transfer to a target location inside the code
segment. This is similar to goto in a High Level Language. The location must be identified by a
code label which is translated by the assembler into an offset. The syntax is:
JMP targetLabel
When the CPU executes this instruction, the offset of targetLabel is moved into the instruction
pointer causing execution to immediately continue at the new location.

Conditional Jump Instruction

A conditional jump instruction branches to a destination label when a flag condition is true. If the
flag condition is false, the instruction immediately following the conditional jump is executed.
The syntax is: Jcond destination
cond refers to a flag condition, identifying the state of one or more flags. For example:
jz ;jump if zero (Zero flag set)
jnz ;jump if not zero (Zero flag clear)
Flags are set by arithmetic, comparison, and Boolean instructions. Each conditional jump
instruction checks one or more flags, returning a result of true or false. If the result is true, the
jump is taken; otherwise, the program skips the jump and continues to the next instruction.
Most common way to set flags for conditional branches is to use compare instruction that has the
following format:
cmp operand1, operand2

Computer Architecture Logic Design Lab Manual 76

 Instruction Description signed Flags
JO Jump if overflow OF = 1
JNO Jump if not overflow OF = 0
JS Jump if sign SF = 1
JNS Jump if not sign SF = 0
JE Jump if equal ZF = 1
JZ Jump if zero
JNE Jump if not equal ZF = 0
JNZ Jump if not zero
JB Jump if below unsigned CF = 1
JNAE Jump if not above or equal
JC Jump if carry
JNB Jump if not below unsigned CF = 0
JAE Jump if above or equal
JNC Jump if not carry
JBE Jump if below or equal unsigned CF = 1 or ZF = 1
JNA Jump if not above
JA Jump if above unsigned CF = 0 and ZF = 0
JNBE Jump if not below or equal
JL Jump if less signed SF <> OF
JNGE Jump if not greater or equal
JGE Jump if greater or equal signed SF = OF
JNL Jump if not less
JLE Jump if less or equal signed ZF = 1 or SF <> OF
JNG Jump if not greater
JG Jump if greater signed ZF = 0 and SF = OF
JNLE Jump if not less or equal
JP Jump if parity PF = 1
JPE Jump if parity even
JNP Jump if not parity PF = 0
JPO Jump if parity odd
JCXZ Jump if CX register is 0 CX = 0
JECXZ Jump if ECX register is 0 ECX = 0

Computer Architecture Logic Design Lab Manual 77

Example:
Let's implement the following pseudo-code in assembly
language.
if value < 10 then
add 1 to smallCount;
print smallCount
else
add 1 to largeCount;
print largeCount
end if;
Assuming that the value is in BX and smallCount and
largeCount are in memory, the corresponding assembly
language coding is shown below:
cmp bx, 10
jnl elseLarge
inc smallCount
jmp endValueCheck
elseLarge:
inc largeCount
endValueCheck:
end main

Example:
consider the following pseudo-code:
if (total >= 100) or (count = 10) then
add value to total;
end if;

Assuming total and value are in memory and count in CX,

the assembly code is shown below:
cmp total, 100
jge addValue
cmp cx, 10
jne endAddCheck
addValue:
mov bx, value
add total, bx
endAddCheck:
end main

Web Resources
http://www.svu.edu.eg/specialunits/acadeet/dwnldFiles/trainMater/provis/emu86_short.pdf
Videos Resources
www.youtube.com/watch?v=pcyvLYb5XDc
www.youtube.com/watch?v=SqcVG6CA4J4

Computer Architecture Logic Design Lab Manual 78

 EXERCISES

Exercise 14.1: [2]

Try to write a program to print the sum of series 1+3+6+ … n and also print the value of ax and bx after
each step.

Note:- ax contains the sum of series and bx used as counter.

Exercise 14.2: [2]

Try to write a program to print the smallest number from three integers.

Exercise 14.3: [2]

Try to write an assembly language program that will repeatedly prompt for a number. After each number
is entered, display the sum and average of all the numbers entered so far.

Exercise 14.4: [3]

Try to write an assembly language code that implements the following if statement. Input an integer from
user and store in DX.

if (value < -1000) or (value > 1000) then

value := 0;
end if;

Exercise 14.5: [3]

Try to write an assembly language code that takes input an integer (less than 10) from user and print it in
English word e.g.
Please Input an integer (less than 10) = 6
You have Entered = Six

Exercise 14.6: [3]

Try to write an assembly language code that takes input an integer from user and print if its even or odd.

Computer Architecture Logic Design Lab Manual 79

 EXPERIMENT 15 – IMPLEMENTATION OF LOOP STRUCTURES

Objective:
 Learn how to repeat execution of a program fragment.
 Learn the working of loop instruction
 Learn implementation of while, until, and for loops.

Time Required : 3 hrs

Programming Language : Assembly Language
Software Required : EMU 8086
Hardware Required : NIL

Loop Instruction
The LOOP instruction provides a simple way to repeat a block of statements a specific number
of times. CX is automatically used as a counter and is decremented each time the loop repeats.
Its syntax is:
LOOP destination
The execution of the LOOP instruction involves two steps: First, it subtracts 1 from CX. Next, it
compares CX to zero. If CX is not equal to zero; a jump is taken to the label identified by
destination. Otherwise, if CX equals zero, no jump takes place and control passes to the next
instruction. In the following example, we add 1 to AX each time the loop repeats. When the loop
ends, AX = 5 and CX = 0:
mov ax, 0
mov cx,5
L1:
inc ax
loop L1

Computer Architecture Logic Design Lab Manual 80

Implementation of while Loop
A while loop can be indicated by the following pseudocode design:
while continuation condition loop
... { body of loop }
end while;

A while loop is a pre-test loop – the continuation condition, a Boolean expression, is checked
before the loop body is executed. Whenever it is true the loop body is executed and then the
continuation condition is checked again. When it is false execution continues with the statement
following the loop. It may take several 80x86 instructions to evaluate and check a continuation
condition. In 80x86 implementation of a while loop follows a pattern much like this one:
while1: . ; code to check Boolean expression
.
.
body: . ; loop body
.
.
jmp while1 ; go check condition again
endWhile1:

Example:
consider the following code
while (sum < 100) loop
sum=sum+count;
count=count+1;
end while;

Assuming sum in memory and count in CX, the

corresponding assembly code follows:

whileSum: cmp sum, 100

jnl endWhileSum
add sum, cx
inc cx
jmp whileSum
endWhileSum

Computer Architecture Logic Design Lab Manual 81

Implementation of for Loop
A for loop can be indicated by the following pseudocode design:
for index := initialValue to finalValue loop
... { body of loop }
end for;
A for loop is a counter-controlled loop that executes once for each value of a loop index (also
known as loop counter) in a given range. Often the number of times the body of a loop must be
executed is known in advance, either as a constant that can be coded when a program is written,
or as the value of a variable that is assigned before the loop is executed. In 80x86
implementation of a for loop follows a pattern much like this one:
mov cx, number ; number of iterations
jcxz endFor ; skip loop if number = 0
forIndex: . ; loop body
.
.
loop forIndex ; repeat body number times

Example:
Consider the following code

for index := 1 to 50 loop

... { loop body using index }
end for;

BX can be used to store index counting from 1 to 50, while the CX register counts down from 50
to 1.
The corresponding assembly code is as follows:

mov bx, 1 ; index := 1

mov cx, 50 ; number of iterations
forNbr: . ;
. ; use BX for index
.
inc bx ; add 1 to index
loop forNbr ; repeat

Computer Architecture Logic Design Lab Manual 82

Implementation of Until Loop
An until loop is a post-test loop – the condition is checked after the body of loop is executed. In
general, an until loop can be represented as follows:
repeat
... { body of loop }
until termination condition;
Termination condition is checked after the loop body is executed. If it is true, execution
continues with the statement following until loop. Otherwise, the loop body is executed again.
Thus, loop body is executed at least once. An 80x86 implementation of until loop follows:
until: . ; start of loop body
body: . ; code to check termination condition
enduntil:

Example:
consider the following code
repeat
add 2*count to sum;
add 1 to count;
until (sum > 1000);

Assuming that the sum references a word in memory, the following 80x86 code implements the
pseudocode, using the CX register for count.

repeatLoop: add sum, cx

inc cx
cmp sum, 1000
jng repeatLoop
endUntilLoop:

Web Resources
http://www.svu.edu.eg/specialunits/acadeet/dwnldFiles/trainMater/provis/emu86_short.pdf

Videos Resources
www.youtube.com/watch?v=pcyvLYb5XDc
www.youtube.com/watch?v=SqcVG6CA4J4

Computer Architecture Logic Design Lab Manual 83

 EXERCISES
Exercise 15.1:
Write a code in assembly language to print Fibonacci series. The number of terms to be
calculated will be entered by the user. 0 1 1 2 3 5 8…..

Exercise 15.2:
Write a program in assembly to break and print a 5-digit number in reverse order.

Exercise 15.3:
Compute the following equation in assembly language. N will be entered by the user.
F(x)=1+x/2+x/3+x/4+x/5+x/6…… up to n terms

Exercise 15.4:
Write a code to convert a decimal number into binary using assembly language.

Exercise 15.5:
Write an assembly language program that will prompt for an integer n and the print the table of n upto 20
on screen.

Exercise 15.6:
Write an assembly language program that will prompt for an integer n, compute the factorial of n and
display it on screen.

Computer Architecture Logic Design Lab Manual 84