Chapter Five

Analysis and synthesis of

Combinational logic circuits
 5.1. Introduction

▪ Logic circuit for digital system can be:

a. Combinational circuit
b. Sequential circuit
❑ Combinational circuit: is a circuit in which the output is depends on only
the present of inputs and consists
✓ Input variable
✓ Output variable
✓ Combinational logic gate
❑ Sequential circuit: is a circuit in which the output is depends on the present
and past inputs and consists
✓ Input variables
✓ Output variables
✓ Combinational logic gate
✓ Memory element
 5.2. Basic Combinational Logic Circuits

1. AND-OR logic:
▪ It produces Sum-of-Products (SOP) expression
▪ It can have any number of AND gates each with any number
of inputs
Product terms
A
AB
B
C CD
D AB + CD + . . . + JK
Sum-of-products
J
JK
K
Product term
 continued…

▪ An example of an SOP implementation is shown. The

SOP expression is an AND-OR combination of the input
variables and the appropriate complements.

A
B ABC
C X = ABC + DE SOP

D
DE
E
 continued…

2. AND-OR-Invert (AOI) logic:

✓ Is formed by inverting the output of a SOP form circuit
✓ The AOI configuration leads itself to product-of-sums (POS)
implementation.
▪ An example of an AOI implementation is shown.
▪ The output expression can be changed to a POS expression by
applying DeMorgan’s theorem twice.
A
B ABC
C X = ABC + DE X = ABC + DE AOI

D X = (ABC)(DE) DeMorgan
E DE X = (A + B + C)(D + E) POS
 continued…

3. Exclusive-OR logic:
✓ The truth table for an exclusive-OR Inputs Output
gate is A B X
✓ Notice that the output is HIGH 0 0 0
0 1 1
whenever A and B disagree. 1 0 1
1 1 0
▪ The Boolean expression is X = AB + AB

The circuit can be drawn as

A
Symbols:
X =1

Distinctive shape Rectangular outline

B
 continued…
4. Exclusive-NOR logic:
✓ The truth table for an exclusive-NOR gate
Inputs Output
is
A B X
✓ Notice that the output is HIGH whenever 0 0 1
0 1 0
A and B agree. 1 0 0
1 1 1
▪ The Boolean expression is X = AB + AB
The circuit can be drawn as
A Symbols:
X
B
=1

Distinctive shape Rectangular outline

For each circuit, determine if the LED should be on or off.
+5.0 V
+5.0 V
+5.0 V +5.0 V
+5.0 V +5.0 V
330 W
330 W
330 W
B LED
LED B LED
B
A
A A

(a) (b) (c)

Circuit (a): XOR, inputs agree, output is LOW, LED is ON.

Circuit (b): XNOR, inputs disagree, output is LOW, LED is ON.
Circuit (c): XOR, inputs disagree, output is HIGH, LED is OFF.
 5.3. Implementing Combinational Logic

▪ Implementing a SOP expression is done by first forming

the AND terms; then the terms are ORed together.
Show the circuit that will implement the Boolean expression
X = ABC + ABD + BDE. (Assume that the variables and
their complements are available.)
Start by forming the terms using three 3-input AND gates.
Then combine the three terms using a 3-input OR gate.
A
B
C
A X = ABC + ABD + BDE
B
D
B
D
E
 K-Map Implementation

▪ For basic combinational logic circuits, the K-Map can be

read and the circuit drawn as a minimum SOP.
A K-Map is drawn from a truth table. Read the minimum
SOP expression and draw the circuit.

C C
1. Group the 1’s into two overlapping
AB 1
B changes groups as indicated.
across this AB 1 1 2. Read each group by eliminating any
boundary variable that changes across a boundary.
AB 3. The vertical group is read A C.
C changes 4. The horizontal group is read AB.
AB
across this
boundary The circuit is on the next slide:
 continued…

Circuit: A
C X= AC + AB
A
B

The result is shown as a sum of products.

▪ It is a simple matter to implement this form using only

NAND gates as shown in the following example.
 continued…

Convert the circuit in the previous example to

one that uses only NAND gates.

Recall from Boolean algebra that double inversion cancels.

By adding inverting bubbles to above circuit, it is easily
converted to NAND gates:

A
C X= AC + AB
A
B
 From a truth table to a logic circuit
▪ By writing the SOP or POS expression from the truth table
we can implement the logic expression.
Develop a logic circuit with four input variables that will only
produce a 1 output when exactly three input variables are 1’s

✓ First develop a truth table of four input variables and find

the combinations which consists three 1’s.
✓ Then put 1 on the output of these combinations and find
their product term representation.
✓ The expression is SOP and produced by summing the
product terms produced from the truth table.
✓ Finally implement the SOP expression
 5.4. Universal property of NAND and NOR Gates
a) NAND gates:
✓ Are sometimes called universal gates because they can be
used to produce the other basic Boolean functions.

A A A AB
B
Inverter AND gate

A A
A+B A+B
B B

OR gate NOR gate

 continued…

b) NOR gates:
✓ Are also universal gates and can form all of the basic
gates.

A A A A+ B
B
Inverter OR gate

A A
AB AB
B B

AND gate NAND gate

 Implementation of Boolean function using NAND Logic

▪ Recall from DeMorgan’s theorem that AB = A + B. By

using equivalent symbols, it is simpler to read the logic of
SOP forms. The earlier example shows the idea:

A
C X= AC + AB
A
B

▪ The logic is easy to read if you (mentally) cancel the two

connected bubbles on a line.
 continued…

▪ To obtain a multilevel NAND gate diagram from Boolean

expression, follow the following steps
1. Draw a logic diagram for a given expression. (Assume, both the
complemented and uncomplemented input variables are available )
2. Convert all AND gates to NAND gates with AND-inverted graphic
symbol
3. Convert all OR gates to NAND gates with invert-OR graphic symbol
4. Check all small circles in the diagram, for every small circle that is not
compensated by another circle along the same line, insert an inverter
(one-input NAND gate) or complement the input variable.
5. Finally draw by using only NAND gate by replacing the invert-OR
gate with AND-invert gate.
continued…

Implement the following Boolean expression by

using NAND gate only
a. 𝐴𝐵𝐶 + 𝐷𝐸
ഥ + 𝐸ത
b. 𝐴𝐵𝐶 + 𝐷
c. 𝐴 + (𝐵ത + 𝐶)(𝐷
ഥ + 𝐵𝐸)
ത
ഥ + 𝐵𝐸)
d. (𝐶𝐷 + 𝐸)(𝐷 ത
 Implementation of Boolean function using NOR gates

▪ Alternatively, DeMorgan’s theorem can be written as

A + B = AB. By using equivalent symbols, it is simpler
to read the logic of POS forms. For example,

A
B X = (A + B)(A + C)
A
C

▪ Again, the logic is easy to read if you cancel the two

connected bubbles on a line.
 continued…

▪ To obtain a multilevel NOR gate diagram from Boolean

expression, follow the following steps
1. Draw a logic diagram for a given expression. (Assume, both the
complemented and uncomplemented input variables are available )
2. Convert all AND gates to NOR gates with invert-AND graphic symbol
3. Convert all OR gates to NOR gates with OR-invert graphic symbol
4. Check all small circles in the diagram, for every small circle that is not
compensated by another circle along the same line, insert an inverter
(one-input NOR gate) or complement the input variable.
5. Finally replace the invert-AND with OR-invert to implement using
only NOR gate.
continued…

Implement the following Boolean expression by

using NOR gate only
a. 𝐴𝐵𝐶 + 𝐷𝐸
ഥ + 𝐸ത
b. 𝐴𝐵𝐶 + 𝐷
c. 𝐴 + (𝐵ത + 𝐶)(𝐷
ഥ + 𝐵𝐸)
ത
ഥ + 𝐵𝐸)
d. (𝐶𝐷 + 𝐸)(𝐷 ത
 Logic circuit operation with pulsed waveform inputs

▪ For combinational circuits with pulsed inputs, the output can be

predicted by developing intermediate outputs for each gates and
combining the result.
▪ For example, the circuit shown can be analyzed at the outputs of
the OR gates:

A
A
G1
B B
G3
C
C
G2
D D
G1
G2
G3
 continued…

▪ Alternatively, you can develop the truth table for

the circuit and enter 0’s and 1’s on the Inputs Output
waveforms. Then read the output from the table. A B C D X
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
A
G1 0 0 1 1 1
B 0 1 0 0 0
G3 1
0 1 0 1
C 0 1 1 0 1
G2
D 0 1 1 1 1
1 0 0 0 0
A 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0
1 0 1 0 0
B 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0
1 1 0 0 0
C 0 0 0 1 1 1 1 0 0 0
1 1 0 1 1
D 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1
1 1 1 1 1
G3 0 0 0 0 1 1 1 0 1 0
 5.5. Design and function of combinational circuit

Design procedure
i. Starting defining the problem
ii. Determining the number of available input variable and required
output variable
iii. Assigning the input and output variables with letter symbols
iv. Construct a truth table that defines the relationship between the
inputs and outputs
v. Obtaining a simplified Boolean function for each output
vi. Draw the logic circuit diagram

▪ However certain restrictions, limitation and criteria will

serve as a guide in the process of choosing a particular
algebraic expression
 continued…
▪ The cost for a logic circuit depends on the total number of
gates plus the total number of inputs to all gates in the
circuit.
▪ Therefor, a particular design method would have to
consider such constructions as:
a. Minimum number of gates
b. Minimum number of inputs to gates
c. Minimum propagation time of the signal
d. Minimum number of interconnection (level of gates)

▪ But satisfying all the above simultaneously is difficult to

make a general statement.
 continued…

▪ However, in most cases the simplification is begin by

satisfying the elementary objective such as producing a
simplified Boolean function in standard forms

Assume that a large room has two doors and

that a switch near each door controls a light in
the room. Design a logic circuit for the
controlling a single lump by using the two
switches in the room
 Function of combinational circuit
1. Basic Adders
a) Half-Adder
▪ Basic rules of binary addition are performed Inputs Outputs
by a half adder, which has two binary inputs A B Cout S
(A and B) and two binary outputs (Carry out 0 0 0 0
and Sum). 0 1 0 1
1 0 0 1
▪ The inputs and outputs can be summarized 1 1 1 0
on a truth table.
▪ The logic symbol and equivalent circuit
are:
S
A S S

B Cout A
Cout
B
 continued…
b) Full-Adder

▪ By contrast, a full adder has three binary Inputs Outputs

inputs (A, B, and Carry in) and two binary A B Cin Cout S
outputs (Carry out and Sum). 0 0 0 0 0
0 0 1 0 1
▪ The truth table summarizes the operation. 0 1 0 0 1
0 1 1 1 0
▪ A full-adder can be constructed from two 1 0 0 0 1
half adders as shown: 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
S S
A A S A S Sum
S
B B Cout B Cout A S
B
Cout
Cin Cin

Cout Symbol
 continued…

S S 0 Sum
1 A S 1 A S

1
0 B Cout 0 B Cout

For the given inputs, determine 1 Cout

the intermediate and final outputs 1
of the full adder.
The first half-adder has inputs of 1 and 0;
therefore the Sum =1 and the Carry out = 0.
The second half-adder has inputs of 1 and 1; therefore the
Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry
out = 1.
 continued…

▪ Notice that the result from the previous example can be read
directly on the truth table for a full adder.

Inputs Outputs
A B Cin Cout S
S S 0 Sum
0 0 0 0 0 1 A S 1 A S
0 0 1 0 1
0 1 0 0 1 1
0 1 1 1 0 0 B Cout 0 B Cout
1 0 0 0 1
1 0 1 1 0 1 Cout
1 1 0 1 0
1 1 1 1 1 1
 continued…
c) Parallel Adders
▪ Full adders are combined into parallel adders that can add
binary numbers with multiple bits.
▪ A 4-bit adder is shown.
A4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4
C3 C2 C1
S4 S3 S2 S1

▪ The output carry (C4) is not ready until it propagates through

all of the full adders. This is called ripple carry, delaying the
addition process.
 continued…

▪ The logic symbol for a 4-bit parallel adder is shown.

▪ This 4-bit adder includes a carry in (labeled (C0) and a Carry
out (labeled C4).
S
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

▪ The 74LS283 is an example.

✓ It features look-ahead carry, which adds logic to minimize the output
carry delay. For the 74LS283, the maximum delay to the output carry
is 17 ns.
 2. Comparators
▪ The function of a comparator is to compare the magnitudes of
two binary numbers to determine the relationship between them.
▪ In the simplest form, a comparator can test for equality using
XNOR gates.
How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1
A2
B2 Output
A3
B3
A4
B4
 continued…

▪ IC comparators provide outputs to indicate which of the numbers is larger or

if they are equal.
▪ The bits are numbered starting at 0, rather than 1 as in the case of adders.
▪ Cascading inputs are provided to expand the comparator to larger numbers.
determine the output of the comparator for A=0110 and B=0011
COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 B
The IC shown is the
B2
B3 3 4-bit 74LS85.
 3. Decoders
▪ Decoder is a logic circuit that converts a binary information from n
input lines to a maximum of 2𝑛 unique output lines
▪ It produces 2𝑛 mini-terms of n input variables and each output
represents one of the mini-terms
Construct 2x4 decoder circuit

The truth table and circuit for the decoder is

 continued…

▪ It detects the presence of a specific combination of bit at is input

▪ Two simple decoders that detect the presence of the binary code 0011
are shown below
▪ The first has an active HIGH output; the second has an active LOW
output
A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011
continued…

Assume the output of the decoder shown is a

logic 1. What are the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1
 continued…

▪ IC decoders have multiple outputs to decode any combination of

inputs.
▪ For example the binary-to-decimal decoder shown here has 16
outputs – one for each combination of binary inputs.
Bin/Dec
0 1
For the input shown, 1 1
what is the output of the 2 1
3 1
active LOW decoder? 4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1
 continued…

▪ Most IC decoders include one or more enable(E) inputs to control

the circuit operation.
▪ The decoder is active when E is 1, otherwise it will be inactive
▪ These enable lines are used to expand the digital functions by
connecting two or more IC packages.
▪ Therefor, it is possible to connect decoders to form a larger
decoder circuit

Implement 3x8 decoder by using two 2x4

decoders
continued…

The block diagram is

 4. Encoders

▪ The decimal to BCD is an example of 1

A0
encoder with an input for each of the 2
ten decimal digits and four outputs that 3
A1
represent the BCD code for the active
digit. 4
5 A2
▪ The basic logic diagram is shown and 6
7
there is no zero input because the 8
A3
outputs are all LOW when the input is 9
zero.
continued…

Show how the decimal-to-BCD encoder converts the

decimal number 3 into a BCD 0011.

The top two OR gates have ones as indicated with

the red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9
 continued…
VCC

R7 R8 R9

Keyboard
7 8 9
encoder HPRI/BCD
1
R4 R5 R6 2
3 1
4 2
5 4 BCD complement of
6
4 5 6 7
8 key press
8
9

R1 R2 R3 74HC147

1 2 3

R0
The zero line is not needed by the
0 encoder, but may be used by other
circuits to detect a key press.
 5. Code converters

▪ There are various code converters that change one code to another.
▪ Two examples are the four bit Binary-to-Gray converter and the
Gray-to-Binary converter.

Show the conversion of binary 0111 to Gray and back.

0 1 LSB
1 0
LSB
0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary
 6. Multiplexers (Data selector)

MUX
0
S0 0
Data 1 1
select S1
▪ Two select lines are shown here Data
D0 0
to choose any of the four data D1 1 output
Data
inputs. D
inputs D2 2
3 3

Which data line is selected if

S1S0 = 10? D2
continued…

Consider 4x1 multiplexer or 4 input multiplexer

If we have 4 inputs (𝐼0 , 𝐼1 , 𝐼2 , 𝐼3 ) we will have 2

selection line (𝑆0 , 𝑆1 , ) and one output Y
 continued…

▪ The circuit diagram is

 continued…

▪ Multiplexer ICs may have an enable input to control the

operation of the unit
▪ The enable can be used to expand two or more MUX ICs to
a digital multiplexer with a larger number of inputs
▪ Consider implementing of 8:1 MUX using two 4:1 MUX
7. De-multiplexers (Distributer)
 continued…

The serial data input waveform and data select inputs are shown
below. Determine the data output waveforms on for the above demultiplex