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Computer Architecture
Chapter Two
Register Transfer
Language (RTL)
 Copyright Notice
Architecture
Computer

Parts (text & figures of this lecture are adopted from:

M. M. Mano, C. R. Kime & T. Martin, “Logic & Computer

Design Fundamentals”, 5th Ed., Pearson, 2015

M. Morris Mano, “Computer System Architecture”, Pearson,

1999

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 M. Morris Mano
Architecture
Computer

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 Contents
Architecture
Computer

 Introduction
 RTL notifications
 Micro-operations:
 Bus & memory transfers
 Arithmetic, Logic, Shift

 Bus Design

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 Digital System
Architecture
Computer

 An interconnection of digital hardware

modules, that are constructed from
digital components, such as:

 Registers

 Decoders

 Arithmetic elements

 Control logics

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 Computer Architecture
Architecture
Computer

 A high-level description of the hardware

from the ISA perspective
 Typically divided into
 a datapath
 a control unit

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 Datapath Basic Components
Architecture
Computer

 A set of registers,
 The micro-operations performed on data
stored in the registers
 The control interface.

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 Control Unit
Architecture
Computer

 Provides signals that control the micro-

operations performed in the datapath
and in other components of the system,
such as memories

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 Interaction of Data Path & Control Unit
Architecture
Computer

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 Instructions vs. Micro-operations
Architecture
Computer

?
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 Instructions
Architecture
Computer

 A group of bits that instructs a digital system

(computer) to perform a specific action

 Includes:
 Opcode (Operation code)

 Operand(s)

 For every operation code the control unit

issues a sequence of control signals to initiate
µoperations in internal computer registers

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 Micro-Operations
Architecture
Computer

 Elementary operations executed on data

stored in registers
 Shift, count, clear, load, …

 The result of the operation may

 Replace the previous data of the register

 Be transferred to another register

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 Register Transfer Language
Architecture
Computer

A system for expressing in symbolic form,

the µoperation sequences among the
registers of a digital module

Every RTL statement implies a hardware construction for

implementing the transfer in exactly one clock cycle

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 4-Bit Register
Architecture
Computer

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 4-Bit Register with Parallel Load
Architecture
Computer

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Architecture

Block Diagrams of Registers

Computer

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Architecture

Basic Symbols for Register Transfers

Computer

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 Control Function
Architecture
Computer

if (K1=1) then (R2 ← R1)

is designated as:

K1: R2 ← R1

A Boolean variable that states the condition

on which the transfer should be performed

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Architecture

Register Transfer
Computer

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 Remark!
Architecture
Computer

What are the contents of R1 and R2 after this

µoperation:

P: R2 ← R1, R1 ← R2

?
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 Micro-operation Types
Architecture
Computer

 Arithmetic µoperations

 Logic µoperations

 Shift µoperations

 Bus & memory transfers

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 Arithmetic Micro-Operations
Architecture
Computer

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 Implementation of Add & Subtract µOps
Architecture
Computer

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 Logic Micro-Operations
Architecture
Computer

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 Example: Register Cell Design
Architecture
Computer

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 Examples of Shifts
Architecture
Computer

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 4-bit Shift Register
Architecture
Computer

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 Serial Transfer
Architecture
Computer

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 Example of Serial Transfer
Architecture
Computer

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 Serial Addition
Architecture
Computer

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 Memory Transfer
Architecture
Computer

Read: DR ← M[AR]
Write: M[AR] ← DR

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 Use of Multiplexers
Architecture
Computer

to select between two registers

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 Generalization of Multiplexer Selection
Architecture
Computer

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 Single Bus vs. Dedicated Multiplexers
Architecture
Computer

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 Examples of Register Transfers
Architecture
Computer

using the single bus

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 Three-State Buffer
Architecture
Computer

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 Three-State Buffers
Architecture
Computer

forming a multiplexed line OL

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 Three-State Bus vs. Multiplexer Bus
Architecture
Computer

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 Final Overview
Architecture
Computer

 Register Transfer Language (RTL):

 The symbolic notation used to describe the µoperation
transfers among registers

 Micro-operations:
 Elementary operations executed on data stored in registers
 Performed in exactly one clock cycle
 Bus & memory transfers
 Arithmetic
 Logic
 Shift

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 Internal HW Organization (in short)
Architecture
Computer

 Set of registers & their functions

 Sequence of µoperations performed on

them

 The control that initiates the sequence

of µoperations

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 Block Diagram of a Generic DataPath
Architecture
Computer

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