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CD Mid2 Qpprint

This document outlines the details for the Mid Examinations-II for III B.Tech. (II Semester) in Compiler Design at GVP College of Engineering for Women, scheduled for April 30, 2024. It includes instructions for answering questions, the maximum marks available, and specific questions related to compiler design concepts such as leaders of basic blocks, peephole optimization, register allocation, and back patching. The exam is conducted by faculty members Dr. N. Sharmili and Mrs. K. Suneetha.
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0% found this document useful (0 votes)
6 views2 pages

CD Mid2 Qpprint

This document outlines the details for the Mid Examinations-II for III B.Tech. (II Semester) in Compiler Design at GVP College of Engineering for Women, scheduled for April 30, 2024. It includes instructions for answering questions, the maximum marks available, and specific questions related to compiler design concepts such as leaders of basic blocks, peephole optimization, register allocation, and back patching. The exam is conducted by faculty members Dr. N. Sharmili and Mrs. K. Suneetha.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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GVP COLLEGE OF ENGINEERING FOR WOMEN

MADHURAWADA::VISAKHAPATNAM
Department of CSE
III B.Tech. (II Semester) Mid Examinations-II, April 2024
Descriptive Type Examination (R-20 Regulations)
Subject: Compiler Design Code: R2032052 Date: 30-04-2024
Sections: CSE-1 & CSE-2 Timings: 9.00AM-10.30AM Duration: 90 min.
Name of the Faculty: Dr.N.Sharmili, Mrs.K.Suneetha
Answer all the Questions
Paper is for maximum of 30 Marks
Q.
Questions Marks CO BL
No.
Define leader of basic block? Analyze the algorithm used to find leaders.
1 (a) 6 4 L4
Draw the flow graph for matrix multiplication.
1 (b) Explain in detail about peephole optimization techniques. 6 4 L2
2 (a) Identify the register allocation and assignment in target code generation. 6 5 L3
2 (b) Compare and Contrast allocation strategies in runtime storage environment. 6 5 L2
Determine the types and relative addresses for the identifiers in the following
sequence of declarations:
3 (a) float x; 3 3 L4
record { float x; float y; } p;
record { int tag; float x; float y; } q;
3 (b) Illustrate the concept of Back patching in intermediate code generation. 3 3 L2

GVP COLLEGE OF ENGINEERING FOR WOMEN


MADHURAWADA::VISAKHAPATNAM
Department of CSE
III B.Tech. (II Semester) Mid Examinations-II, April 2024
Descriptive Type Examination (R-20 Regulations)
Subject: Compiler Design Code: R2032052 Date: 30-04-2024
Sections: CSE-1 & CSE-2 Timings: 9.00AM-10.30AM Duration: 90 min.
Name of the Faculty: Dr.N.Sharmili, Mrs.K.Suneetha
Answer all the Questions
Paper is for maximum of 30 Marks
Q.
Questions Marks CO BL
No.
Define leader of basic block? Analyze the algorithm used to find leaders.
1 (a) 6 4 L4
Draw the flow graph for matrix multiplication.
1 (b) Explain in detail about peephole optimization techniques. 6 4 L2
2 (a) Identify the register allocation and assignment in target code generation. 6 5 L3
2 (b) Compare and Contrast allocation strategies in runtime storage environment. 6 5 L2
Determine the types and relative addresses for the identifiers in the following
sequence of declarations:
3 (a) float x; 3 3 L4
record { float x; float y; } p;
record { int tag; float x; float y; } q;
3 (b) Illustrate the concept of Back patching in intermediate code generation. 3 3 L2

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