Digital CMOS VLSI Circuits

(20IC402T)
Arpan Desai
ICT Department, PDEU
 Syllabus
COURSE OBJECTIVES
• To understand the characteristics and concepts related to the design of digital CMOS VLSI circuits/gates.
• To explore various CMOS logic styles, and design CMOS VLSI circuits/gates at the transistor-level and
layout-level.
• To analyze the performance/power of digital CMOS VLSI circuits/gates.

UNIT-1 INTRODUCTION TO DIGITAL CMOS VLSI

Trends in VLSI/Semiconductor industry, related to technology (Moore’s) scaling; ITRS Roadmap; Overview
of semiconductor devices inherent in the MOSFET: Drain-Body and Source-Body PN junctions, Metal-
semiconductor contacts, MOS Capacitor; IV characteristics of P-channel and N-channel planar MOSFETs;
Non-ideal effects; Basic steps of CMOS fabrication process/technology.

UNIT-2 DESIGN OF DIGITAL CMOS VLSI STANDARD AND COMPOUND GATES

Static CMOS inverter and its VTC characteristics; Resistive Load NMOS inverter and its VTC
characteristics; Pseudo NMOS inverter and its VTC characteristics; Design and transistor sizing of standard
gates (NAND, NOR, EXOR, tri-state INV) and compound gates.
 Syllabus
UNIT-3 PERFORMANCE AND POWER ANALYSES OF DIGITAL CMOS VLSI GATES/CIRCUITS
RC modelling and Elmore delay analysis of gates (pattern dependent delay analysis); Sutherland’s logical
effort method of delay estimation and sizing of cascaded paths/gates; Static and dynamic Power of gates;
Euler Diagram/Paths for layout of gates, stick diagrams, Lambda rules (DRC) and layouts of gates; Design,
simulate and analyze digital CMOS VLSI gates using SPICE and EDA tools.

UNIT-4 CMOS LOGIC STYLES

Pass-transistor tree based logic gates (and similar other logic styles – CPL, transmission gates, DPL, etc);
Pseudo-NMOS logic; CVLS logic; Dynamic logic (domino, NP domino, Zipper); Hybrid logic style and
examples (Full-Adder, MUX, XOR).

TEXT/REFERENCE BOOKS

1. Neil Weste, David Harris, Ayan Banerjee, “CMOS VLSI design: A circuits and systems perspective”, 3rd Edition,
Pearson.
2. Sung-Mo Kang, Yusuf Leblebici , “CMOS Digital Integrated Circuits”, 3rd Edition, Tata McGraw Hill.
3. Robert F. Pierret, “Semiconductor Device Fundamentals”, 1st Edition, Pearson.
 UNIT-1
INTRODUCTION TO DIGITAL
CMOS VLSI
 A Brief History of the Transistor
• Some of the events which led to the microprocessor
-Photographs in the following are from “State of the Art: A
photographic history of the integrated circuit”, Stan Augarten,
Ticknor & Fields, 1983.

• They can also be viewed on the Smithsonian web site

- http://smithsonianchips.si.edu/
- Another web site http://www.pbs.org/transistor/

• Another collection of interesting chip photos and other things.

- http://micro.magnet.fsu.edu/creatures/pages/chili.html
 Early Ideas Leading to the Transistor
• J. W. Lilienfeld’s patents

1930: “Method and apparatus for 1933: “Device for controlling electric
controlling electric currents”, U.S. current”, U. S. Patent 1,900,018
Patent 1,745,175
 Key Developments at Bell Labs
• 1940: Ohl develops the PN Junction
• 1945: Shockley's laboratory established
• 1947: Bardeen and Brattain create point contact transistor (U.S. Patent
2,524,035)
 Developments at Bell Labs, cont’d
• 1951: Shockley develops a junction transistor manufacturable in quantity
(U.S. Patent 2,623,105)
 1950s – Silicon Valley

• 1950s: Shockley in Silicon Valley

• 1955: Noyce joins Shockley Laboratories
• 1954: The first transistor radio
• 1957: Noyce leaves Shockley Labs to form Fairchild with Jean Hoerni and
Gordon Moore
• 1958: Hoerni invents technique for diffusing impurities into Si to build
planar transistors using a SiO2 insulator
• 1959: Noyce develops first true IC using planar transistors, back-to-back
PN junctions for isolation, diode-isolated Si resistors and SiO2 insulation
with evaporated metal wiring on top
 The Integrated Circuit (IC)
• 1959: Jack Kilby, working at TI, dreams up the idea of a monolithic
“integrated circuit” – Components connected by hand-soldered wires and
isolated by “shaping”, PN-diodes used as resistors (U.S. Patent 3,138,743)
 ICs, Cont’d
• 1961: TI and Fairchild introduce the first logic ICs
• 1962: RCA develops the first MOS transistor
 Moore’s Law
• The number of transistors on a microchip doubles approximately every two years,
leading to an exponential increase in computing power and efficiency while
reducing relative cost per transistor.
 Intrinsic Semiconductor
• Pure Silicon may be mixed with impurities to change the number of
available carriers.

• 4 Valance electrons which forms covalent bonds with other Silicon atoms.
(Intrinsic Semiconductor or Pure form of semiconductor)
 N-Type Semiconductors
Adding elements with 5 valence
electrons to pure silicon
N-Type Semiconductors
Adding elements with 5 valence
electrons to pure silicon

Fermi Level
 P-Type Semiconductors
Adding elements with 3
valence electrons to pure
silicon
P-Type Semiconductors
Adding elements with 3 valence
electrons to pure silicon

Fermi Level
 Summary

• Silicon is a semiconductor
• Pure silicon has no free carriers and
conducts poorly
• Adding dopants increases the
conductivity
• Group V: extra electron (n-type)
• Group III: missing electron, called
hole (p-type)
 P-N Junctions
• A junction between p-type and n-type semiconductor forms a diode.
• Current flows only in one direction

The depletion region contains immobile positive ions (donors) in the N-type material
and immobile negative ions (acceptors) in the P-type material. These ions are left behind
when the free electrons and holes recombine near the junction.
 nMOS Transistor
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
– Even though the gate is no longer made of metal
 nMOS Transistor
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
 pMOS Transistor
• Similar, but doping and voltages reversed
• – Body tied to high voltage (VDD)
• – Gate low: transistor ON
• – Gate high: transistor OFF
• – Bubble indicates inverted behavior
 Transistors as Switches
• We can view MOS transistors as electrically controlled switches
• Voltage at gate controls path from source to drain
CMOS Inverter

pMOS

nMOS
CMOS Inverter

pMOS

nMOS
CMOS Inverter

pMOS

nMOS
Fabrication of MOSFET’s
 Contents
• Fabrication of nMOS Transistor
Lithography/Patterning
Etching
Oxide Growth/Oxide Deposition
Ion Implantation
Device Isolation Techniques

• Fabrication of CMOS
 Fabrication of nMOS
a Si- substrate

Silicon Dioxide (SiO2)

b
Si- substrate
Silicon Dioxide (SiO2)
c Si- substrate
Thin oxide (SiO2)
Silicon Dioxide (SiO2)
d
Si- substrate
Oxidation

• Oxidation of the silicon surface

creates a SiO2 layer that acts as an
insulator.

• Oxide layers are also used to isolate

metal interconnections.
Etching

• Etching is a common process to pattern

material on the surface.

• Once the desired shape is patterned with

photoresist, the unprotected areas are
etched away, using wet or dry etch
techniques.
 Lithography/Patterning

• An IC consists of several layers of material that are

manufactured in successive steps.

• Lithography is used to selectively process the layers,

where the 2-D mask geometry is copied on the
surface.

•The surface of the wafer is coated with a photosensitive material, the photoresist.

•The mask pattern is developed on the photoresist, with UV light exposure.

•Depending on the type of the photoresist (negative or positive),the exposed or

unexposed parts of the photoresist change their property and become resistant to
certain types of solvents.
 Lithography/Patterning
Positive and Negative Photoresist
 Fabrication of nMOS
Functions of Various Layers
• Thin oxide layer:
- It forms the gate oxide of the MOS transistor.
- Dielectric layer that separates gate terminal of MOSFET from
source and drain region as well as the underlying conductive
channel that connects source and drain when the transistor is
turned on.
• Polysilicon Layer:
- Used both as gate electrode material and also as an
interconnect medium.
 Fabrication of nMOS
Polysilicon
Thin oxide (SiO2)
e Silicon Dioxide (SiO2)
Si- substrate
Polysilicon
Thin oxide (SiO2)
f Silicon Dioxide (SiO2)
Si- substrate

Polysilicon
Thin oxide (SiO2)
g Silicon Dioxide (SiO2)
Si- substrate
 Fabrication of nMOS
(SELF ALIGNED PROCESS)
• Polysilicon gate, which is patterned before doping defines:
i.) precise location of the channel region
ii.)location of source and drain regions

Since, this procedure allows very precise positioning of two regions relative to
the gate, it is called as Self Aligned Process.
 Fabrication of nMOS
Polysilicon
Thin oxide (SiO2)
h n+ n+ Silicon Dioxide (SiO2)
Si- substrate
Insulating Oxide
Thin oxide (SiO2)
i n+ n+ Silicon Dioxide (SiO2)
Si- substrate
Insulating Oxide
Thin oxide (SiO2)
j n+ n+ Silicon Dioxide (SiO2)
Si- substrate
Ion Implantation

• Ion implantation is used to add doping

materials to change the electrical
characteristics of silicon locally.

• The dopant ions penetrate the surface,

with a penetration depth that is
proportional to their kinetic energy.
Fabrication of nMOS
Metal
Insulating oxide
Thin oxide (SiO2)
k n+ n+ Silicon Dioxide (SiO2)
Si- substrate

Metal Contacts
Insulating oxide
l Thin oxide (SiO2)
n+ n+ Silicon Dioxide (SiO2)
Si- substrate
 Device Isolation Techniques
• MOS transistors must be electrically isolated from each other in
order to:
➢prevent unwanted conduction paths between devices
➢avoid creation of inversion layers outside the channel
regions
➢reduce the leakage currents
• Each device is created in dedicated regions - active areas

• Each active area is surrounded by a field oxide barrier using few

techniques:
i.) Etched field-oxide isolation
ii.) LOCOS (Local Oxidation of Silicon)
 Device Isolation Techniques
Etched field-oxide isolation

1) Grow a field oxide over the entire surface of the chip

2) Pattern the oxide and define active areas
Drawbacks:
• large oxide steps at the boundaries between active areas and field regions.
• cracking of polysilicon/metal and subsequent deposited layers

❑To prevent this, most manufacturers prefer isolation techniques that partially recess the
field oxide into the silicon surface.
 Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)
• Process flow
1) Grow a thin pad oxide (SiO2) on the silicon surface.
Thin pad oxide - protect the silicon surface from stress caused by nitride
2) Define active area : deposition and patterning a silicon nitride (Si3N4) layer
 Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)
3) Channel stop implant: p-type regions that surround the transistors
 To prevent the formation of any unwanted channels between two neighboring N+
diffusion regions.

4) Grow a thick field oxide

•Field oxide is partially recessed into the surface (oxidation consume some
of the silicon)
 Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)

•Field oxides forms a lateral extension under the nitride layer – bird’s beak region. Responsible for reduction
in active areas.
• Bird’s beak region limits device scaling and device density in VLSI circuits!

5) Etch the nitride layer and the thin oxide pad layer
 CMOS Fabrication Process

• CMOS fabrication technology requires that both n-

channel (nMOS) and p-channel (pMOS) transistors be VDD
built on the same chip substrate.
• To accommodate both nMOS and pMOS devices, special
A Y
regions must be created in which the semiconductor type
is opposite to the substrate type. These regions are called
wells of tubs. GND
• A p-well is created in an n-type substrate or, alternatively , CMOS Inverter
an n-well is created in a p-type substrate.
CMOS Fabrication Process
 CMOS
Fabrication
Process
 CMOS
Fabrication
Process
 CMOS
Fabrication
Process
 Layout Design Rules
• Layout or Design Rules
• Design rules specify geometric constraints on the layout artwork.
• Specify minimum allowable line widths.
• Provide a communication channel between the IC designer and the fabrication process engineer.

• Objective
• To obtain a circuit with optimum yield.
• To minimize the area of the circuit.
• To provide long term reliability of the circuit.

• Two approaches for describing design rules

• Lambda rule
• Micron Rule
 Lambda rule

• Every distance in layout rules is specified by lambda

• Given a process, lambda is set to a specific value.
• Process technology is defined using minimum line width. 0.25um technology means
minimum line width is 0.25um.
• Lambda=minimum line width/2.
• For a 0.25um process, lambda=0.125um
• In practice, scaling is often not linear.
• Industry usually uses micron rule and lambda rule is used only for prediction/estimation of
the impact of technology scaling to a design.
Layout Design Rules
 Micron Rule
• Minimum feature sizes and spacing in micro meter units (normal spec in
industry)

• Micron rules can result in as much as a 50% size reduction over lambda
rules.
• Normal style for industry.
• Pro: Allow taking full advantage of technology
• Con: Scaling and Porting becomes more complicated
 Design Rule Entities
1. Layer Representations
– Substrates and/or Wells
– Diffusion Regions (Active areas)
• Select regions: For contacts to substrate or well
– Polysilicon Layers
– Metal Interconnects
• Contact: Metal to active
• Via: Metal to metal
2. Intralayer Constraints
3. Interlayer Constraints
MOSIS (MOS Implementation System)
Layout Design Rules
MOSIS (MOS Implementation System) Layout Design Rules

Rule Number Description λ Rule

Active Area rules
R1 Minimum active area width 3λ

R2 Minimum active area spacing 3λ

Polysilicon Rules
R3 Minimum poly width 2λ
R4 Minimum poly spacing 2λ
R5 Minimum gate extension of poly over active 2λ

R6 Minimum poly active edge spacing (poly 1λ

outside active area)

R7 Minimum poly active edge spacing (poly inside 3λ

active area)
MOSIS (MOS Implementation System) Layout Design Rules

Rule Number Description λ Rule

Metal Rules
R8 Minimum metal width 3λ
R9 Minimum metal spacing 3λ
Contact Rules
R10 Poly contact size 2λ
R11 Minimum poly contact spacing 2λ
R12 Minimum poly contact to poly edge spacing 1λ
R13 Minimum poly contact to metal edge spacing 1λ
R14 Minimum poly contact to active edge spacing 3λ
MOSIS (MOS Implementation System) Layout Design Rules

Rule Number Description λ Rule

R15 Active contact size 2λ
R16 Minimum active contact spacing (on the 2λ
same active region)
R17 Minimum active contact to active edge 1λ
spacing
R18 Minimum active contact to metal edge 1λ
spacing
R19 Minimum active contact to poly edge 3λ
spacing
R20 Minimum active contact spacing (on 6λ
different active region)
 Layout rules for a minimum size MOSFET
(CMOS Inverter Layout Design)

Minimum overall length of active area = (minimum polysilicon width) + 2 x (minimum

poly to contact spacing) + 2 x (minimum contact size) + 2 x (minimum spacing from
contact to active area edge)
Separation between nMOS and pMOS transistor of
CMOS inverter
Complete mask layout of the CMOS inverter

VDD

A Y

GND
The Metal Oxide Semiconductor (MOS)
structure

The structure consists of three layer:

1.The metal gate electrode
2.The insulating oxide (SiO2) layer
3.The p-type bulk semiconductor

At, T= 300K,
ni = 1.45 X 10^10 cm-3
Acceptor concentration (Boron) NA = 10^15 to 10^16 cm-3
The Metal Oxide Semiconductor (MOS)
structure

ACCUMULATION
[Vg<0]

DEPLETION
[Vg>0] Slightly Positive

INVERSION
[Vg>Vt]
Energy band diagram of MOS structure
 Terminal Voltages

• Mode of operation depends on Vg, Vd, Vs

• Vgs = Vg – Vs
• Vgd = Vg – Vd
• Vds = Vd – Vs = Vgs - Vgd
Vg
• Source and drain are symmetric diffusion terminals
+
• By convention, source terminal at lower voltage +
Vgs Vgd

• Hence Vds  0 - -
Vs Vd
• nMOS body is grounded. First, assume that source is 0 too. -
Vds +

• Three regions of operation

• Cutoff
• Linear
• Saturation
 The MOS System under External Bias -ACCUMULATION

•A negative voltage VG is applied to the gate electrode.

–The holes in the p-type substrate are attracted to the semiconductor-oxide surface
–The majority carrier concentration > the equilibrium hole concentration

•The electron concentration (minority carrier) decreases as the negatively charged electrons are pushed deeper
into the substrate
–The oxide electric field is directed toward the gate electrode
– Negative surface potential causes the energy bands to bend up-ward near the surface
 The MOS System under External Bias –DEPLETION

•A small positive gate bias VG is applied to the gate electrode

–The oxide electric field will be directed towards the substrate
–Causing the energy bands to bend downward near the surface
–The majority carrier (hole) will be repelled backed into the substrate

•Leaving negatively charged fixed acceptor ions behind (depletion region)

 The MOS System under External Bias –INVERSION

* A further increase in the positive gate bias–

- Increasing surface potential -> the downward bending of the energy bands will increase
- The mid-gap energy level Ei becomes smaller than the Fermi level Efp on the surface
• The substrate semiconductor in this region become n-type
• The electron density is larger than the majority hole density
• Inversion layer, surface inversion
• Can be utilized for conducting current between two terminal of the MOS transistor
– The surface is said to be inverted if
• The density of mobile electrons on the surface becomes equal to the density of holes in the bulk substrate
• Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi potential φF
• Further increase gate voltage -> electron concentration↑ but not to an increase of the depletion depth
Depth of the depletion region
 charge in a thin horizontal layer parallel to the surface
change in surface potential required to displace the charge
sheet dQ by a distance xd

 integrating along vertical direction yields

 thus the depth of the depletion region

 depletion region charge density (fixed acceptor ions)

The physical structure of a n-channel enhancement-
type MOSFET
•MOS structure
–polysilicongate, thin oxide layer, semiconductor
•Source, drain n+-region
– The current conducting terminals of the device
•Conducting channel, channel length L, channel
width W
– The device structure is completely symmetrical with
respect to the drain and source
– The thickness of oxide layer covering the channel
region is given by tox.
•The simple operation of this device
–Controlling the current conduction between the source
and the drain, using the electric field generated by the
gate voltage as a control variable
 Formation of a depletion region

• For small gate voltage level

–The majority of carriers (holes) are repelled back into the substrate
–The surface of the p-type substrate is depleted
–Current conduction between S and D is not possible
 Formation of an inversion layer

•As the gate-to-source voltage is further increased

–The surface potential reaches –φFp -> surface inversion will be established -> conducting channel between S and D –>
Allowing current flow, as long as there is a potential difference between S and D
• VGS<VT0(threshold voltage)
– Not sufficient to establish an inversion layer
– No current between S and D
• VGS>VT0(threshold voltage)
– Electrons are attracted to the surface
– Contributing to channel current conduction
• Further increase in gate voltage
– Doesn’t affect the surface potential and the depletion region depth.
 Depletion type and Enhancement type MOSFET

• Enhancement type MOSFET: MOS transistor which has no

conducting channel region at zero gate bias.
• Depletion type MOSFET: Conducting channel already exist at
zero gate bias.
• N-Channel MOSFET: In a MOSFET with P type substrate and
with n+ source and drain regions, the channel region to be formed
is N type.
• P-Channel MOSFET: In a MOSFET with N type substrate and
with p+ source and drain regions, the channel region to be formed
is P type.
 Circuit symbols for enhancement-type MOSFET

• The abbreviations used for device terminals are

G for the gate, D for the drain, S for the source, and B for the substrate
• The small arrow always marks the source terminal
 Circuit symbols for n-channel depletion-type MOSFETs

•Using selective ion implantation into the channel

–The threshold voltage for MOSFET can be adjusted.
– N channel MOSFET:
• threshold voltage increases (made more positive) by adding extra p-type impurities (acceptor ions)
• threshold voltage decreases (made more negative) by adding extra n-type impurities (donor ions)
– Resulting nMOS transistor will have a conducting channel at VGS=0 enabling current flow between
source and drain as long as Vgs > -ve threshold voltage
– Such a device is called a DEPLETION type (or normally on) n channel MOSFET.
 MOSFET operation: linear region
•The MOSFET consists
–A MOS capacitor, two pn junction adjacent to the channel
–The channel is controlled by the MOS gate
•The carrier (electron in nMOSFET)
–Entering through source, controlling by gate, leaving through drain
•To ensure that both p-n junctions are reverse-biased initially
–The substrate potential is kept lower than the other three terminal potentials
•When 0<VGS<VT0
–G-S region depleted, G-D region depleted
–No current flow

•When VGS>VT0
–Conduction channel formed
–Capable of carrying the drain current
–As VDS=0
•ID=0
–As VDS>0 and small
•ID proportional to VDS
•Flowing from S to D through the conducting channel
•The channel act as a voltage controlled resistor
•The electron velocity much lower than the drift velocity limit
•As VDS↑ the inversion layer charge and the channel depth at the drain end start to decrease
MOSFET operation: Saturation region
•For VDS=VDSAT
–The inversion charge at the drain is reduced to zero
–Pinch off point
•For VDS>VDSAT
–A depleted surface region forms adjacent to the drain
–As VDS is further increased, the depletion region grows
toward the source
–The channel-end remains essentially constant and equal to
VDSAT
–The pinch-off (depleted) section
•Absorbing most of the excess voltage drop, (VDS-VDSAT)
•A high-field forms between the channel-end of the drain
boundary–Accelerating electrons, usually reaching the drift
velocity limit
 Threshold Voltage

Four physical components of Vto:

1. The work function difference between gate and

channel
2. The gate voltage component to offset the
Qb 0 Qox
depletion region charge Vto =  gc − 2 f − −
3. The gate voltage component to change the surface Cox Cox
potential
4. The voltage component to offset the fixed charge
in the gate oxide and in the silicon oxide
interface.
 Threshold Voltage
KT ni
f = ln( ) Fermi potential for a p-type semiconductor
q NA
KT Nd
f = ln( ) Fermi potential for a n-type semiconductor
q ni

gc =  f (substrate) −  ( gate)

- The substrate Fermi potential
φF is negative in NMOS, positive

(
Qb 0 = − 2.q.N A . si . − 2 f ( substrate) ) in pMOS
–The depletion region charge
densities QB0 and QB are
negative in nMOS, positive in
 ox pMOS
Cox = Qox = q.N ox
tox
Energy band diagram of a p-type silicon substrate

K -> Boltzman Constant = 1.38 x 10^-23 J/K

q -> charge of electron = 1.6x 10^-19 C

Fermi potential for N type material is +ve

Fermi potential for P type material is –ve

qx -> electron affinity -> potential diff between

conduction band level and vaccum level
 Threshold Voltage Question

Q.1 Calculate the threshold voltage VTO at VSB = 0, for a n channel MOS transistor, with the following parameters: Substrate
doping density NA =10^16 cm-3, polysilicon gate density
ND =2 x 10^20 cm-3, gate oxide thickness tox=500 Angstrom and oxide interface fixed charge density Nox= 4 x 10^10 cm-2,
φF( gate) = 0.55V. q= 1.602x10^-19 coulombs, K= 1.381x10^-23 J/K, T= 300 K
Physical constants :
Thermal voltage =KT/q = 0.026 volt
Energy Gap of silicon(Si) =Eg = 1.12 eV
Intrinsic Carrier Concentration of silicon = ni =1.45 x 10^10 cm –3
Dielectric constant of vacuum = εo =8.85 x 10-14 F/cm
Dielectric constant of silicon = εsi = 11.7 x εo F/cm
Dielectric constant of silicon dioxide = εox = 3.97 x εo F/cm
Ans: φF( sub) = -.35v ,
φGC = -.90 v,
Qbo = -4.82x10^-8 C/cm^2,
Qox = 6.4 x 10^-9 C/cm^2 ,
Cox = 7.03x10^-8 F/cm^2,
Vto =0.40v
 Threshold Voltage Question

Q.2 Calculate the threshold voltage VTO at VSB = 0, for a polysilicon gate p channel MOS transistor, with the following
parameters: Substrate doping density ND =10^15 cm-3, polysilicon gate density
ND =10^20 cm-3, gate oxide thickness tox=500 Angstrom = 500x10^-8 cm and oxide interface fixed charge density Nox= 2
x 10^10 cm-2, φF( gate) = 0.55V.
Physical constants :
Thermal voltage =KT/q = 0.026 volt
Energy Gap of silicon(Si) =Eg = 1.12 eV
Intrinsic Carrier Concentration of silicon = ni =1.45 x 10^10 cm –3
Dielectric constant of vacuum = εo =8.85 x 10-14 F/cm
Dielectric constant of silicon = εsi = 11.7 x εo F/cm
Dielectric constant of silicon dioxide = εox = 3.97 x εo F/cm

[ans: φF( sub) = .290v , φGC = -.26 v, Qbo = 1.38X10^-8 C/cm^2, Qox = 3.2 x 10^-9 C/cm^2 , Cox = 7.03x10^-8 F/cm^2, Vto = -
1.1v ]
 I-V Characteristics
• In Linear region, Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?
 Channel Charge
• MOS structure looks like a parallel plate capacitor while operating in
inversions
• Gate – oxide – channel
• Qchannel = CV
• C = Cg = eoxWL/tox = CoxWL
• V = Vgc – Vt = (Vgs – Vds/2) – Vt +
gate
Vg
+
source Vgs Cg Vgd drain
Vs - - Vd
channel
n+ - + n+
Vds
polysilicon
gate p-type body
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body
 Carrier velocity
• Charge is carried by e-
• Electrons are propelled by the lateral electric field between source and drain
• E = Vds/L
• Carrier velocity v proportional to lateral E-field
• v = mE m called mobility
• Time for carrier to cross channel:
• t=L/v
 nMOS Linear I-V
• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross
Qchannel
I ds =
t
= Cox
W V − V − Vds V
 gs t  ds
L 2 
=  Vgs − Vt − ds Vds
V
 2
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
• When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current

I ds =  Vgs − Vt − dsat V
V
 dsat
 2 

( − Vt )
2
= Vgs
2
 nMOS I-V Summary

• Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  V V V  V
I ds =   Vgs − Vt − ds  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2
Summary of the Current-voltage equation of n-, p-channel
MOSFET
 MOSFET current-voltage characteristics-gradual channel
approximation (GCA)(1)

•Considering linear mode operation

VS=VB=0, the VGS, and VDS are the external parameters controlling the drain current ID
VGS> VT0 (assume constant through the channel)to create a conducting inversion layer
–Defining
•X-direction: perpendicular to the surface, pointing down into the substrate
•Y-direction: parallel to the surface
–The y=0 is at the source end of the channel
–Channel voltage with respect to the source, Vc(y)
–Assume the electric field Ey is dominant compared with Ex
•This assumption reduced -> the current flow in the channel to the y-direction only
–Let QI(y) be the total mobile electron charge in the surface inversion layer,
We know that Q=CV,

QI(y)=-Cox[VGS-Vc(y)-VT0]
=>
 MOSFET Current-voltage Characteristics-gradual Channel Approximation (GCA)(2)

• Assuming that all mobile electrons in the inversion layer have a constant surface mobility μn.

(minus sign is due to negative polarity of the inversion layer charge QI)

The electron surface mobility μn depends on the doping concentration of the channel region, and its magnitude is typically about one-
half of that of the bulk electron mobility.
 MOSFET current-voltage characteristics-gradual channel
approximation (GCA)-saturation region
• 65 nm IBM process, VDD = 1.0 V
Ids (A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1
 Channel length modulation

• Reverse-biased p-n junctions form a depletion region

• Region between n and p with no carriers
• Width of depletion Ld region grows with reverse bias
• Leff = L – Ld GND V V
DD DD
Source Gate Drain
• Shorter Leff gives more current Depletion Region
Width: Ld
• Ids increases with Vds
• Even in saturation n L n
+ Leff +
p GND bulk Si
 Channel length modulation


( − Vt ) (1 + Vds )
2
I ds = V gs GND VDD VDD
2 Source Gate Drain
Depletion Region
Width: Ld

•  = channel length modulation coefficient n

+
L
Leff
n
+
• not feature size p GND bulk Si

• Empirically fit to I-V characteristics

 Non-Ideal IV Characteristics

❖ Non-ideal Transistor Behavior

- High Field Effects
• Mobility Degradation
- Threshold Voltage Effects
• Body Effect
- Short Channel Effect
- Threshold Voltage Reduction
- Drain-Induced Barrier Lowering (DIBL)
- Velocity Saturation
 High field Effects- Mobility Degradation
Mobility degradation refers to the reduction in carrier mobility (i.e., the speed at which electrons can move
through the channel) as the electric field in the channel increases. This phenomenon occurs primarily due to:

High Vertical Electric Field: The strong vertical electric field (between the gate and the channel) can cause
carriers to be more tightly bound to the surface, which increases scattering and reduces mobility. This effect is
more pronounced at higher gate voltages and in short-channel devices where the electric field is particularly
intense.
 Threshold Voltage Effects

• Vt is Vgs for which the channel starts to invert

• Ideal models assumed Vt is constant
• Really depends (weakly) on almost everything else:
• Body voltage: Body Effect
• Drain voltage
• Channel length
 Body Effect
• Body is a fourth transistor terminal
• Vsb affects the charge required to invert the channel
• Increasing Vs or decreasing Vb increases Vt
Vt = Vt 0 +  ( s + Vsb − s )
• fs = surface potential at threshold
NA
s = 2vT ln
ni
• Depends on doping level NA
• And intrinsic carrier concentration ni
• g = body effect coefficient
tox 2q si N A
 = 2q si N A =
 ox Cox
 Body Effect Cont.

• For small source-to-body voltage, treat as linear

 Short Channel Effect
• When the channel length (the distance between the source and drain) becomes
comparable to the depletion region widths of the source and drain junctions.
As MOSFETs are scaled down in size for higher performance and density in
integrated circuits, these effects become increasingly significant.
• In small transistors, source/drain depletion regions extend into the channel
• Impacts the amount of charge required to invert the channel
• And thus makes Vt a function of channel length
• Short channel effect: Vt increases with L
• Some processes exhibit a reverse short channel effect in which Vt decreases
with L
 Velocity Saturation
Velocity saturation occurs when the carriers (electrons in the case of an NMOS) reach a maximum velocity as they
travel through the channel, beyond which increasing the electric field no longer increases their speed.
Velocity Saturation
In an ideal MOSFET, the drain current (ID ) increases linearly with the drain-source voltage (VDS​) in the linear
(ohmic) region, and it increases quadratically with the gate-source voltage (VGS​) in the saturation region. This is
based on the assumption that the carriers can continue to accelerate indefinitely as the electric field increases.
However, in reality, this is not the case.
At very high electric fields, the carriers reach a maximum velocity known as the saturation velocity. When this
velocity is reached, further increases in the electric field do not result in an increase in carrier speed, and the drain
current saturates earlier than it would in the absence of velocity saturation.

Vd​=μ⋅E
The drift velocity eventually saturates at Vsat​, and this behavior can be represented as:
vd≈vsat when E is high
 DIBL
• Electric field from drain affects channel
• More pronounced in small transistors where the drain is closer to the channel
• Drain-Induced Barrier Lowering
• Drain voltage also affect Vt
ttds VVV=−

Vt = Vt − Vds
• High drain voltage causes current to increase.
MOSFET scaling and small-geometry effects
Full scaling (constant-field scaling)
Constant-voltage scaling
Full Scaling Constant Voltage Scaling
Substrate bias effect
Oxide related capacitance(1)
Oxide related capacitance(1)
Oxide related capacitance(2)
MOS INVERTERS: STATIC CHARACTERISTICS
ACTUAL INVERTER VOLTAGE TRANSFER CHARTERISTIC
(VTC)
NOISE IMMUNITY AND NOISE MARGINS
NOISE IMMUNITY AND NOISE MARGINS
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
POWER DISSIPATION- RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
RESISTIVE-LOAD INVERTER
DEPLETION-LOAD NMOS INVERTER

SELF Study
Refer to Digital Integrated Circuit
Sung Mo Kang Book
 CMOS INVERTER

• Complementary NMOS and PMOS devices Vcc

• In steady-state, only one device is on (no static

power consumption) Load: PMOS

• Vin=1: NMOS on, PMOS off Vin Vout

• Vout = VOL = 0 Driver: PMOS
• Vin=0: PMOS on, NMOS off
• Vout = VOH = Vcc
• Ideal VOL and VOH! Gnd
 CMOS INVERTER OPERATION

• NMOS transistor:
• Cutoff if Vin < VTN
Load: PMOS
• Linear if Vout < Vin – VTN
• Saturated if Vout > Vin – VTN Vin Vout
Driver: PMOS
• PMOS transistor
• Cutoff if (Vin-VCC) < VTP → Vin < Vcc+VTP
• Linear if (Vout-VCC)>Vin-Vcc-VTP → Vout>Vin - VTP
• Sat. if (Vout-VCC)<Vin-Vcc-VTP → Vout < Vin-VTP
 CMOS INVERTER
Vto , n = + ve
Vgs , n = Vin

- VDD - Vds , n = Vout

Vto , p = −ve
Vgs , p = −(VDD − Vin )
Id,p + Vds , p = −(VDD − Vout )
+ Vout
Id,n
Vin
- -
Region Vin Vout nMOS pMOS
A <Vto,n VOH
B VIL High ≈ VOH
Gnd
C Vth Vth
D VIH Low≈ VOL
E >(VDD+Vto,p) VOL
 CMOS INVERTER
Vto , n = + ve
Vgs , n = Vin

- VDD - Vds , n = Vout

Vto , p = −ve
Vgs , p = −(VDD − Vin )
Id,p + Vds , p = −(VDD − Vout )
+ Vout
Id,n
Vin
- -
Region Vin Vout nMOS pMOS
A <Vto,n VOH Cut off Linear
B VIL High ≈ VOH Saturation Linear
Gnd
C Vth Vth Saturation Saturation
D VIH Low≈ VOL Linear Saturation
E >(VDD+Vto,p) VOL Linear Cutoff
CMOS INVERTER VTC
 CMOS INVERTER VTC VIL

• KCL: kn
2
2

2

(VGS ,n − VT 0,n ) = 2(VGS , p − VT 0, p )VDS , p − VDS , p 2
kp

kn
2
k
2

(Vin − VT 0,n )2 = p 2(Vin − VCC − VT 0, p )(Vout − VCC ) − (Vout − VCC )2 
• Differentiate and set dVout/dVin to –1
 dV 
kn (Vin − VT 0,n ) = k p (Vin − VCC − VT 0, p ) out + (Vout − VCC ) − (Vout − VCC ) out 
dV
 dVin dVin 
kn (VIL − VT 0,n ) = k p (2Vout − VIL + VT 0, p − VCC )

2Vout + VT 0, p − VCC + k RVT 0,n kn

VIL = kR =
1 + kR kp
• Solve simultaneously with KCL to find VIL
 CMOS INVERTER VTC VIH

• KCL: kn
2

2(VGS ,n − VT 0,n )VDS ,n − VDS ,n =
2 kp
2
(VGS , p − VT 0, p )2
kn
2

2(Vin − VT 0,n )Vout − Vout =
2 kp
2
(Vin − VCC − VT 0, p )2
• Differentiate and set dVout/dVin to –1
 dVout 
k n (Vin − VT 0,n ) out + Vout − Vout = k p (Vin − VCC − VT 0, p )
dV

 dVin dVin 
kn (2Vout − VIH + VT 0, p ) = k p (VIH − VCC − VT 0, p )

VCC + VT 0 , p + k R (2Vout + VT 0 ,n ) kn
VIH = kR =
1 + kR kp
• Solve simultaneously with KCL to find VIH
 CMOS INVERTER VTC VTH

(VGS ,n − VT 0,n ) = (VGS , p − VT 0, p )2

kp
• KCL: kn 2

2 2

(Vin − VT 0,n ) = (Vin − VCC − VT 0, p )2

kn 2 kp
2 2
• Solve for VTH = Vin = Vout

VT 0,n +
1
(VCC + VT 0, p ) kn
kR
VTH = kR =
1 kp
1+
kR
 CMOS INVERTER VTC

VT 0,n +
1
(VCC + VT 0, p )
kR kn
VTH = kR =
1 kp
1+
kR
• Ideally, VTH = VCC/2  VCC 2 + VT 0, p 
2

k R ,ideal =  

 VCC 2 + VT 0,n 
• Assuming VT0,n = VT0,p, k R,ideal = 1

W 
 
 L  p n
=  2.5
 
W p
 
 L n
CMOS INVERTER
 NMOS LOAD INVERTER

NMOS passes weak logic ‘1’ and Strong logic ‘0’

Apart from the power dissipation, the other issue with the NMOS transistor is that, it passes weak logic ‘1’.
NMOS LOAD INVERTER
When the input to the inverter is logic ‘0’, then output of
the inverter should be high and ideally, it should be equal
to VDD. But actually, here the output will not go beyond
VDD – VT.
Because, if output of the inverter goes to 5V, then the
source terminal of the upper NMOS transistor will be at
5V and therefore, VGS will become 0V.
Now, for MOSFET to be in ON condition, VGS should be
more than VT. That means in this case, the voltage at the
source terminal of the upper MOSFET won’t go beyond
VDD – VT.
Otherwise, the upper NMOS transistor will become OFF.
So, for example, if threshold voltage of NMOS is 0.5V
and supply voltage is 5V then output will not go beyond
4.5 V.
That means we will not get full voltage swing. Or in other
words, NMOS is weak to pass logic ‘1’.
NMOS LOAD INVERTER

if the input to the inverter is logic ‘1’ then NMOS will be

in the ON condition and since source is connected to the
ground, it will pull down the voltage of the drain terminal
to 0V.
That means NMOS passes weak logic ‘1’ but it passes
logic ‘0’. And it can be used in the pull-down network to
pull down the voltage of specific node to 0V.
 PMOS
PMOS passes strong logic ‘1’ and weak logic ‘0’

When input to PMOS is 0V then V is more

SG

than V and PMOS will act as a closed switch.

T

So, capacitor at the drain terminal will start

charging towards 5V and eventually the
voltage at the drain terminal will be equal to
5V.
So, when we want to pull-up the voltage at the
drain terminal to the supply voltage, then we
can use the PMOS transistors.
• Now the drain terminal is connected to ground and capacitor is connected at the source terminal.
• Let’s assume that, initially, the voltage across the capacitor is 3V.
So, now when VG = 0V, then VSG is more than VT, and because of that, PMOS will conduct and it will try to bring down
the voltage of the source terminal to 0V. So, capacitor will start discharging.
• As soon as the voltage at the source terminal reaches threshold voltage, then MOSFET will be turned off. Because
now VSG = VT.
• That means the voltage at the source terminal cannot go below threshold voltage.
So, for example, if the threshold voltage of the MOSFET is 0.5V then the voltage at the source terminal will not go
below 0.5V. That means PMOS is weak to pass logic ‘0’.
That is why it not preferable to use the PMOS transistor in the pull-down network. But it can be used in the pull-up
network where we want to pull up the voltage of the specific node.
 CMOS INVERTER

• In the CMOS network both PMOS and NMOS transistors are used.

• The PMOS is used as a pull up network (PUN) and NMOS transistors are used in the pull-down network
(PDN).
 CMOS LOGIC CIRCUITS

2 PMOS are serially connected 2 PMOS are Parallelly connected

2 NMOS are Parallelly connected 2 PMOS are serially connected

CMOS Two input NOR Gate CMOS Two input NAND Gate
 Complex LOGIC Gates

Complex CMOS logic gate Full-CMOS implementation of the

realizing the Boolean function XOR function.
 Exercise
Find an equivalent CMOS inverter circuit for simultaneous switching of all inputs, assuming that (W/L)p = 15 for all
pMOS transistors and (W/L) = 10 for all nMOS transistors.

The equivalent (W/L) ratios of the nMOS network and the pMOS network are
determined by using the series-parallel equivalency rules
 CMOS Pass Gates

Four different representations of the

CMOS transmission gate (TG).

Bias conditions and operating regions of

the CMOS transmission gate, shown as
functions of the output voltage.