IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO.

10, OCTOBER 2018 2763

A 0.5-V 12-bit SAR ADC Using Adaptive

Time-Domain Comparator With
Noise Optimization
Sung-En Hsieh , Chen-Che Kao, and Chih-Cheng Hsieh

Abstract— This paper presents a 0.5-V 12-bit low-voltage

power-efficient successive-approximation register (SAR) analog-
to-digital converter (ADC) using an adaptive time-domain (ATD)
comparator with noise optimization. To be power efficient with
different residual input levels (Vin ) during conversion, the pro-
posed ATD comparator automatically adjusts its input-referred
noise performance rather than consuming the same power
for each bit conversion. Considering the noise requirement of
12-bit resolution, the proposed ATD technique effectively reduces
the comparator power consumption by 50% compared to the
conventional approach. Moreover, a differential threshold win-
dow (DTW) technique is also developed to provide the optimized
time-domain threshold for lowest figure-of-merit (FoM) perfor-
mance with a self-adjusted (Vctrlp –Vctrln ), depending on process–
voltage–temperature (PVT) variation. The test chip occupies a
core area of 0.109 mm2 in Taiwan Semiconductor Manufacturing
Company (TSMC) 90-nm CMOS technology. With a 0.5-V supply Fig. 1. Comparison of different SAR ADCs.
voltage, the prototype consumes 810 and 1425 nW at 100 and
250 kS/s, respectively. The achieved effective number of bits including an analog-to-digital converter (ADC). However, with
and signal-to-noise and distortion ratio with Nyquist-rate input densely existing sensing nodes of an IoE network, frequent
are 10.71/10.3 bit and 66.3/63.8 dB, respectively. The resultant and manual replacement of batteries is inevitable if the power
Walden FoM and Schreier FoM are 4.82/4.52 fJ/conversion step
and 174.2/173.23 dB, respectively. consumption issue is not appropriately addressed. For this
reason, IoE devices with an efficient and low-power ADC as a
Index Terms— Adaptive time-domain (ATD) comparator, low key block are highly attractive. From technological evolution,
noise, low power, successive-approximation register (SAR)
analog-to-digital converter (ADC). the digital power consumption of ADCs has decreased dramat-
ically. However, the power consumption of capacitor arrays
I. I NTRODUCTION and comparators in ADCs has increased dramatically with the
increased resolution due to the kT/C noise requirements and
T HE Internet-of-Everything (IoE) is a network of smart
devices for applications ranging from smart grids, virtual
power plants, smart homes, intelligent transportation, and
decreased VLSB . Therefore, the most challenging design issue
of low-voltage, high-resolution ADCs is the noise suppression
smart cities. The economic benefits of the IoE have possible and power reduction of comparators and capacitor arrays.
applications far beyond portable devices, medical devices, and Successive-approximation register (SAR) ADCs [1]–[9] have
autonomous wireless sensor nodes with advanced data centers. demonstrated good power efficiency in the resolution range
The time-space context instead of specifications of ubiquitous of 8–12 bits by introducing efficient techniques for the reduc-
sensing circuits provides the efficient and complete functions tion of digital-to-analog convertor (DAC) switching energy and
of IoE. Therefore, only kilohertz sampling rates and about comparator noise, as shown in Fig. (1).
12 bit of resolution are often required for each sub-circuit, In terms of DAC switching energy reduction by using
the top-plate sampling, the monotonic switching (MS) pro-
Manuscript received February 9, 2018; revised April 17, 2018 and cedure [2] omitted the trial-and-error switching for MSB
June 22, 2018; accepted July 24, 2018. Date of publication August 27, 2018; conversion and reduced the switching energy with the penalty
date of current version September 21, 2018. This paper was approved by
Guest Editor Seung-Tak Ryu. This work was supported by National Science of a common mode voltage shift. By using the operations
Council, Taiwan, under Contract MOST 104-2221-E-007-103-MY3, Contract of merge and split (MAS) [3] and charge-averaging switch-
106-2221-E-007-119, and Contract 106-2622-8-007-014-TA. (Corresponding ing (CAS) [4], the DAC switching energy was further reduced
author: Chih-Cheng Hsieh.)
The authors are with the Department of Electrical Engineering, with fixed common-mode voltage during conversion and
National Tsing Hua University, Hsinchu 31003, Taiwan (e-mail: required reset energy. The Vcm -based switching procedure
[email protected]). merged-capacitor switching (MCS) [5], [6] achieved the ultra-
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. low switching energy without the reset energy at the expense
Digital Object Identifier 10.1109/JSSC.2018.2862880 of additional reference voltage (Vcm ).
0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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2764 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 10, OCTOBER 2018

Fig. 2. Architecture of the proposed SAR ADC.

Considering the power consumption of the comparator for a is developed to set the optimized time-domain threshold of
high-resolution ADC, the insertion of additional loading (C) is the ATD comparator for noise-and-power tradeoff optimiza-
widely adopted to suppress the input-referred noise by half at tion with a self-adjusted (Vctrlp − Vctrln ) depending on PVT
the expense of quadruple power consumption and comparison variation. An improved MCS scheme is also employed to
time. The bidirectional comparator [7] and cascade-input com- reduce the DAC switching energy without using additional
parator [8] were reported to avoid the dilemma of power and reference voltage. Overall, the proposed SAR ADC with the
noise. Nevertheless, in the conversion procedure of an SAR ATD comparator and the improved-MCS DAC provide a
ADC, only one to two times of critical decisions require a low-noise low-power solution without the needs of complex
low-noise comparison. Two-step architecture [9] was proposed redundancy design, coarse-fine operation, critical decision
to reduce the power consumption of non-critical comparisons detection, and additional reference voltage. The implemented
at the coarse conversion phase, combined with a high-power prototype achieves a figure-of-merit (FoM) performance of
and a low-noise fine ADC. However, a complex calibration 4.82 fJ/conversion step, which is low for ADCs of over
circuit and a global control circuit are required. Moreover, 10.5 bit.
in high-resolution ADC implementation, it is difficult to imple- The rest of this paper is organized as follows. Section II
ment a reasonable redundancy range for the noise tolerance of describes the architecture of the proposed design. Section III
the coarse conversion. The majority voting technique [10] used presents the detailed circuit implementation. Section IV
multiple comparisons at critical decisions to suppress the noise shows the measurement result, and Section V provides the
without two-step operation, which has an additional complex conclusion.
critical decision detection circuit. Furthermore, the inherent
noise of the critical decision circuit may cause fault detection II. ADC A RCHITECTURE
when the input level is small. There are only two modes Fig. 2 shows the proposed SAR ADC with the ATD
of noise performance with 1× or 5× voting which are not comparator, sample and hold (S and H), improved-MCS DAC,
completely adaptive to the input voltage level. The oscil- and asynchronous SAR logic. The improved-MCS DAC is
lation collapse comparator [11] was proposed to adaptively implemented with an 11-bit capacitor array using a unit
change its noise performance with different input levels by capacitance of 1.5 fF, which results in a kT/C noise of 0.3 LSB.
the latch-up of the closed-loop voltage-controlled delay line The double-boosted S and H [4] and local-boosted [4] switch-
(VCDL). However, the oscillation is ended with the ratio ing are implemented for leakage and linearity control in
of oscillation period and voltage-to-time gain of the delay low-voltage operation. To reduce the digital power consump-
element (DE), which is a process–voltage–temperature (PVT) tion, the asynchronous logic is implemented by dynamic shift
sensitive operation. registers with minimized transistor count.
By using the VCDL with positive feedback and a phase
detector (PD), this paper proposes an adaptive time-domain A. Improved MCS for DAC Switching
(ATD) comparator with adaptive oscillation circuit (AOC) [12] The concept of the conventional MCS procedure [5], [6]
that adjusts the noise performance by automatically enabling is adopted to reduce the switching energy consumption of
the oscillation loop of the VCDL, based on the interme- the DAC. To avoid the additional reference voltage Vcm
diate residual input level of the comparator during conver- requirement of MCS, we implement an improved MCS
sion. The differential threshold window (DTW) technique scheme by merging the bottom plates of the DAC at the

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HSIEH et al.: 0.5-V 12-bit SAR ADC USING ATD COMPARATOR 2765

Twindow, oscillation is not enabled for power reduction. For

Vip ≈ Vin with a resulting Tout < Twindow, this is detected
as a critical decision, and oscillation is adaptively enabled to
√ gain (N ∗ V 2T ) and reduce the
increase the effective VTC
input-referred noise by N .
Fig. 5 shows the timing diagrams of the AOC operation
example in the oscillation mode. In the beginning, the time-
delay difference (Tout = T ) of the VCDL_Outp and the
VCDL_Outn is smaller than Twindow, and the output of the
oscillation control OSC_EN = 1. After three oscillation cycles
of the AOC, the time-delay difference is accumulated (Tout =
3T ) and is larger than Twindow to trigger the semi-resting
Fig. 3. Proposed switching procedure. set-reset (SR) latch of PD as a polarity check and make the
control OSC_EN = 0 to stop the oscillation. In this example,
top-plate sampling phase, as shown in Fig. 3. Since the the input-referred
√ noise of the ATD comparator is adaptively
corresponding sampling capacitor arrays of Vip and Vin are reduced by 3 with a minimum number (three) of oscillations
matched, the merged voltage of the bottom plates is Vdd /2 with the corresponding VTC gain for best power efficiency.
(=Vcm ) at the sampling phase due to charge conservation. The
common-mode voltage is then generated by charge sharing and C. Input-Referred Offset of ATD Comparator
held on the DAC array during the conversion phase instead of
being supplied by an extra voltage reference. The generated Considering the input-referred offset voltage (Voffset )
Vcm is affected by the phase/amplitude mismatch of the input induced by the mismatch of VCDLs (Toffset ) as shown
signal, bottom-plate parasitic mismatch, and leakage issues in Fig. 6, the accumulated time-delay difference Tout of VCDL
during conversion. Assuming a worst-case scenario combined outputs after N cycles of oscillation is expressed as follows:
with an input signal mismatch (5%), bottom-plate parasitic Tout = N × (Vip − Vin ) × V 2T − N × Toffset
mismatch (5%), and leakage issue, the total common-mode
= N × (Vip − Vin − Toffset /V 2T ) × V 2T. (2)
shift is about 15 mV with an induced dynamic offset of
0.08 LSB, resulting in a negligible dynamic range (DR) drop By detecting Tout > Twindow or not, (2) shows the mismatch
of 0.012 dB. As a result, the proposed improved MCS scheme of VCDLs can be regarded as a fixed input-referred offset
achieves the same high energy efficiency as MCS without an voltage (Voffset ) of the ATD comparator, which is equal to
additional reference voltage (Vcm ). With the reduced bottom Toffset /V 2T and is independent of the number of cycles N.
plate voltage swing, the resulting switching energy is 170 CV2 Therefore, the top plate of the capacitor array converges to
which is 68.5%, 49.9%, and 12.48% of MS [2], CAS [4], and a fixed input-referred offset voltage Voffset (= Toffset /V 2T ) in
the conventional switching procedures, respectively. each bit conversion to compensate for the accumulated Toffset
with or without oscillation. In the HSPICE simulation with a
B. Operation of ATD Comparator Toffset of 575 ps and a V 2T gain of 33.2 ps/LSB, the resulting
offset of the overall transfer curve is 17.3 LSB (4.22 mV),
Fig. 4 shows the proposed ATD comparator that is com-
which results in a negligible signal-to-noise and distortion
posed of AOC, DTW, PD, and oscillation control unit. The
ratio (SNDR) degradation of 0.037 dB.
AOC has a VCDL, oscillation enabling gate for voltage-to-
time conversion (VTC), and VTC gain tuning. The VCDL
(DE × 7) has seven-stage cascaded DEs for optimized per- D. Design Tradeoff
formance (which is explained in detail in Section III-A). The In the conventional approach, an SAR ADC uses a low-
time-delay difference Tout of the AOC output is expressed as noise high-power comparator (or a time-domain comparator)
Tout = N × (Vip − Vin ) × V 2T (1) for every bit conversion without adaptive noise reduction.
Fig. 7 shows a simulated comparison of the conventional
where N is the number of oscillation cycles and V 2T is approach and the proposed ATD comparator for the design
the VTC gain of VCDL (DE × 7). The critical decision tradeoff of power and effective number of bits (ENOB).
detection circuit has a DTW circuit using single-stage VCDL Fig. 7(a) shows the achieved “ENOB” versus the required
(DE × 1) replicas and an additional control voltage (Vctrlp − input-referred noise (σ ) (at N = 1) for comparators
Vctrln ) that is self-adjusted, depending on PVT variation. The with (ATD) and without (conventional time-domain compara-
DTW creates a delay difference of (Vctrlp − Vctrln ) × (V 2T /7) tors) adaptive noise reduction. The ATD comparator shows a
between PD_n_D and PD_n_clk (PD_p_D and PD_p_clk) as better ENOB performance at the same input-referred noise due
a time-domain threshold window Twindow. By checking the to the noise suppression effect of enabling adaptive oscillation.
time-delay difference of the AOC output (Tout > Twindow?) in Assuming that the comparator (time domain and voltage
the conversion procedure, the oscillation is adaptively enabled, domain) consumes “one” unit of normalized power to achieve
based on the residual input level (Vip − Vin ) for noise and an input-referred noise of 1.5 LSB, the corresponding total
power optimization. When Vip  Vin with a resulting Tout  power consumption comparison of comparator with (ATD)

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2766 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 10, OCTOBER 2018

Fig. 4. Architecture of the proposed ATD comparator.

Fig. 5. Timing diagrams of the proposed AOC in oscillation mode.

Fig. 7. Behavioral simulation comparison of the conventional and ATD

Fig. 6. Equivalent model of input-referred offset voltage Voffset of ATD comparators. (a) ENOB versus noise. (b) Power versus ENOB.
comparator induced by the mismatch of VCDLs’ Toffset .

and without (conventional time-domain comparators) adaptive comparator need special design considerations as described in
noise reduction is simulated as shown in Fig. 7(b). By detect- Section III.
ing the residual input level (equivalently, the time-delay dif-
ference after the AOC) and adaptively enabling oscillation at a A. Voltage-Controlled Delay Line
critical decision, the required power of the ATD comparator is The VCDL is implemented by cascaded stages of the
reduced by a factor of about 3.2, compared to the conventional voltage-controlled DE composed of a delay cell and buffer,
approach at a target ENOB of 11 bit. as shown in Fig. 8(a). The total input-referred noise of DE is
a combination of the delay cell and output buffer. From the
III. I MPLEMENTATION OF K EY B UILDING B LOCKS HSPICE noise simulation as shown in Fig. 8(b), the finger
To operate at 0.5 V with robustness of mismatch and number (m = 4) of M1 (and M0) is chosen to efficiently get
PVT variation, the key building blocks in the proposed ATD a noise level of 5.3 LSB since the noise reduction slope is

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HSIEH et al.: 0.5-V 12-bit SAR ADC USING ATD COMPARATOR 2767

Fig. 9. MATLAB simulation of FOM and ENOB versus Twindow .

Fig. 8. (a) Voltage-controlled DE. (b) Noise simulation versus M1 (and M0)
size.
B. Differential Threshold Window
The DTW sets the minimum required time-delay difference
saturated even with a larger number of “m” due to the noise window (Twindow) of the AOC output for critical decision
contribution of the buffer. Once the sizing of DE of VCDL detection. To track the PVT-induced variation of the AOC, the
is decided, the number of cascaded units is designed based DTW is implemented using the identical DE of the AOC with
on the tradeoff of required ENOB and achieved FoM. Since a differential-ratio control voltage (Vctrlp − Vctrln ) generated
the VTC gain (V 2T ) and output-referred noise of the VCDL from an extra DAC using the same switching method as the
are proportional to the number of stages (S) and square-root main DAC. For area and power optimization, the DTW uses
of “S,” respectively, the input-referred noise Vrms can be a single DE instead of seven cascaded DEs in the AOC. The
formulated as generated Twindow is expressed in the following:
√ Twindow = (V ctrlp − Vctrln )(V 2T /7). (4)
2K T 2Idis
Vrms = √ × (3)
S × C L V dd × gm From (1), the number of oscillation cycles N can be derived
as
where Idis is the discharging current of M0, C L is the Tout (= Twindow) (V ctrlp − Vctrln )(V 2T /7)
N = =
loading, and gm is the transconductance of M1. With a more (V ip − Vin ) × V 2T (V ip − Vin ) × V 2T
cascaded number (S) of DEs, the input-referred noise of the (V ctrlp − Vctrln )
VCDL is smaller with less enabling of oscillation during = (5)
(V ip − Vin ) × 7
conversion, but it also consumes more power in one cycle.
To find the best “S” in terms of FoM and ENOB, a co- with an optimized and fixed control voltage (Vctrlp − Vctrln ).
simulation (HSPICE + MATLAB) has been executed. The This shows that the required number of oscillation cycles (N)
parameters from the HSPICE simulation at a target sampling defined by Tout ≥ Twindow is adaptively changed, depending
rate of 100 kHz (including the time-domain noise of the VCDL on the input difference level (Vip − Vin ). This also shows that
per oscillation cycle, power consumption of the VCDL per the adaptive “N” is PVT insensitive by canceling out the PVT
oscillation cycle, oscillation period of the VCDL, V 2T gain sensitive VTC gain of the VCDL (V 2T ) in (5). In choosing a
of the VCDL, power consumption of the digital circuit, and larger Twindow (Vctrlp − Vctrln ) as a threshold, more oscillation
power consumption of DAC switching) were put into the cycles are required to extend the time difference with a smaller
ADC behavioral models in MATLAB. The statistical results input-referred noise at a cost of larger power consumption
show that the ENOB and power vary with different “S” and and slower speed. Compared to the required cycles of the
time-domain threshold (Twindow) as in Fig. 9. This shows that oscillator collapse-based comparator [11] which depends on
a VCDL with S = 7 achieves the target ENOB and the lowest the oscillation frequency and VTC gain (V 2T ) of the VCDL,
power at Twindow = 1180 ps among all the other combinations. the optimal average number of oscillation cycles (average
Therefore, the VCDL with seven cascaded DEs is chosen in of N) of the ATD comparator controlled by the proposed DTW
this paper. is PVT-variation insensitive. From the HSPICE simulation,

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2768 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 10, OCTOBER 2018

Fig. 12. Voltage-to-time transfer curve of DE.

Fig. 10. MATLAB simulation of (a) ENOB versus Vctrl and (b) FOM versus
Vcrtlp − Vcrtln .

Fig. 13. Fine-tuned TSPC flip-flop.

Fig. 12 shows the simulated linearity of V 2T gain of the

DE, which is higher than 0.99 in the range of 0.5–40 LSB
(>36 LSB) to guarantee the fixed ratio of Tout and Twindow
under corner variations.

Fig. 11. DAC switching for Vctrlp and Vctrln generations. C. Phase Detector
The PD has high-speed dynamic-D flip-flops (DFFs)
and SR latch for time-domain polarity decision. The true
the oscillator collapse-based comparator [11] consumes an single-phase clock (TSPC) operated DFFs are employed for
additional 70% of the VCDL power for the design margin the leading-edge detection of “data” and “clk” as shown
of PVT-variation. In contrast, the required additional DTW in Fig. 13. By favoring the data = 1 condition with the larger
(including the voltage generation of Vctrlp,n ) and PD circuits sizing of M1, M2, M3, and M4, the setup time of the PD
consume only 17% of the VCDL power. In order to find is minimized to avoid the dead zone issue which degrades
the best Twindow (controlled by Vctrlp − Vctrln ) of the DTW the DTW performance. The implemented setup time is 10 ps
under process variations, MATLAB behavioral simulation with which is only 7% of Twindow and is negligible.
a target sampling rate of 100 KHz is executed as shown in
Fig. 10(a) and 10(b). Using a VCDL composed of a single
DE for power and area savings, the DTW shows the achieved D. Meta-Stability Prevention of ATD Comparator
FoMs are optimized with a control voltage of around 36 In low- to medium-speed SAR ADCs, the probability of
VLSB . Fig. 11 shows the detailed operation of the extra DAC the meta-stability occurrence of the conventional comparator
(composed of extra DACp and extra DACn with 114c for is dramatically reduced with the positive feedback latch. How-
each) for the generation of the differential-ratio control voltage ever, the ATD comparator with open-loop operation may have
(Vctrlp − Vctrln ). At the DAC reset phase, both Vctrlp and a meta-stable condition in the extremely critical case with
Vctrln are connected to the generated Vcm (Section II-A) for small input difference (Vip  Vin ). The resulting T of the
initialization. At the conversion phase, the bottom plates of small input voltage difference is so small that the accumulated
the 1c in the extra-DACp and extra-DACn are switched to Vdd time-delay difference after N oscillation cycles (N ∗ T ) is
and Vss . The generated voltage shifts of Vctrlp and Vctrln are still smaller than the target Twindow, which causes a sustained
+0.5 V/114 and −0.5 V/114, respectively. Since the VLSB = 1 oscillation and consumes a large amount of power. To omit the
V/4096, the achieved Vctrlp − Vctrln is 36 LSB (=4096/114). meta-stability induced oscillation, an additional meta-stability

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HSIEH et al.: 0.5-V 12-bit SAR ADC USING ATD COMPARATOR 2769

Fig. 14. Proposed meta-stability prevention circuit.

Fig. 16. Chip micrograph.

Fig. 15. MATLAB statistical result of the total oscillation cycle number per
sample. Fig. 17. Measured static performance.

prevention circuit is implemented as shown in Fig. 14. If the

comparison time of the ATD comparator is larger than the
maximum time budget set by the de-meta delay line, a meta-
stable condition is detected. Then, the oscillation is stopped
and the comparison result of the ATD comparator is forced
to “1” for a power reduction. Fig. 15 shows the MATLAB
statistical result of the total number of oscillation cycles per
sample with and without meta-stability prevention. This shows
that the total occurrence rate of samples that have more
than 42 oscillation cycles is around 2.27% without meta-
stability prevention. With a meta-stability prevention circuit,
the maximum oscillation cycles of the ATD comparator are
reduced from 77 cycles to 33 cycles to dramatically save power Fig. 18. Measured dynamic performance.
and conversion time.

IV. M EASUREMENT R ESULTS 10.75 bit, respectively. Fig. 19 shows the stable SNDR per-
Fig. 16 shows a micrograph of the prototype chip fabri- formance versus the input frequency with different sampling
cated in 1P9M 90-nm CMOS with an active area of 0.109 rates (100–250 kS/s). The control voltage (Vctrlp − Vctrln ) of
mm2 . Fig. 17 depicts the measured static performance of the the DTW can be externally adjusted in the test mode to
proposed ADC at 0.5-V and 100 kS/s. The MoM capacitor check the noise performance correlation with Twindow. Using
of the CDAC with the additional bottom-plate shielding metal a smaller (Vctrlp − Vctrln ), the number of oscillation cycles is
and a more uniform density [13] is adopted, which results in decreased, which results in a degraded SNDR and a faster
a higher matching performance. Thus, the measured peaks of achievable operational speed, as expected. Fig. 20 shows that
differential nonlinearity (DNL) and integral nonlinearity (INL) the total power dissipation is 0.81 μW ( f s = 100 kS/s) with
are +0.59/−0.7 LSB and +0.77/−0.88 LSB, respectively. a breakdown of 70% in the proposed comparator, 18% in the
Fig. 18 shows the measured dynamic performance of the DAC switching energy, and 12% in the digital control circuits.
implemented ADC with low and Nyquist input frequency Table I summarizes the performance comparison of the
at a sampling rate of 100 kS/s. The resultant SNDR and prototype with state-of-the-art low-power designs in 12-bit
corresponding ENOB at the Nyquist input are 66.48 dB and resolution. With the proposed ATD low-noise comparator,

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2770 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 10, OCTOBER 2018

TABLE I
C OMPARISON TABLE W ITH S TATE - OF - THE -A RT W ORKS

University (NTHU), Hsinchu, Taiwan, for their manufacturing

and measurement supports.

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[11] M. Shim et al., “An oscillator collapse-based comparator with appli-
adaptively suppressed with efficient power consumption. The cation in a 74.1 dB SNDR, 20 KS/s 15 b SAR ADC,” in Proc. IEEE
prototyped ADC achieves an SNDR from 63.8 to 66.3 dB and Symp. VLSI Circuits, Jun. 2016, pp. 1–2.
a corresponding FoM from 4.52 to 4.82 fJ/conversion step. [12] C.-C. Kao, S.-E. Hsieh, and C.-C. Hsieh, “A 0.5 V 12-bit SAR ADC
using adaptive timedomain comparator with noise optimization” in Proc.
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ACKNOWLEDGMENT [13] S.-E. Hsieh and C.-C. Hsieh, “A 0.3-V 0.705-fJ/conversion-step 10-bit
SAR ADC with a shifted monotonic switching procedure in 90-nm
The authors would like to thank the National Chip Imple- CMOS,” IEEE Trans. Circuits Syst., II, Exp. Briefs, vol. 63, no. 12,
mentation Center (CIC) and SiSAL in National Tsing Hua pp. 1171–1175, Dec. 2016.

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HSIEH et al.: 0.5-V 12-bit SAR ADC USING ATD COMPARATOR 2771

[14] R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Chen-Che Kao received the B.S. degree from
J. Sel. Areas Commun., vol. 17, no. 4, pp. 539–550, Apr. 1999. National Tsing Hua University, Hsinchu, Taiwan,
[15] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Con- in 2013, where he is currently pursuing the M.S.
verters. Piscataway, NJ, USA: IEEE Press, 2005. degree in electrical. engineering
[16] P. Harpe et al., “An oversampled 12/14b SAR ADC with noise reduction He is currently involved in the research of
and linearity enhancements achieving up to 79.1 dB SNDR,” in IEEE low-power and high-resolution SAR analog-to-
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 194–195, digital converter (ADC) for biomedical and wireless
Feb. 2014. applications. His current research interests include
[17] K. Yoshioka and H. Ishikuro, “A 13 b SAR ADC with eye-opening VCO mixed analog/digital circuit designs, especially in
based comparator,” in Proc. ESSCIRC 40th Eur. Solid State Circuits ADCs.
Conf. (ESSCIRC), Sep. 2014, pp. 411–414.
[18] M. Liu, A. van Roermund, and P. Harpe, “A 7.1 fJ/conv.-step 88 dB-
SFDR 12 b SAR ADC with energy-efficient swap-to-reset,” in Proc.
IEEE ESSCIRC, Sep. 2016, pp. 409–412.
[19] J.-Y. Lin and C.-C. Hsieh, “A 0.3 V 10-bit SAR ADC with first 2-bit
guess in 90-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 64, no. 3, pp. 562–572, Mar. 2017.
[20] L. Chen, X. Tang, A. Sanyal, Y. Yoon, J. Cong, and N. Sun, “A 0.7-V
0.6-μW 100-kS/s low-power SAR ADC with statistical estimation-
based noise reduction,” IEEE J. Solid-State Circuits, vol. 52, no. 5,
pp. 1388–1398, May 2017.
Chih-Cheng Hsieh received the B.S., M.S., and
Ph.D. degrees from the Department of Elec-
tronics Engineering, National Chiao-Tung Univer-
sity, Hsinchu, Taiwan, in 1990, 1991, and 1997,
Sung-En Hsieh received the B.S. degree in electrical respectively.
engineering from National Tsing Hua University, From 1999 to 2007, he was with IC Design House,
Hsinchu, Taiwan, in 2014, where he is currently Pixart Imaging Inc., Hsinchu, where he was involved
pursuing the Ph.D. degree. in the development of CMOS image sensor ICs
His research interests include low-power and low- for PC, consumer, and mobile phone applications.
voltage successive-approximation register (SAR) In 2007, he joined the Department of Electrical Engi-
AD converters, digital circuit optimization, and time- neering, National Tsing Hua University, Hsinchu,
to-digital converter design for oximeter application. where he is currently a Full Professor. His current research interests include
low-voltage low-power smart CMOS image sensor IC, ADC, and mixed-mode
IC development for artificial intelligence (AI), Internet of Things (IoT),
biomedical, space, robot, and customized applications.

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