INTEGRATED CIRCUIT LOGIC FAMILIES

The integrated circuit (IC) Before ICs, circuit connections were made from one discrete component to another Discrete components: diode, transistor, resistor, etc. ICs have internal connections, protecting them from most physical problems (like poor soldering, breaks and shorts) Require less power to perform functions Cannot handle very large currents or voltages due to limited space Cannot easily implement electrical devices such as inductors, transformers and large capacitors Thus, ICs are typically used for low-power circuit operations such as information processing.

Digital IC Terminology

Current and Voltage Parameters VIH(min)- High-level Input Voltage: The minimum voltage level required for a logical 1 at an input. VIL(max)- Low-level Input Voltage: The maximum voltage level allowable for a logic 0 at an input. VOH(min)-High-level Output Voltage: The minimum voltage level at a logic circuit output in the logical 1 state, under defined load conditions. VOL(max)- Low level Output Voltage: The maximum voltage level at a logic circuit output in the logical 0 state under defined load conditions. IIH - High-level Input Current: The current that flows into an input when a specified highlevel voltage is applied to that input IIL Low-level input Current: The current that flows into an input when a specified lowlevel voltage is applied to that input IOH High-level Output Current: The current that flows from an output in the logical 1 state under specified load conditions IOL Low-level Output Current: The current that flows from an output in the logical 0 state under specified load conditions

Fan-in and Fan-out Fan-in refers to the number of inputs to a certain logic gate. As the fan-in of a gate increases, the gate performs slower, as delay is introduced due to the input capacitance of the device. Fan-out refers to the number of logic inputs (or gates) that a particular logic output drives. The fan-out of a device, also called the loading factor, is defined as the maximum number of logic inputs that an output can drive reliably. Increasing the number of driven outputs past the fan-out can result in deviation of the output logic-level voltages.

Propagation Delay Logic signals experience delays as they progress through a circuit. Two types of propagation delays: o tPLH delay time in going from logic 0 to logic 1 state (low to high) o tPHL delay time in going from logic 1 to logic 0 state (high to low)

Propagation delay times are measured between the 50% points of the input and output. H2L and L2H propagation times are not usually the same, and varies on the capacitive loading of the input and output.

Power Requirements Voltage supply is designated as Vcc (for TTL) and VDD (for MOS devices) P = Icc x Vcc (i.e. for TTL) Icc is dependent on the logic states of the circuits on the chip. PAVE = Icc(AVE) x Vcc

Icc(ave)

Icc H Icc L 2

Speed Power Product Ideally we want shorter gate propagation delays and lower power dissipation values Realistically, the two are inversely proportional; its difficult to do both at the same time SPP = propagation delay x gate power dissipation (average values) The lower the SPP, the better

Noise Immunity Stray electric and magnetic fields can induce voltages on connecting wires, resulting in unwanted, spurious signals called noise. Noise may cause a logics circuit input voltage to drop below VIH(min) or rise above VIL(max), resulting in unpredictable operation. Noise immunity a circuits ability to tolerate noise without causing changes in output voltage Noise margin a measure of noise immunity

Indeterminate/disallowed ranges shouldnt be used. High-state noise margin, VNH = VOH(min) VIH(min) Low-state noise margin, VNL = VIL(max) VOL (max) Negative noise spikes less than VNH and positive noise spikes greater than VNL can result in the voltage falling in the disallowed/indeterminate range.

Current-Sourcing and Current-sinking action

IC Packages The following table summarizes the different IC packaging and the corresponding height and lead pitch (spacing between pins).

The TTL Logic Family One of the first IC technologies; now almost obsolete replaced by MOS technology Two basic TTL logic circuits: NAND and NOR gates

TTL NAND GATE

Multiple-emitter input transistor: when either of the inputs are forward-biased, Q1 is ON. When all inputs are reverse-biased, Q1 is off. Totem-pole arrangement- Q3 connects Vcc to the output, Q4 connects output to ground. IN normal operation, either one (but not both) will be conducting, depending on the output logic.

TTL NAND GATE Low State Operation

0.8 V @ Q2 is estimated with Vbe of 0.7 Volts and a Vce(sat) of 0.1 voltsThis 0.8 V is insufficient to turn both Q3 and D1 on, hence the pull-up transistor Q3 is OFF. Meanwhile, Q4 acts as the pull-down transistor. Also, Vo is low since the effective resistance of Q4 is small. TTL NAND GATE High State Operation

This time Q3 can be turned on even with the voltage drop at R2, with Q2 off due to insufficient current from D4. VOH is around 3.4-3.8 volts as caused by two 0.7 V drops (Q3 and D1) but will still be reduced by the voltage drop @ resistor R2. The pull-up transistor Q3 is now ON, while the pulldown transistor Q4 is OFF.

CURRENT-SOURCING and CURRENT-SINKING of TTL NAND Gates

The LOW-state NAND gate acts as a current sink, taking its current from the load gate, while the HIGH-state NAND acts as a current source, driving its current to the load gate. The totem-pole arrangement Regulates current through resistor R4 in the output LOW state = low power dissipation For the HIGH state, provides low output impedance, which allows for a shorter time constant (RC) when charging any capacitive load on the output = fast rise-time. Disadvantage: at LOW-to-HIGH transition, Q4 turns off more slowly than Q3 turns on, thus gives a period where both Q4 and Q3 are on and drawing a relatively large current from Vcc.

TTL NOR Gate

TTL Loading and Fan-out

Left fig. shows the current-sinking action of a NAND gate at its LOW state Right fig. shows the current-sourcing action of a NAND gate at its HIGH state

Consider: if each IC has datasheet specifications of the following: IIL = 1.6 mA, and VOL(max) = 0.4 V, VIL(max) = 0.8 V, and Q4 can sink 16mA before VOL = 0.4 V How many IILs can it sink? Ans. 16 mA/1.6mA = 10 loads. Exceeding this will in turn exceed VOL and will reduce the noise margin, or worse, push VOL up to the indeterminate voltage stage. On the other hand, if it sources too many loads, the main sourcing current IOH will be large enough to cause voltage drops across R2, Q3 and D1 to bring VOH below its minimum value. This reduces, this time, the HIGH-state noise margin and may lower VOH to the indeterminate range. Summary: A TTL output has a limit, IOL(max) on how much current it can sink in the LOW state A TTL output has a limit, IOH(max) on how much current it can source in the HIGH state It is important that the sum of all load currents be less than the driving (sourcing or sinking) outputs IOH or IOL specification.

For same ICs, fan-out is given by the following equations:

Fan out ( HIGH )

I OH (max) , I IH (max)

Fan out ( LOW )

I OL (max) I IL (max)

Examples: Given the table of TTL logic families and their characteristics:

1. Calculate the DC noise margins for a typical 74LS IC, and compare it with the standard TTL (74) noise margins. 2. Which TTL series can drive the most device inputs of the same series? 3. Which of the following TTL series is a. Best at high frequencies? b. Has the largest HIGH-state noise margin? Fan-out calculations: Base the current calculations on the given table. In practice, the values can be found on the specific ICs datasheet.

* negative sign simply indicates current direction. Observe that all IOH and IIL values are negative, meaning that the current is flowing out of the node. Basic fan-out (i.e. same family drive) 1. How many 74ALS00 NAND gate inputs can be driven by a 74ALS00 NAND gate output?

In practice, youll most likely combine ICs from different families. General steps for different-family fan-out computation: 1. Add up the IIH for all inputs connected to an output. This sum must be less than the outputs IOH specification (for current sourcing action; HIGH-state driving output). 2. Add up the IIL for all inputs connected to an output. This sum must be less than the outputs IOL specification (for current sinking action; LOW-state driving output). Example 1. A 74LS00 NAND gate output is driving three 74S gate inputs and one 7406 output. Determine if there is a loading problem based on fan-out calculations. 2. The 74LS00 NAND gate in the previous example needs to be used to drive some 74ALS inputs in addition to its load above. How many 74ALS inputs can be driven without overloading? 3. The output of a 74AS04 inverter is providing the CLEAR signal to a parallel register made up of 74AS74 D flip-flops. What is the maximum number of FF CLR inputs can this gate drive? The asynchronous inputs of the D flip-flop have specifications of IIH = 40A and IIL = 1.8mA. Note that these values are different from the table specifications, which are the ones we use for the clock and D inputs. 4. A 74ALS gate output is currently driving two 74ALS loads and three 74F loads. How many more of the following gates can it drive without overloading? (a) 74LS? (b) 74S?

MOS Technology MOS- metal oxide semiconductor Basic MOS structure involves a metal electrode over an oxide insulator over a semiconductor substrate. MOSFET- metal-oxide semiconductor field-effect transistor Two types: depletion and enhancementdigital ICs use enhancement MOSFETs MOS ICs are composed of MOSFETs entirely Advantages of MOSFETs Simple and inexpensive to fabricate- one-third as complex as bipolar ICs Small, covers less area, esp. because it doesnt utilize resistors Rather, uses the capability of MOSFET as a resistive element Consumes very little power Used primarily in LSI and VLSI (large; very large scale integration) Main disadvantage: Susceptibility to static-electricity damage. That is why TTL ICs are still preferred for laboratory experimentation and digital electronics education.

Schematic symbols for MOSFETs

Note two things: Broken line b/w source and drain indicating that there is normally no conducting channel b/w the electrodes (but the channel forms when properly biased, resulting in conduction) Separation b/w gate and the DS terminals, showing very high resistance of the oxide layer between the gate and channel. MOSFET Switching 1. N-channel MOSFET, or simply NMOS: ON when a positive VGS is applied, OFF when no VGS applied.

2. P-channel MOSFET, or PMOS: turns ON when negative VGS is applied (that is, opposite polarity compared to the NMOS). 3. We can think of NMOS as active-high switches and PMOS as active-low switches.

Summary:

COMPLEMENTARY MOS (CMOS) Logic Uses both PMOS and NMOS in the same circuit Faster and consumes even less power than other MOS families Complementary: has pull-up network (PUN) and pull-down network (PDN), only one of which is active at any operation. PUN is composed of only PMOS transistors, PDN is composed of only NMOS transistors. If reversed, corresponding threshold voltage drops are encountered. PUN is the dual of PDN (i.e. application of DeMorgans theorem). Again, PMOS transistors are active-low transistors, NMOS transistors are active high. CMOS Inverter

CMOS NAND Gate

CMOS NOR Gate

Exercise: Implement the following using CMOS logic. Hint: use the concept of the universal gates and the networks discussed. 1. A three-input NAND gate 2. A three-input NOR gate 3. A two-input AND gate CMOS Logic Family Characteristics

CMOS Power Characteristics Very low power given DC inputs, since the resistance in the active networks path includes an off MOSFET, thus the value of power dissipation (V2/R ) is low (i.e. 25/1010=2.5nW). However, at switching states which involve frequency, CMOS begins to increase power dissipation due to current being drawn/supplied to the capacitive load during switching.

CMOS Fan-out The input signals essentially dont draw current since they have very high resistance when OFF However, each CMOS input presents a typical capacitive load to ground (usually 5pF). Increasing the loads adds parallel capacitances, which are additive. Increasing total capacitive load increases propagation delay (typically 3 ns per CMOS load)

Unused inputs, ESD and Latch-up CMOS inputs should never be left disconnected, and must be tied either to VDD , ground, or an input CMOS is susceptible to noise and static charges that could easily bias the PUN and PDN ESD electrostatic discharge Latch-up: caused by parasitic (unwanted) PNP and NPN transistors embedded in CMOS IC substrates, also by unused/unconnected inputs. CMOS Bilateral Switch (Transmission Gate)