Common digital components

By
Andargie Mekonnen
Integrated Circuits

An integrated circuit (IC) is manufactured using silicon material and

mounted in a ceramic or plastic container (known as Chip).
The basic components of an IC consist of electronic circuits for the digital
gates.
The various gates are interconnected inside an IC to form the required
circuit.
The following categories can broadly classify an Integrated Circuit (IC):
SSI (Small Scale Integration Devices)
MSI (Medium Scale Integration Devices)
LSI (Large Scale Integration Devices)
VLSI (Very Large Scale Integration Device)

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Integrated Circuits
SSI (Small Scale Integration Devices)
These type of devices contain several independent gates in a single package.
The inputs and outputs of these gates are connected directly to the pins in the
package.
The number of logic gates are usually less than 10 and are limited by the
number of pins available in the IC.
MSI (Medium Scale Integration Devices)
These type of devices has a complexity of approximately 10 to 200 gates in a
single package.
The basic components include decoders, adders, and registers.

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Integrated Circuits
LSI (Large Scale Integration Devices)
LSI devices contain about 200 to a few thousand gates in a single package.
The basic components of an LSI device include digital systems, such as
processors, memory chips, and programmable modules.
VLSI (Very Large Scale Integration Device)
This type of devices contains thousands of gates within a single package.
The most common example of a VLSI device is a complex microcomputer
chip.

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Integrated Circuits
Digital integrated circuits are also classified by their specific circuit technology to
which they belong.
The circuit technology is often referred to as Digital Logic Family.
Each technology has its own basic electronic circuit and functions to perform.
The most common component in each technology is either a NAND, a NOR, or an
inverter gate.
The most popular among the digital logic families include:

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TTL (Transistor-transistor Logic)
The TTL technology was an upgraded version of a previous
technology called as DTL (Diode-Transistor Logic).
The DTL technology used to have diodes and transistors for the
basic NAND gate.
TTL came in existence when these diodes are replaced with
transistors to improve the circuit operation.
There are several variations of the TTL like high-speed TTL, low-
power TTL, Schottky TTL, low-power Schottky TTL, and
advanced Schottky TTL.

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TTL (Transistor-transistor Logic)
The following circuit diagram shows a Standard TTL circuit and its
configuration.

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TTL (Transistor-transistor Logic)
Features of TTL Family:
The overall power supply voltage for TTL circuit is 5 volts, and the two logic
levels are approximately 0 and 3.5 volts.
A TTL circuit can support at most 10 gates at its output.
The average propagation delay for a TTL circuit is about 9ns.
TTL Applications
TTL is used as a switching device in driving lamps and relays.
TTL is used in controller application for providing 0 to 5Vs.
TTL families are mostly used in processors of minicomputers like DEC VAX.
It is also used in printers and video display terminals.

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ECL (Emitter-coupled Logic)
The ECL technology provides the highest-speed digital circuits in
integrated form.
An ECL circuit is used in supercomputers and signal processors where
high speed is essential.
The transistors in ECL gates operate in a non-saturated state, a
condition that allows the achievement of propagation delays of 1 to 2
nanoseconds.

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ECL (Emitter-coupled Logic)

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ECL (Emitter-coupled Logic)
Features of ECL Family
The logic gates continuously draw current even in the inactive state.
Hence power consumption is more as compared to other logic families.
ECL uses bipolar transistor logic where the transistors are not operated in the
saturation region.
The average propagation delay for an ECL gate is about 0.5 to 2ns.

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MOS (Metal-oxide semiconductor)
The MOS (Metal-oxide semiconductor) is a unipolar transistor that
depends on the flow of only one type of carrier, which may be
electrons (n-channel) or holes (p-channel).
MOS technology is generally categorized in two basic forms:
A p-channel MOS is referred to as PMOS.
An n-channel MOS is referred to as NMOS.

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MOS (Metal-oxide semiconductor)
PMOS
The operations performed by a PMOS logic family can be explained by
considering a PMOS NAND gate.
The following circuit diagram shows a two input PMOS NAND gate.

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MOS (Metal-oxide semiconductor)
When a low logic is applied to either A or B, the transistor gets
activated.
This makes a connection between power supply and the output
terminal.
When a low logic is applied, the output is raised to a logic high value.
Otherwise, it will remain at logic low in other cases.
The pull-down resistor 'R' maintains the low logic unless a low logic
is applied to either A or B.

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MOS (Metal-oxide semiconductor)
NMOS
The structure of NMOS logic is similar to that of PMOS.
However, instead of using PMOS transistors, here we will use NMOS
transistors along with a pull-up resistor R.
The following circuit diagram shows a two input NMOS NAND gate.

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MOS (Metal-oxide semiconductor)
As shown in the circuit diagram, an NMOS NAND gate has two NMOS
transistors connected in series from the output to the ground terminal.
A pull-up resistor is connected from the output terminal to the power
supply.
When a high logic is applied to both inputs, both of the transistors get
activated.
This makes a connection between the output terminal and ground.
In case, any one of the input is at logic high, and the other one is at logic
low, the transistor gets deactivated.
This terminates the path between the output terminal and ground.
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CMOS (Complementary metal-oxide semiconductor)

The complementary MOS or CMOS technology uses PMOS and

NMOS transistors connected in a complementary manner in all
circuits.
CMOS logic families are highly preferred in large-scale integrated
circuits because of its high noise immunity and low power dissipation.
The following circuit diagram shows a Standard CMOS circuit and its
configuration.

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CMOS (Complementary metal-oxide semiconductor)

Q1 and Q2 are the respective NMOS and PMOS transistors connected in a
complementary fashion.
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Decoders
A Decoder can be described as a combinational circuit that converts
binary information from the 'n' coded inputs to a maximum of 2^n
different outputs.
Note: A binary code of n bits is capable of representing up to 2^n
distinct elements of the coded information.
The most preferred or commonly used decoders are n-to-m decoders,
where m<= 2^n.
An n-to-m decoder has n inputs and m outputs and is also referred to
as an n * m decoder.

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Decoders
The following image shows a 3-to-8 line decoder with three input variables which
are decoded into eight output, each output representing one of the combinations of
the three binary input variables.

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Decoders…
The three inverter gates provide the complement of the inputs
corresponding to which the eight AND gates at the output generates
one binary combination for each input.
The most common application of this decoder is binary-to-octal
conversion.

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Decoders…
The truth table for a 3-to-8 line decoder can be represented as:
x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

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Decoders…
 Let us consider an example of 2-to-4 line The truth table for a 2-to-4 line
NAND Gate Decoder which uses NAND
Gates instead of AND gate in the central logic. decoder can be represented as:
 The following image shows a 2-to-4 line
E A1 A0 D0 D1 D2 D3
decoder with NAND gates.

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

1 0 0 1 1 1 1
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Decoders…
It is also possible to combine two or more decoders to form a large decoder
whenever needed.
For instance, we can construct a 3 * 8 decoder by combining two 2 *4 decoders.
The following image shows a 3 * 8 decoder constructed with two 2 * 4 decoders.

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Encoders
An encoder can also be described as a combinational circuit that performs the
inverse operation of a decoder.
An encoder has a maximum of 2^n (or less) input lines and n output lines.
In an Encoder, the output lines generate the binary code corresponding to the input
value.
The following image shows the block diagram and truth table of a 4 * 2 encoder
with four input and two output lines.
truth table
A3 A2 A1 A0 D1 D0

0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0

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0 0 0 1 1 25
Encoders
From the truth table, we can write the Boolean function for each output as:
D1 = A3 + A2
D0 = A3 + A1
The circuit diagram for a 4-to-2 line encoder can be represented by using two
input OR gates.

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Encoders
The most common application of an encoder is the Octal-to-Binary encoder.
Octal to binary encoder takes eight input lines and generates three output lines.
The following image shows the block diagram and truth table of an 8 * 3 line
encoder. Truth table
D D D D D D D D x y z
7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
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Encoders
From the truth table, we can write the Boolean function for each output as:
x = D4 + D5 + D6 + D7
y = D2 + D3 + D6 + D7
z = D1 + D3 + D5 + D7
The circuit diagram for an 8 * 3 line encoder can be represented by using two
input OR gates.

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Multiplexers
A Multiplexer (MUX) can be described as a combinational circuit that
receives binary information from one of the 2^n input data lines and
directs it to a single output line.
The selection of a particular input data line for the output is decided
on the basis of selection lines.
The multiplexer is often called as data selector since it selects only
one of many data inputs.
Note: A 2^n-to-1 multiplexer has 2^n input data lines and n input
selection lines whose bit combinations determine which input data are
selected for the output.

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Multiplexers
The following image shows the block diagram of a 4 * 1 Multiplexer.

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Multiplexers
Out of these four input data lines, a particular input data line will be connected to
the output based on the combination of inputs present at these two selection lines.
Note: A truth table describing the circuit needs 64 rows since six input variables
can have 2^n binary combinations.
This will result in an excessively long table.
Therefore, a more convenient way to describe the operation of multiplexers is
using a function table.
The function table for a 4 * 1 Multiplexer can be represented as:
S1 S0 y

0 0 I0
0 1 I1
1 0 I2
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1 1 13
Multiplexers
From the function table, we can write the Boolean function for the output (y) as:
y = S1'S0'I0 + S1' S0'I1 + S1S0'I2 + S1S0I3
The above equation for output 'y' can be implemented using inverters, three-input
AND gates and an OR gate.

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Multiplexers
We can also implement higher order multiplexers using lower order
multiplexers.
For instance, let us implement an 8 *1 multiplexer using two 4*1
multiplexers and a 2*1 multiplexer.
The two 4*1 multiplexers are required in the first stage to get the eight
input data lines.
A 2*1 multiplexer is required in the second stage to converge the
outputs generated at first stage into a single output.

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Multiplexers
The following image shows the block diagram of an 8*1 multiplexer
designed using two 4*1 multiplexers and a single 2*1 multiplexer.
S2 S1 S0 y

0 0 0 10
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 17
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Multiplexers
A set of common selection lines (S1 and S2) are applied to both of the
4*1 multiplexers.
The output generated by both of the 4*1 multiplexers is applied as
inputs of the 2*1 multiplexer.

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De-Multiplexers
A De-multiplexer (De-Mux) can be described as a combinational
circuit that performs the reverse operation of a Multiplexer.
A De-multiplexer has a single input, 'n' selection lines and a maximum
of 2^n outputs.
The following image shows the block diagram and function table of a
1 * 4 De-multiplexer.
S1 S0 y3 y2 y1 y0

0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
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De-Multiplexers
From the above function table, we can write the Boolean function for each output
as:
y3 = S1S0 I, y2 = S1S0' I, y1 = S1' S0 I, y0 = S1'S0' I
The above equations can be implemented using inverters and three-input AND
gates.

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De-Multiplexers
We can also implement higher order De-multiplexers using lower order De-
multiplexers.
For instance, let us implement a 1 * 8 De-multiplexer using 1 * 2 De-multiplexer
in the first stage followed by two 1 * 4 De-multiplexers in the second stage.
The function table for a 1 * 8 De-multiplexer can be represented as:
S2 S1 S0 y7 y6 y5 y4 y3 y2 y1 y0

0 0 0 0 0 0 0 0 0 0 I
0 0 1 0 0 0 0 0 0 I 0
0 1 0 0 0 0 0 0 I 0 0
0 1 1 0 0 0 0 I 0 0 0
1 0 0 0 0 0 I 0 0 0 0
1 0 1 0 0 I 0 0 0 0 0
1 1 0 0 I 0 0 0 0 0 0
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De-Multiplexers
The block diagram for a 1 * 8 De-multiplexer can be represented as:

The Selection lines 'S1' and 'S0' are common for both of the 1 * 4 De-
multiplexers.
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Registers
A Register is a fast memory used to accept, store, and transfer data and
instructions that are being used immediately by the CPU.
A Register can also be considered as a group of flip-flops with each flip-
flop capable of storing one bit of information.
A register with n flip-flops is capable of storing binary information of n-
bits.
The flip-flops contain the binary information whereas the gates control the
flow of information, i.e. when and how the information?s are transferred
into a register.
Different types of registers are available commercially.
A simple register consists of only flip-flops with no external gates.
The transfer of new data into a register is referred to as loading the register.
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Registers
The following figure shows a register constructed with four D-type flip-flops and
a common clock pulse-input.
The clock pulse-input, CP, enables all flip-flops so that the information presently
available at the four inputs can be transferred into the four-bit register.

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Shift - Registers
Shift - Registers are capable of shifting their binary information in one
or both directions.
The logical configuration of a Shift - Register consists of a series of
flip-flops, with the output of one flip-flop connected to the input of the
next flip-flop.
Note: To control the flow of shifts, i.e. the flow of binary information
from one register to the next, a common clock is connected to all of
the registers connected in series.
This clock generates a clock pulse which initiates the shift from one
stage to the next.
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Shift - Registers
The following image shows the block diagram of a Shift - Register
and its configuration.

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Shift - Registers
The basic configuration of a Shift - Register contains the following
points:
The most general Shift - Registers are often referred to as Bidirectional Shift
Register with parallel load.
A common clock is connected to each register in series to synchronize all
operations.
A serial input line is associated with the left-most register, and a serial output
line is associated with the right-most register.
A control state is connected which leaves the information in the register
unchanged even though clock pulses are applied continuously.

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Counters
A register that goes through a prescribed sequences of states upon the
application of an input pulse is called a counter.
The input pulse may be a clock pulse or may have some other origin.
 A counter that goes through a binary sequence is called a binary
counter.
An n-bit binary counter uses n flip-flops and can count from 0 to 2n-1
Counters are either ripple counters or synchronous counters.
 In synchronous counters, all flip-flops receive the common clock
pulse; therefore they change at the same time.
In ripple counters, the output of one flip-flop is used as a source for
triggering others.

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Counters

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Counters

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Counters

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Counters

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Counters

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Memory Unit
A Memory Unit is a collection of storage cells together with associated circuits
needed to transfer information in and out of storage.
The memory stores binary information(1's and 0's) in groups
of bits called words.
A word in memory is an entity of bits that move in and out of storage as a unit. A
memory word is a group of 1's and 0's and may represent a number, an instruction
code, one or more alphanumeric characters, or any other binary coded
information.
A group of eight bits is called a byte. Most computer memories use words whose
number of bits is a multiple of 8.
Thus a 16-bit word contains two bytes, and a 32-bit word is made up of 4 bytes.
The capacity of memories in commercial computers is usually stated as the total
number of bytes that can be stored.

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Internal Structure of a Memory Unit

The internal structure of a memory unit is specified by the number of

words it contains and the number of bits in each word.
 Special input lines called address lines select one particular word.
Each word in memory is assigned an identification number, called
an address, staring from 0 and continuing with 1, 2, 3, up to 2k -
1 where k is the number of address lines.
The selection of a specific word inside the memory is done by
applying the k-bit binary address to the address lines.

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Internal Structure of a Memory Unit
A decoder inside the memory accepts this address and opens the paths
needed to select the bits of the specified word.
Computer memories may range from 1024 words, requiring an
address of 10 bits, to 232 words, requiring 32 address bits.
It is customary to refer to the number of words(or bytes) in a memory
with one of the letters:
K(Kilo) is equal to 210
M(Mega) is equal to 220
G(Giga) is equal to 230

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Internal Structure of a Memory Unit
Two major types of memories are used in computer systems:
Random Access Memory(RAM) and
Read Only Memory(ROM).

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Random Access Memory(RAM)
In random-access memory(RAM) the memory cells can be accessed
for information transfer from any desired random location.
That is, the process of locating a word in memory is the same and
requires an equal amount of time no matter where the cells are located
physically in memory.
Communication between a memory and its environment is achieved
through data input and output lines, address selection lines, and control
lines that specify the direction of transfer.

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Random Access Memory(RAM)
• A block diagram of a RAM unit is shown below:

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Random Access Memory(RAM)
The n data input lines provide the information to be stored in memory,
and the n data output lines supply the information coming out of
particular word chosen among the 2k available inside the memory.
The two control inputs specify the direction of transfer desired.
The two operations that a random access memory can perform are
the write and read operations.
The write signal specifies a transfer-in operation and the read signal
specifies a transfer-out operation.
On accepting one of these control signals. The internal circuits inside
the memory provide the desired function.

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Random Access Memory(RAM)
The steps that must be taken for the purpose of transferring a new word to
be stored into memory are as follows:
Apply the binary address of the desired word into the address lines.
Apply the data bits that must be stored in memory into the data input lines.
The memory unit will then take the bits presently available in the input data lines and
store them in the specified by the address lines.
The steps that must be taken for the purpose of transferring a stored word
out of memory are as follows:
Apply the binary address of the desired word into the address lines.
Activate the read input.
The memory unit will then take the bits from the word that has been selected by the
address and apply them into the output data lines.
The content of the selected word does not change after reading.
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Read Only Memory(ROM)

As the name implies, a read-only memory(ROM) is a memory unit

that performs the read operation only; it does not have a write
capability.
This implies that the binary information stored in a ROM is made
permanent during the hardware production of the unit and cannot be
altered by writing different words into it.

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Read Only Memory(ROM)
Whereas a RAM is a general-purpose device whose contents can be
altered during the computational process, a ROM is restricted to
reading words that are permanently stored within the unit.
The binary information to be stored, specified by the designer, is then
embedded in the unit to form the required interconnection pattern.
ROMs come with special internal electronic fuses that can
be programmed for a specific configuration.
Once the pattern is established, it stays within the unit even when
power is turned off and on again.

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Read Only Memory(ROM)
An m x n ROM is an array of binary cells organized into m words of n bits each.
As shown in the block diagram below, a ROM has k address input lines to select
one of 2k = m words of memory, and n input lines, one for each bit of the word.
An integrated circuit ROM may also have one or more enable inputs for
expanding a number of packages into a ROM with larger capacity.

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Read Only Memory(ROM)
The ROM does not need a read-control line since at any given time,
the output lines automatically provide the n bits of the word selected
by the address value.
Because the outputs are a function of only the present inputs (the
address lines), a ROM is classified as a combinational circuit.
In fact, a ROM is constructed internally with decoders and a set of OR
gates.
There is no need for providing storage capabilities as in RAM, since
the values of the bits in the ROM are permanently fixed.

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Read Only Memory(ROM)
ROMs find a wide range of applications in the design of digital systems.
As such, it can implement any combinational circuit with k inputs
and n outputs.
When employed in a computer system as a memory unit, the ROM is used
for storing fixed programs that are not to be altered and for tables of
constants that are not subject to change.
 ROM is also employed in the design of control units for digital computers.
As such, they are used to store coded information that represents the
sequence of internal control variables needed for enabling the various
operations in the computer.
A control unit that utilizes a ROM to store binary control information is
called a microprogrammed control unit.

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 Any Question?

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