Combinational Circuits

Adder/Subtractor Circuits: Circuits that can find the sum or difference of binary numbers.
Half Adder (HA): A circuit that can add two single-bit binary numbers
Inputs: Two single-bit numbers A , B ∈ {0 , 1 }
Output: R=A +B . Here +¿ represents arithmetic sum.
R is a two-bit number. R ∈{00 , 01, 10 }.
LSB of R is called the SUM (S), and the MSB of R is called the CARRY OUT (C o).

Truth table: Logic Diagram of a Half Adder (HA)

Inputs Outputs
B A R=A +B Co S
0 0 00 0 0
0 1 01 0 1
1 0 01 0 1
1 1 10 1 0
From the table it is evident that:
C o= A ⋅ B Half Adder (HA)
S= A ⊕ B

Exercise:
Implement the HA circuits using only NAND gates.
Implement the HA circuits using only NOR gates.

Full Adder (FA): A circuit that can add three single-bit binary numbers
Inputs: Two single-bit numbers A , B ,C ∈ {0 , 1 }
Output: R=A +B +C . Here +¿ represents arithmetic sum.
R is a two-bit number. R ∈{00 , 01, 10 , 11}.
LSB of R is called the SUM (S), and the MSB of R is called the CARRY OUT (C o).
Truth table:
Inputs Outputs
C B A R=A +B +C Co S
0 0 0 00 0 0
0 0 1 01 0 1
0 1 0 01 0 1
0 1 1 10 1 0
1 0 0 01 0 1
1 0 1 10 1 0
1 1 0 10 1 0
1 1 1 11 1 1

K-map for S K-map for C o

BA 00 01 11 10 BA 00 01 11 10
C C
0 0 1 0 1 0 0 0 1 0

1 1 0 1 0 1 0 1 1 1
S cannot be simplified.
S= A ⊕ B ⊕ C C o= AB+BC + AC
 Note S=1 when odd number of inputs are 1

Logic Diagram of a Full Adder (FA)

Full Adder (FA)

Implementing a Full Adder using Half Adders:

S= A ⊕ S 1=A ⊕ ( B ⊕ C )= A ⊕ B ⊕ C

C O=C O 2 +CO 1
¿ A ⋅ S1 + B⋅C
¿ A ⋅ ( B⊕ C ) + B⋅ C
¿ A BC + A BC + BC
¿ A BC + BC + A BC + B C
¿ B ( A C +C )+ ( A B+ B ) C
¿ B ( A +C ) + ( A+ B ) C
¿ AB+ AC + BC

Ripple Carry Adder: A multi-bit Adder Circuit

A3 A2 A1 A0
+ B3 B2 B1 B0
Co S3 S2 S1 S0

Adder/Subtractor Circuit:
 When
ADD / ¿ ¿ = 0
Circuit adds B to A

When
ADD / ¿ ¿ = 1
Circuit subtracts B from A

Explanation:
X ⊕ 0=X
X ⊕ 1= X (XOR gates are called controlled NOT gates or controlled inverters.)

When ADD / ¿ ¿ = 1, the XOR gates inverts all the bits of B.

Thus, we get 1’s complement of B at the output of the XOR gate.
S= A +1' s complement ( B ) +1
'
¿ A+2 s Complement ( B )
¿ A−B

When ADD / ¿ ¿ = 0, the XOR gates do not change the bits of B.

Thus,
S= A +B+ 0
¿ A+ B

Exercise:
Draw the truth table of a half-subtractor that computes X −Y . Find the simplified expressions for the difference ( D )
and borrow ( Bo) outputs. Draw the logic diagram of the half-subtractor.
Draw the truth table of a full-subtractor and find the simplified expressions for the difference ( D ) and borrow ( Bo)
outputs. Draw the logic diagram of the full-subtractor
Prepare a full-subtractor using two half-subtractors and one OR gate. Justify mathematically how it works.
Prepare a 4-bit adder/subtractor circuit using full-subtractors and controlled inverters.

Note:
The carry output of a full-adder is fed as an input to the next full-adder (i.e. corresponding to the next significant bit).
Thus, the sum and carry of a full-adder cannot settle down until all the previous sum and caries are settled down.
Suppose each full-adder takes τ amount of time for its sum and carry to be settled to the desired value. Then a n-bit
ripple-carry-adder needs nτ amount of time to get the final result. Thus, this circuit works slower as the number of
bits increases. Later we shall study a fast adder circuit known as the carry-look-ahead adder.

Overflow and sign:1

Consider a n-bit adder circuit. The adder circuit works for both unsigned and signed numbers unless the sum
overflows.
(1) For unsigned numbers:
A and B are within the range from 0 to 2n−1 .

1
This is a slightly advanced topic
 A+ B should also be less than or equal to 2n−1 .
If A+ B is larger than 2n−1 , then the result overflows (and we cannot get the desired result).
Overflow can be detected (identified) by looking at the carry output from the MSB.
When overflow occurs carry output from the MSB becomes 1.

(2) For signed numbers:

A and B are within the range from −2n−1 to ( 2n−1−1 ) .
A+ B should also be within the range from −2n−1 to ( 2n−1−1 ) .
If A+ B is outside the range, then the result overflows (and we cannot get the desired result).
Overflow can occur only if A and B are of the same sign (positive or negative).
When overflow occurs addition of two positive numbers results in a negative number or vice-versa.

Overflow can be detected (identified) by looking at the carry output from the MSB and second MSB.
Overflow detection circuit: (we leave the justification to the reader):

OverFlow = XOR (Carry from MSB, Carry from second MSB).

When Overflow occurs, the result does not contain the true sum.
But we can always find the sign (positive or negative) of the true sum as
TrueSign =XOR (Overflow, sign-bit of the result)
 Multiplexers (MUX)
2-to-1 Multiplexer:
Inputs: Truth table
(1) Data inputs (d 0 , d 1) s d1 d0 z
z (2) Select input (s) 0 0 0 0
Output: z 0 0 1 1
0 1 0 0
Rule: 0 1 1 1
When s=0, then z=d 0 1 0 0 0
When s=1, then z=d 1 Analogous to a toggle switch 1 0 1 0
1 1 0 1
Symbol
1 1 1 1
Logic diagram:
d 1 d 0=00 d 1 d 0=01 d 1 d 0=11 d 1 d 0=10
s=0 0 1 1 0
z
s=1 0 0 1 1

z=s d 0 + s d 1

Using 2-to-1 MUX as a NOT gate Using 2-to-1 MUX as a AND gate Using 2-to-1 MUX as a OR gate

1 0 y
z z z
0 y 1

x x x
z=s d 0 + s d 1=x ⋅1+ x ⋅0=x z=s d 0 + s d 1=x ⋅0+ xy=xy z=s d 0 + s d 1=x y + x 1=x + y
Thus, multiplexers can be used as universal gates.

2n-to-1 Multiplexer:
Inputs:
(1) n-number of select inputs ( sn−1 , … , s 1 , s 0)
(2) 2n−1-number of data inputs (d 0 , d 1 , … d 2 −1)
n

Output: z

Rule:
Suppose, the binary number represented by sn−1 , … , s 1 , s 0 is k .
Then z=d k.

Symbol

Logic Diagram of a 22 to 1 MUX:

 Decoders
1-to-2 Decoder: Input: A Truth table
Outputs: D 0 , D 1 A D1 D0
0 0 1
Rule: 1 1 0
When A=0, then only D 0=1 , other outputs are zero.
Symbol When A=1, then only D 1=1 , other outputs are zero.

Thus, only one of the outputs is 1, at any time.

n-to-2n Decoder: Input: An−1 , … , A 1 , A0
Outputs: D 0 , D 1 , … D 2 −1
n

Rule:
Suppose, the binary number represented by An−1 , … , A 1 , A0 is k .
Then D k =1, other outputs are zero.
Thus, only one of the outputs is 1, at any time.

Recall minterms m 0 , m1 , … .
Note:
Dk =mk ( A n−1 , … , A 1 , A 0 )

n-to-2n Decoder with Often there may be an additional input called Enable (EN)
Enable input: Rule:
When EN=0
All outputs are zero (irrespective of the inputs An−1 , … , A 1 , A0 )

When EN=1
Suppose, the binary number represented by An−1 , … , A 1 , A0 is k .
Then D k =1, other outputs are zero.
Logic diagram of a 2 to 4 decoder: Truth table
E A1 A0 D0 D1 D2 D3
N
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

D0=EN ⋅ ( A 1 A0 )
D1=EN ⋅ ( A1 A 0 )
D2=EN ⋅ ( A1 A 0 )
D3=EN ⋅ ( A1 A0 )

Combining two n-to-2n decoders to form a (n+1)-to-2(n+1) decoder

Any Boolean function can be implemented with a decoder and an OR gate.
Example: Given z=( w+ x ⋅ y ) ⊕ ( x + y )
Solution:
Truth table: (We did it earlier) Circuit:
w x y z
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
Z=∑ (0 ,1 , 2 ,3 , 5)
m

Demultiplexers
1-to-2n Demultiplexer: A demultiplexer is functionally opposite to a multiplexer
Inputs:
(1) n-number of select inputs ( sn−1 , … , s 1 , s 0)
(2) 1number of data inputs (i)
Output: d 0 , d 1 , … d 2 −1n

Rule:
Suppose, the binary number represented by
sn−1 , … , s 1 , s 0 is k .
Then d k =i. All other outputs are zero.

A demultiplexer is functionally identical to a decoder

Symbol with an EN input:
i≡ EN
sn−1 , … , s 1 , s 0 ≡ An−1 , … , A 1 , A0
d 0 , d 1 , … d 2 −1 ≡ D0 , D 1 , … D2 −1
n n

Encoders
n
2 -to-n Encoder: An encoder is functionally opposite to a decoder.
Input: D 0 , D 1 , … D 2 −1
n

Outputs: Q n−1 , … ,Q 1 , Q0

Constraints: At any moment, exactly one of the 2n inputs will be 1 (logic HIGH),
remaining inputs being 0 (logic LOW)
 Rule:
Suppose, D k =1
Then Q n−1 , … ,Q 1 , Q0 will represent the binary equivalent of k .

Priority Encoders
n
2 -to-n Priority Encoder: A priority encoder is similar to an encoder; however, it allows any number of the
inputs to be HIGH simultaneously.

Input: D 0 , D 1 , … D 2 −1
n

Outputs: Q n−1 , … ,Q 1 , Q0, and DV (Data Valid)

Rule:
(1) If none of the inputs is HIGH then DV (Data valid) will be 0.
(We don’t care about the other outputs)
(2) Suppose, k is the highest (or lowest) number such that D k = HIGH
Then Q n−1 , … ,Q 1 , Q0 will represent the binary equivalent of k .
And DV (Data valid) will be 1.

Example: Prepare the logic diagram for a 8-to-3 (ordinary) encoder.

Truth table: Logic Diagram:
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
For all other (invalid) input combinations X X X
Q2=D 4 + D5 + D6 + D7
Q1=D2 + D3 + D6 + D7
Q0=D 1+ D3 + D5 + D7

Example: Prepare the logic diagram for an 8-to-3 priority encoder where the data input with highest index has the
highest priority.
Truth table:
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 DV Functions that uniquely identify the input
combination
 0 0 0 0 X0 X X0 0 0D7 D6 D 5 D4 D3 D2 D 1 D0
0
0 0 0 0 00 0 00 1 0D7 D6 D 5 D4 D3 D2 D 1 D0
1
0 0 0 0 −¿ 0 0 1
0 0 1 1D7 D6 D 5 D4 D3 D2 D1
0 0 0 0−¿ −¿ 0 1 00 1 1 D7 D6 D 5 D4 D3 D2
0 0 0 −¿ −¿ −¿ 0 1 1
0 1 1 D7 D6 D 5 D4 D3
0 0 0 −¿ −¿ −¿ −¿ 1 0 0
1 1 D7 D6 D 5 D4
0 0 −¿ −¿ −¿ −¿ −¿ 1 0 1
1 1 D7 D6 D 5
0 1 −¿ −¿ −¿ −¿ −¿ −¿ 1 1 0 1 D7 D6

− Indicates both the cases corresponding to 0 and 1 inputs

1 −¿ −¿ −¿ −¿ −¿ −¿ −¿ 1 1 1 1 D7

X Indicates don’t care, we can choose either 0 or 1 as the output depending on our convenience.
Q2=D7 + D7 D6 + D7 D6 D5+ D7 D6 D5 D4
Q1=D7 + D7 D6 + D7 D6 D5 D 4 D3 + D7 D6 D5 D 4 D3 D2
Q0=D 7+ D7 D6 D5 + D7 D6 D 5 D4 D3 + D7 D6 D5 D 4 D 3 D2 D1

DV =D7 D6 D5 D 4 D3 D2 D 1 D0=D 7+ D6+ D5+ D4 + D3 + D2 + D1 + D0

Logic Diagram:

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 ROM (Read Only Memory):

The fuses can be blown off one time only.

Assume that the floating (not connected) inputs of the OR gates behave as if they are connected to logic LOW
inputs.
NOTE: The inputs A0 , A1, … are called the address lines (inputs). The outputs z 0, z 1, … are called data outputs.
Diode Matrix ROM:
Simplified single-line diagram:

For the OR gates, we draw one single line to

represent all 16 input lines.

The x symbol indicates that the corresponding

decoded line is connected to one of the input lines
of the corresponding OR gate.

A ROM is called a Programable Logic Device (PLD). It is Simplified Single-line diagram

made up of a decoder and a programable array of OR The AND gates have fixed (non-programable) inputs
 gates. Let’s look inside the decoder of a small 3-input, 4- indicated as firm dots. The OR gates have programable
output ROM. input connections indicated as crosses.
Thus, a ROM is a PLD which has a fixed set of AND gates followed by a programable set of OR gates.

NOTE: There are two other well-known types of PLDs (Programable logic devices):
PLA (Programable Logic Array) and
PAL (Programable Array Logic)

A PLA is a PLD which has a programable set of AND gates followed by a programable set of OR gates
A PAL is a PLD which has a programable set of AND gates followed by a fixed set of OR gates.

A PLA (Programable Logic Array)2

Floating (not connected) inputs of AND gates behave as if they are connected to logic HIGH level

There are more Complex Programmable Logic Device (CPLD). The most popular programable device is FPGA (Field
Programable Gate Array) which we shall not study here.

2
Taken from M Morris Mano
 Magnitude Comparator3
Given two 4-bit unsigned numbers ( A=A 3 A 2 A 1 A 0 ) and ( B=B3 B 2 B1 B0 ).
We want to check which number is larger or whether they are equal.

Logical Circuit:

Note: x 3= A3 ⊙ B3, x 2= A2 ⊙ B 2, x 1= A1 ⊙ B 1, x 0= A 0 ⊙ B0

If x 3=x 2=x 1=x 0=1 then A=B

A> B means ( A3 =1∧B3=0 )∨( x3 =1∧( A2 =1∧B2=0 ) )

¿ ( x 3=x 2=1∧( A1=1∧B 1=0 ) ) ∨( x 3=x 2=x 1=1∧( A0 =1∧B0=0 ) )

3
Taken from M Morris Mano
 Carry look ahead adder or Fast adder4
Table showing when carries are propagated or generated
Carry Is a Carry Is a Carry Propagated
Carry Input Output Type of Carry Generated Pi
Ai Bi Ci C o=C i+1 Gi
0 0 0 0 None 0 0
0 0 1 0 None 0 0
0 1 0 0 None 0 0
0 1 1 1 Propagate 0 1
1 0 0 0 None 0 0
1 0 1 1 Propagate 0 1
1 1 0 1 Generate 1 0
1 0
Both
(Actually 1. However since G i=1,
1 1 1 1 Generate,
equation (1) below would remain
Propagate
unaffected if we make Pi=0 here )

C i+1=Gi + ( Pi ⋅Ci ) … (1)

G i= A i ⋅ Bi
Pi = A i ⊕ Bi

C 1=G0 + ( P0 ⋅C0 )
C 2=G1+ ( P1 ⋅C 1 )=G1 + P1 G0+ P 1 P0 C 0
C 3=G2 + ( P2 ⋅C 2 )=G 2+ P2 G1+ P2 P1 G0 + P2 P1 P 0 C 0
C 4=G3 + ( P 3 ⋅C 3 )=G3 + P3 G2+ P 3 P2 G1+ P 3 P2 P 1 G0 + P3 P 2 P1 P 0 C 0

Time required for each carry to be settled down

= Time required to generate a G i i.e. and AND operation + Time required for a AND operation + Time required for a
OR operation
This time is quite independent of the number of bits.

Exercise: Find out the time required for each sum bit to be settled down and show that this is quite independent of
the number of bits

Logical Circuit:

4
Taken from the Wikipedia. It is a slightly advanced topic.