VLSI Digital Signal Processing Systems

Text Book

VLSI Digital Signal Processing Systems

Design and Implementation

Keshab K. Parhi, Ph. D.

Department of Electrical and Computer
Engineering
University of Minnesota, MN 55455
 VLSI Digital Signal Processing Systems

Text Book (2/2)

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Prof. Parhi’s Education

B. Tech. (Honors) degree from the Indian Institute of
Technology, Kharagpur (India), in 1982.
M.S.E.E. degree from the EE Department, University
of Pennsylvania, Philadelphia, in 1984.
Ph.D. degree from the EECS Department, University
of California, Berkeley, in 1988.

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Prof. Parhi’s Brief Biography

Keshab Parhi has been with the Department of Electrical & Computer Engineering at the University of
Minnesota, Minneapolis, since 1988, where he was an Assistant Professor from Oct. 1988-June 1992, Associate
Professor from July 1992-June 1995, and has been a Professor since July 1995. Since 2000, He has held the
permanent title of "Distinguished McKnight University Professor" awarded by the Graduate School of the University.
Since 1997, he has held the title of "Edgar F. Johnson Professor" awarded by the College of Science and Engineering.
From July 2008 till August 2011, he served as the Director of Graduate Studies of the Electrical Engineering program.
He has held short term positions in several industries such as IBM T.J. Watson Research Center (Yorktown Heights,
NY), AT&T Bell Laboratories (Holmdel, NJ), NEC Corporation (Miyamae-Ku, Kawasaki, Japan), where he was a
National Science Foundation Japan Fellow, Broadcom Corp., Irvine, CA, and Medtronic Corp., Minneapolis, MN. He
has been a visiting Professor at Delft University (The Netherlands) and Lund University (Sweden).
His research addresses VLSI architecture design and implementation of signal processing, communications and
biomedical systems, error control coders and cryptography architectures, high-speed transceivers, stochastic
computing, secure computing, and molecular/DNA computing. He is also working on intelligent classification of
biomedical signals and images, for applications such as seizure prediction and detection, schizophrenia classification,
biomarkers for mental disorders, brain connectivity, and screening of fundus and optical coherence tomography (OCT)
images for ophthalmic abnormalities. He has published over 550 papers, has authored the text book VLSI Digital
Signal Processing Systems: Design and Implementation ( Wiley, 1999), and is the co-editor (with Takao Nishitani) of
the reference book "Digital Signal Processing for Multimedia Systems" (CRC Press, March 1999). He has coauthored
the research monographsPipelined Adaptive Digital Filters (with Naresh Shanbhag, 1994), Digit-Serial
Computation (with Richard Hartley, 1995) and Pipelined Lattice and Wave Digital Recursive Filters (with Jin-Gyun
Chung, 1996), all published by Springer.
Dr. Parhi is the recipient of numerous awards including the 2013 Distinguished Alumnus Award from IIT, Kharagpur,
India, 2013 Graduate/Professional Teaching Award from the University of Minnesota, 2012 Charles A. Desoer
Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the
American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.
R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 2000. He
has served on the editorial boards of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS —PART I and PART
II, VLSI Systems, Signal Processing, Signal Processing Letters,and Signal Processing Magazine, and served as the
Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS —PART I (2004-2005 term), and
currently serves on the Editorial Board of the Springer Journal of Signal Processing Systems (JSPS). He has served
on technical program committees of IEEE Conferences such as ASAP, ICASSP, ISCAS, Computer Arithmetic Symp.,
Great Lakes Symp. on VLSI, workshop on VLSI Signal Processing, SiPS, Workshop on VLSI in Communications, and
of ASP-DAC, IECS and IWISP conferences. He has served as technical program cochair of the 1995 IEEE VLSI
Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on
Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996-
1998. He served as an elected member of the Board of Governors of the IEEE Circuits and Systems society from
2005 to 2007. He is a Fellow of IEEE (1996). Lan-Da Van VLSI-DSP-0-4
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Reference Book
Peter Pirsch, Architectures for Digital Signal
Processing. Chichester, John Wiley & Sons, 1998.
Mahesh Mehendale and Sunil D. Sherlekar, VLSI
Systhesis of DSP Kernels: Algorithms and
Architectural Transformations. Boston, Kluwer
Academic Publishers, 2001.
S. Y. Kung, VLSI Array Processor. Englewood Cliffs,
NJ: Prentice-Hall, 1988.
Handout.

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Lecture Goal
Introduce the various DSP-related algorithms and
architectures for the VLSI-DSP system designs

Graduate students for one semester

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Lecture Outline
Lecture 1 Introduction to Digital Signal Processing Systems
Lecture 2 Iteration Round
Lecture 3 Pipelining and Parallel Processing
Lecture 4 Retiming
Lecture 5 Unfolding
Lecture 6 Folding
Lecture 7 Algorithmic Strength Reduction in Filters and
Transforms
Lecture 8 Pipelined and Parallel Recursive and Adaptive
Filters
Lecture 9 Low-Power Design
Lecture 10 Programmable Digital Signal Processors
Lecture 11 Introduction to 3D Graphics Processing Flow
Lecture 12 Introduction to GPU Hardware
Lecture 13 Geometry Subsystem Design

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授課方式 & 評分標準

教授授課
評分標準
 期中報告: 30%
 期末計畫: 50% (請選擇一個比賽參加)
 作業: 20%
 出席: 0.25N% (表示全學期點名共N次, 每次點名均出席加
0.25N分, ㄧ次曠課加0.25(N-1)分,兩次曠課加0.25(N-2)分,…
點名施主均沒有出席則不加分)。
 --------------------------------------------------------
 總和: (100+0.25N)%
Material Web-Site:
 http://viplab.cs.nctu.edu.tw/course/VLSI-DSP2015_Fall.htm
Teaching Assistant:
 邱敬捷 (e-mail: ccchiu(at)viplab.cs.nctu.edu.tw 分機: 59283)
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期中報告
研讀期刊論文並報告
研讀課本章節並報告
其它方式 (須與老師討論過)

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期末計畫
Team Work
演算法或架構的改良或論文創作。
創意發揮使用IoT平臺，並參與比賽。

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VLSI Signal Processing System

Design Spectrum (1/2)
Computer arithmetic Processor
 Adder  General purposed processor
 Multiplier  DSP processor
 Inverse square root  Reconfigurable computing
 Division processor
Digital filter 3D Graphics
 Multidimensional filter
 Geometry transformation
 Symmetry filter
 Rasterization/Rendering
Adaptive digital filter
 Z-buffer compression
 LMS/DLMS (Delay LMS) based
 Texture compression
 RLS based
Transform Ear-Aid System
 Multiplier-accumulator based  Adaptive algorithm
 Recursive-filter based  Filter bank
 ROM-based: DA, CORDIC System Security
 Butterfly based

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VLSI Signal Processing System

Design Spectrum (2/2)
MIMO Detection Image Processing
 Grouped Detection Pattern Recognition
 VBLAST Median Filter
 K-Best
Image Reconstruction
Image Projection
Biomedical Computation
Video Processing
 ICA
Compression
 PCA
Block Matching
 HRV
Deblocking filter
ADC Non-numerical operation
 SAR ADC
 Error control coding
 Pipeline ADC  Viterbi Decoder
 Sigma-Delta  Turbo Code
PLL  Polynomial computation
 Dynamic programmable

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Homework
Homework is not “Teamwork”!!
You can discuss with each other but not
“COPY”!!
Don’t miss hard deadline for each homework!!

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My Lab: VLSI Information

Processing (VIP) Research Lab
His research interests are in VLSI algorithms,
architectures, and chips for digital signal processing
(DSP) and biomedical signal processing. This
includes the design of low-power/high-
performance/cost-effective 3-D graphics processing
system, adaptive/learning systems, computer
arithmetic, multidimensional filters, transforms and
IoT applications. He has published more than 50
journal and conference papers in these areas.

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VIP Research Lab (2014)

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VIP Research Lab (2014)

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VIP Research Lab (2009)

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VIP Research Lab (2007)

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