NPTEL Assignment
Week-6
Q1. What should be the sizes of the PMOS and NMOS transistors of a symmetric 3-NAND (3 input Nand
gate) having same falling and rising resistance of 2:1 inverter ?
1. 2, & 3
2. 5, & 2
3. 1, & 2
4. 2, & 10
5. 10, & 2
6. 5, & 10
7. 10, & 5
8. 10, & 10
Solution:-
Q2. What is the typical size of NMOS transistors for an footed 2-NOR (2 input NOR) dynamic gate?
1. 1
2. 2
3. 3
4. 4
5. 0.5
6. 1.5
7. 6
8. 4
Solution:-
Q3. Select the correct option about the following statements-
(i) Compound gate design offers less area and decrease in delay, when compared to multistage design.
(ii) Compound gate design offers less area, but increase in delay, when compared to multistage design.
(iii)Compound gate design offers more Area, but increases in delay, when compared to multistage design.
(iv) Compound gate design offers more area, but decreases in delay, when compared to multistage design.
1. Only i, ii, iii
2. Only i
3. Only ii, iii
4. Only iv
5. Only i, iv
6. Only ii
7. Only i, iii
8. All of the above
Q4. If the gate size of a Pseudo NMOS based 3-NOR (3 – input NOR) gate is 10, what should be the sizes of
NMOS and PMOS transistors respectively?
1. 2/3 & 4/3
2. 4/3 & 2/3
3. 2/3 & 10
4. 10 & 2/3
5. 5 & 10
6. 3 & 2/3
7. 2/3 & 3
8. 10, & 5
Solution:-
Q5. For a Short Channel NMOS transistor of width xW and length 4L/3, what should be x to get the current
same as Benchmark Inverter’s current (width = W and length = L for benchmark inverter) ?.
Given:
Vg = 1V
Vt = 0.3V
Vc,NMOS = 1.04V
1. 1.2
2. 2.6
3. 3
4. 4.44
5. 5.176
6. 8.2
7. 2.9
8. 0.1
Solution:-
Q6. What is the best P/N ratio for 3-NAND (3-Input NAND) gate ?
1. 2:3
2. 4:3
3. 1:1
4. 8:1
5. 2: 2 3
6. 3: 2
7. 2: 3
8. 1:8
Solution:-
Q7. What is the W/L ratio of equivalent pull-down transistor for an asymmetric 2-NAND gate where the two
pull-down transistors are designed to 2W/3, and 2W, as per the long channel current model. Note that both
transistors have 1L channel length.
1. 2W/3:2L
2. 1W:2L
3. 2W:2L
4. 20W:2L
5. 2W:20L
6. 4W:2L
7. 6W:2L
8. 4W:L
Solution:-
Assuming the equivalent transistor to have 2/3W width and xL length, we need to find ‘x’.
Relative width of 2/3W transistor = 2/3 / 2/3 = 1
Relative width of 2W transistor = 2 / 2/3 = 3
Relative length of equivalent transistor ‘x’ = 1/1 + 1/3 = 4/3
So the W/L ratio of equivalent pull-down transistor is 2/3W: 4/3L = 1W:2L
Q8. What is the length of the equivalent transistor if we consider width of equivalent transistor as 3W, for
the following circuit?
1. 2L
2. 6L
3. 3L
4. 4L
5. 3L/4
6. 2L/3
7. 5L/6
8. 9L/4
Solution:-
Given the equivalent transistor to have 3W width and xL length, we need to find ‘x’.
Relative width of 2W transistor = 2 / 3 = 2/3
Relative width of 4W transistor = 4 / 3 = 4/3
Relative length of equivalent transistor ‘x’ = (1 / 2/3) + (1 / 4/3) = 3/2 + 3/4 = 9/4
So the length of the equivalent transistor is 9L/4
Q9. Find the average logical effort of a ganged CMOS NOR gate, which has PMOS size = ⅔, NMOS size = 4/3
and whose output is connected to 4C, where C is unit NMOS capacitance.
1. 1/2
2. 2/3
3. 3/4
4. 4/5
5. 5/6
6. 6/7
7. 7/8
8. 8/9
Solution:-
Q10. Find the size of a k-input pseudo-NMOS NOR gate, whose inputs are driven by 1 unit inverter each. The
output of the NOR gate is connected to a capacitor of capacitance 18C, where C is unit NMOS capacitance.
1. 1
2. 2
3. 3
4. 4
5. 5
6. 6
7. 7
8. 8
Solution:-
Where, H = 18. Then x = 4.
