Lecture 14

Direct memory access

Direct Memory Access (DMA) is a process in which an

external device takes over the control of system bus from the
CPU.
The basic idea of DMA is to transfer blocks of data directly
between memory and peripherals. The data don’t go through
the microprocessor but the data bus is occupied.
DMA is for high-speed data transfer from/to mass storage
peripherals, e.g. hard disk drive, magnetic tape, CD-ROM,
and video controllers. For example, a hard disk may boast a
transfer rate of 5 M bytes per second, i.e.1 byte transmission
every 200 ns.
The transfer rate of DMA controller is limited by the speed of
memory and peripheral devices.
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Lecture 14 Basic process of DMA
The HOLD and HLDA pins are used to receive and acknowledge the
hold request respectively.
Normally the CPU has full control of the system bus. In a DMA
operation, the peripheral takes over bus control temporarily

HOLD is sampled in any clocking cycle

HOLD input has higher priority than INTR or NMI
A DMA read transfers data from the memory to the I/O device, causes
the MRDC and IOWC signals to be activate.
A DMA write transfer’s data from an I/O device
to memory, A DMA write causes the MWTC and IORC signals to both
activate. 2
Lecture 14
DMA controller
DMA controller interfaces with several peripherals that may
request DMA.
The controller decides the priority of simultaneous DMA requests
The controller communicates with the peripheral and the CPU,
and provides memory addresses for data transfer.

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Lecture 14

The 8237 Programmable DMA controller

The 8237 is a special-purpose microprocessor, whose job is high-

speed data transfer between memory and I/O
The 8237 is a 4-channel device. Each channel is dedicated to a
specific Peripheral device and capable of addressing 64 K bytes
section of memory.
The 8237 is capable of DMA transfers at rates up to 1.6M bytes /s

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Lecture 14

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Lecture 14
8237 DMA Controller PIN out

 DREQ0–DREQ3: DMA request inputs are used to request a transfer

for each of the four DMA channels. The polarity of these inputs is
programmable, so they are either active-high or active-low inputs.
 CS: Chip select is an active low input used to select the 8237 as an
I/O device
DACK0–DACK3: DMA channel acknowledge outputs
acknowledge a channel DMA request.
A0–A3 These address pins select an internal register during
programming and also provide part of the DMA transfer address
during a DMA action.
A7-A4: address pins are outputs that provide part of the DMA
transfer address during a DMA operation.
IOR : I/O read is a bidirectional pin used during programming
and during a DMA write cycle.

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Lecture 14
8237 DMA Controller PIN out

IOW : I/O write is a bidirectional pin used during programming

and during a DMA read cycle.
EOP : End-of-process is a bidirectional signal used as an input
to terminate a DMA process or as an output to signal the end of
the DMA transfer.
AEN : Address enable signal enables the DMA address latch
connected to the DB7–DB0 pins on the 8237.
ADSTB : Address strobe functions, it is used by the DMA
controller to latch address bits A15–A8 during the DMA transfer.
HRQ: Hold request is an output that connects to the HOLD input
of the microprocessor in order to request a DMA transfer.
CLK: The Clock Input is used to generate the timing signals
which control 82C37A operations.

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Lecture 14
8237 Internal Registers &
Programming DMA Controller

CAR: The current address register holds a 16-bit memory address used
for the DMA transfer; each channel has its own current address register
for this purpose
CWCR: The current word count register programs, a channel for the
number of bytes (up to 64K) transferred during a DMA action. The
number loaded into this register is one less than the number of bytes
transferred.
BA and BWC : The base address (BA) and base word count (BWC)
registers are used when auto-initialization is selected for a channel. In
auto-initialization mode, these registers are used to reload the CAR and
CWCR after the DMA action is completed.
CR: The command register programs the operation of the 8237 DMA
controller.
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Lecture 14 The Command register (CR)
The CR programs the operation of the 8237 DMA controller.

• Normal timing: The DMA cycle contains 4 Clock periods

• Compressed timing: The DMA cycle contains 2 Clock periods
• Fixed priority: Channel 0 has the highest priority and channel 3 Lowest
• Rotating priority: The most recently serviced channel assumes the lowest
priority 9
 Lecture 14 The Command register cont.

 The "Late Write Selection" is a feature that allows the DMA

controller to delay the memory write operation until the end of the
DMA transfer cycle. Needed when accessing slow memory devices
or peripherals.
 The "Extended Write Selection" is a feature that allows the DMA
controller to extend the duration of the memory write operation.
Needed when accessing memory-mapped I/O devices or other
peripherals with specific timing requirements.

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Lecture 14 The mode register (MR)
The mode register programs the mode of operation for a channel.

• Demand mode: until an external EOP is input or DREQ input becomes inactive.
• Single mode: release Hold after each byte of data transferred.
• Block mode: automatically transfers the number of bytes indicated by the count
register
• Cascade mode: is used when more than one DMA is present in the system.
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Lecture 14
The bus request register
The bus request register is used to request a DMA transfer via software.

The Mask request register

The mask register set/reset sets or clears the channel mask.

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Lecture 14 The MSR (Model-Specific Register) request register

The MSR register clears or sets all of the masks with one command
instead of individual channels, as with the MRSR

The SR request register

The status register shows status of each DMA channel.

The TC bits indicate if the channel has reached its terminal count (transferred all its bytes). 13
Lecture 14
More than one 8237 Connected to Microprocessor

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Lecture 14
8237 System Interface

Latch B
A16-A31

During a DMA action (AEN=1), the DMA

controller provide the address A8-A15 while
A0-A7 connected directly
The DMA controller provides control signals.
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Lecture 14 Software Commands
Three software commands are used to control the operation of the
8237.
 A simple output to the correct port number enables the
software command
I. Master clear
This command disables all channels
II. Clear mask register
Enables all four DMA channels.
III. Clear the first/last flip-flop
 Clears the first/last (F/L) flip-flop within 8237.
 The F/L flip-flop selects which byte (low or high order) is
read/written in the current address and current count
registers.
• If F/L = 0, the low-order byte is selected
• If F/L = 1, the high-order byte is selected
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Lecture 14

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 Programming the Address and Count Registers

The table below shows I/O port locations for programming the
count and address registers for each channel.

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 Lecture 14
Four steps are required to program the 8237

(1) The F/L flip-flop is cleared using a clear F/L command

(2) The channel is disabled
(3) LSB & MSB of the address are programmed
(4) LSB & MSB of the count are programmed

 Example:
Interfacing DMA 8237 Controller to 80386 Microprocessor at I/O
ports 0700H- 07F0H for DMA controller and I/O ports 0100H-
01F0H for latch B.

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Lecture 14 I/O ports 0700H- 07F0H

A11 A10 A9 A8 A7 A6 A5 A4
790
7B0
780
7E0
7F0
7C0
100
700
720
730

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 Lecture 14
Sample Memory-to-Memory DMA Transfer
Suppose contents of memory locations 10000H–13FFFH are to be
transferred to locations 14000H–17FFFH. (Real Mode).
Shows the software required to initialize the 8237 and program
latch B in the block diagram indicated above for this DMA
transfer

Software required initializing the 8237 and programming latch B

; Calling parameter
; SI = Source address;
; DI = destination address;
; Cx = Count
; ES = Segment of source and destination
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Lecture 14

LatchB EQU 100H ; Latch B

Clear_F EQU 7C0H ; F/L
CH0_A EQU 700H ; Channel 0 Address
CH1_A EQU 720H ; Channel 1 Address
CH1_A EQU 730H ; Channel 1 Count
MODE EQU 7B0H ; Mode register
CMMD EQU 780H ; Command register
MASKS EQU 7F0H ; Masks register
REQ EQU 790H ; Request register
Status EQU 780H ; Status register

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Lecture 14
; Program Latch
MOV AX, ES
MOV AL, AH
SHR AL, 4
OUT LatchB, AL

; Clear F/L;
OUT Clear_F, AL

; Program Source Address

MOV AX, ES
SHL AX, 4
ADD AX, SI
OUT Ch 0_A, AL
MOV AL, AH
OUT Ch 0_A, AL

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Lecture 14
; Program Destination Address
MOV AX, ES
SHL AX, 4
ADD AX, DI
OUT Ch 1_A, AL
MOV AL, AH
OUT Ch 1_A, AL
; Program Count
MOV AX, CX
DEC AX
OUT Ch 1_C, AL
MOV AL, AH
OUT Ch 1_C, AL

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Lecture 14

; Program Mode
MOV AX, 88H
OUT MODE, AL
MOV AL, 85H
OUT MODE, AL

; Enable memory to memory Transfer

MOV AX, 1H
OUT CMMD, AL

; Unmask Channel 0
MOV AX, 0EH
OUT MASKS, AL

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Lecture 14

; Start DMA Transfer

MOV AX, 04H
OUT REQ, AL

; Wait until DMA complete

Repeat
IN AL, STATS
UNTIL AL& 1
RET

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