The document outlines an assignment task involving the simulation of a D Latch and a D Flip-Flop (D FF) with specified inputs. It requires filling out a table of outputs based on the given D inputs, enable signals, and clock signals, along with creating a video for both outputs. The table details the Q outputs for each scenario, indicating changes and no changes in output states.
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A2 DLD
The document outlines an assignment task involving the simulation of a D Latch and a D Flip-Flop (D FF) with specified inputs. It requires filling out a table of outputs based on the given D inputs, enable signals, and clock signals, along with creating a video for both outputs. The table details the Q outputs for each scenario, indicating changes and no changes in output states.