(PART A – 2 Marks)

UNIT – I
 Questions

Design a half subtractor in gate level modeling using Verilog HDL.

module halfsubtractor( D,Bo,A,B);
input A,B;
output D,Bo;
wire w1;
QA101
xor (D,A,B);
not (w1,B);
and (Bo,B,w1);
endmodule

Write a Verilog code for D-Flip-flop using behavioral modelling

module DFlipFlop (D,clk, reset,Q);
input D; // Data input
input clk; // clock input
input reset; // synchronous reset
output reg Q; // output Q
always @(posedge clk)
QA102 begin
if(reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule
Compare Data flow and Behavioral Modeling in Verilog HDL.
Dataflow Modeling Behavioral Modeling

At this level, the module is designed This is the highest level of abstraction
by specifying the data flow. The provided by Verilog HDL. A module can
QA103
designer is be implemented in terms of the desired
aware of how data flows between design algorithm without concern for the
hardware registers and how the data is hardware implementation details.
processed in the design. Designing at this level is very similar to C
programming.
 Questions

Design a half subtractor in gate level modeling using Verilog HDL.

module halfsubtractor( D,Bo,A,B);
input A,B;
output D,Bo;
wire w1;
QA101
xor (D,A,B);
not (w1,B);
and (Bo,B,w1);
endmodule

Write a Verilog code for D-Flip-flop using behavioral modelling

module DFlipFlop (D,clk, reset,Q);
input D; // Data input
input clk; // clock input
input reset; // synchronous reset
output reg Q; // output Q
always @(posedge clk)
QA102 begin
if(reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule
Name the different data types in Verilog HDL.
Input
Output
QA104 * Inout
Wire
Reg
 Questions

Design a half subtractor in gate level modeling using Verilog HDL.

module halfsubtractor( D,Bo,A,B);
input A,B;
output D,Bo;
wire w1;
QA101
xor (D,A,B);
not (w1,B);
and (Bo,B,w1);
endmodule

Write a Verilog code for D-Flip-flop using behavioral modelling

module DFlipFlop (D,clk, reset,Q);
input D; // Data input
input clk; // clock input
input reset; // synchronous reset
output reg Q; // output Q
always @(posedge clk)
QA102 begin
if(reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule
Write a Verilog code for 2 to 1 multiplexer using conditional operator.
module mux_2to1_dataflow (Y,A,B,S);
input A,B,S;
QA105* output Y;
assign Y = S?A:B;
endmodule
 UNIT – II

Q. No Questions

QA201* Differentiate task in Verilog.

 Define UDP and what is the structure of UDP?

QA202

QA203 List out the keywords used for switch primitives in switch level modeling?
 MOS switches
nmos
pmos
cmos
 Bidirectional switches
 tran
tranif0
tranif1
 Resistive switches
rnmos
rpmos
rcmos
 Resitive bidirectional switches
rtran
rtranif0
rtranif1
Write Verilog code for CMOS inverter in switch level modeling.
module my_not (input x, output f);
// internal declaration
supply1 vdd;
QA204 supply0 gnd;
// NOT gate body
pmos p1 (f, vdd, x);
nmos n1 (f, gnd, x);
endmodule
QA205 Differentiate the timing checks $setup and $hold.
 UNIT – III

Q. No Questions

What is the value of 11011 after left shift by 2?

QA301* Shift by 1 = 01101

Shift by 2 = 00110

QA302 Write the syntax for NEXT statement in VHDL

Loop
Statement1;
NEXT or NEXT WHEN condition;
Statement2;
 …..
END LOOP;

Give an example of how a test bench is used ?

QA303*
A test bench or testing workbench is an environment used to verify the correctness or soundness of a design or model.

Write the VHDL code for half subtractor using dataflow modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALF_SUB is
port(A, B : in std_logic;
QA304 DIFF, Borrow : out std_logic);
end HALF_SUB;

architecture HS_DATAFLOW of HALF_SUB is

begin

DIFF <= A xor B;

Borrow <= (not A) and B;

end HS_ DATAFLOW;

Write the VHDL code to realize a 2 × 1 multiplexer.

QA305
 Data Flow Modeling: Behavioral Modeling:
entity Mux2x1 is entity Mux2x1 is
port( A,B,S: in std_logic; port( A,B,S: in std_logic;
F: out std_logic); F: out std_logic);
end Mux2x1; end Mux2x1;

architecture Dataflow of Mux2x1 is architecture Behavioral of Mux2x1 is

begin begin
F <= ((not S) and A) or (S and B); process(A,B,S)
end Dataflow; begin
if (S='0') then
F<=A;
else
F<=B;
end if;
end Process; end Behavioral;

UNIT – IV

Q. No Questions

QA401 Differentiate a function and procedure in VHDL.

Function Procedure
Functions are used to describe frequently used These are used to partition large behavioral
sequential algorithms that return a single value that is descriptions into modular sections.
returned to the calling program using a return
statement.
Eg., resolution functions, type conversion functions. Eg., Arithmetic Unit, Memories, Control Unit, etc
 These are usually used for computing a single value. Procedures can return zero or more values using
parameters of mode out and inout
Functions are used to compute values that are A process that calls a procedure with a wait statement
available instantaneously. cannot have a sensitivity list. This follows from the
fact that a process cannot be sensitive to signals and
also be made to wait simultaneously.
A function cannot be made to wait. A procedure body can have a wait statement. Hence
any variables declared in the procedure retain their
values through this wait period and cease to exist only
when the procedure terminates.
The general syntax of a subprogram specification for a Syntax for a procedure body
function body is
procedure procedure-name ( parameter-list )
function function-name (parameter-
list) return return-type The parameter-list specifies the list of formal
parameters for the procedure. Parameters may be
The parameter-list describes the list of formal constants, variables, or signals and their modes may
parameters for the function. The only mode allowed be in, out, or inout.
for the parameters is mode in. Also, only constants
and signal objects can be passed in as parameters.

How the Generics is useful in VHDL code?

The purpose of defining a generic statement within an entity is to confer more flexibility and reusability. A generic
QA402
parameter is basically used globally with some value. Whenever one want to reuse same thing again and again then
defining it as a generic parameter will be useful rather than defining it again and again.

QA403 Define package and what is the need of package declaration?

A package provides a convenient mechanism to store and share declarations that are common across many design
units. Packages in VHDL consists of two parts:
1. Package declaration section

2. Package body.

The package declaration defines the interface for the package, much the same way that the entity defines the interface
 for a model.

A package declaration contains a set of declarations that may possibly be shared by many design units. It defines the
interface to the package, that is, it defines items that can be made visible to other design units, for example, a function
declaration.

configuration_specification ⇐
Write the syntax for configuration specification.

for component_specification
QA404 binding_indication ;
{ use vunit verification_unit_name { , … } ; }
end for ;
This is similar to the form in a component configuration, but without the nested configuration for the architecture.
Define component and give its syntax.
A component declaration declares a virtual design entity interface that may be used in component instantiation
statement.
QA405 component component_name [ is ]
generic (generic_list);
port (port_list);
end component component_name;

UNIT V

Q. No Questions

What is meant by logic synthesis?

Logic synthesis is the process of converting a high-level description of design into an optimized gate-level
QA501
representation. Logic synthesis uses a standard cell library which have simple cells, such as basic logic gates like and,
or, and nor, or macro cells, such as adder, muxes, memory, and flip-flops
How should be case statement synthesized ?.
QA502
Case statement synthesized as multiplexer.

QA503* List out any five synthesizable Verilog constructs.

 • “module … endmodule”

• Instantiation of a synthesizable module

• “always” construct

• “assign” statements

• Built-in gate primitives

• User defined primitives – combinational only

• “parameter” statement
Differentiate simulation and synthesis in HDL.

Simulation Synthesis
Process of describing the behavior of the process of constructing a physical system
circuit using input signals output signal and from an abstract descriptions of predefined
delays set of building blocks.
QA504*
Uses the sensitivity list to figure out when to Ignores sensitivity list
run the process
Simulation is used to verify the functionality Synthesis is used for
of the circuit convert VHDL description to match the
target technology.
Define technology mapping and optimization.

Technology mapping is an important task of logic synthesis of digital circuits. It consists of transforming a multiple-
*
QA505 level Boolean network into an interconnection of primitive gates that belong to a pre-specified library.

Optimization: Synthesis optimizes the design for various metrics, such as area, power consumption, and timing. By
leveraging advanced algorithms, it improves the performance and efficiency of the resulting netlist.

PART B – 13 Marks - Either Or Type)

 UNIT - I

Q. No Questions

QB101 (a) Design the 8-Ripple carry Adder using Structural level modeling in Verilog HDL

// Verilog code for 1-bit full adder

module fulladder(S, Co, X, Y, Ci);
input X, Y, Ci;
output S, Co;
wire w1,w2,w3;
//Structural code for one bit full adder
xor G1(w1, X, Y);
xor G2(S, w1, Ci);
and G3(w2, w1, Ci);
and G4(w3, X, Y);
or G5(Co, w2, w3);
endmodule
 // Verilog project: Verilog code for 4-bit ripple-carry adder

module rippe_adder(S, Cout, X, Y,Cin);

input [7:0] X, Y;// Two 4-bit inputs
input Cin;
output [7:0] S;
output Cout;
wire w1, w2, w3;
// instantiating 4 1-bit full adders in Verilog
fulladder u1(S[0], w1,X[0], Y[0], Cin);
fulladder u2(S[1], w2,X[1], Y[1], w1);
fulladder u3(S[2], w3,X[2], Y[2], w2);
fulladder u4(S[3], w4,X[3], Y[3], w3);
fulladder u1(S[0], w5,X[4], Y[4], w4);
fulladder u2(S[1], w6,X[5], Y[5], w5);
fulladder u3(S[2], w7,X[6], Y[6], w6);
fulladder u4(S[3], Cout,X[7], Y[7],w7);

endmodule

(Or)
QB101 (b) Build a JK flip flop and SR Flip flop circuit using an always statement with necessary logic diagram using
Behavioral modeling in Verilog HDL.
JK Flip flop Verilog code : (7 Marks)
module JK_flipflop (q, q_bar, j,k, clk, reset);
input j,k,clk, reset;
output reg q;
output q_bar;
// always@(posedge clk or negedge reset) // for asynchronous reset
always@(posedge clk) begin // for synchronous reset
if(!reset)
q <= 0;
else
begin
case({j,k})
 2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // Toggle
endcase
end
end
assign q_bar = ~q;
endmodule

SR Flip flop Verilog code : (6 Marks)

module SR_flipflop (q, q_bar, s,r, clk, reset);
input s,r,clk, reset;
output reg q;
output q_bar;
// always@(posedge clk or negedge reset) // for asynchronous reset
always@(posedge clk) begin // for synchronous reset
if(!reset)
q <= 0;
else
begin
case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign q_bar = ~q;
endmodule

Interpret the operator types in data flow modelling with an example also write the 4:1 mux using conditional
QB102 (a) operators.
Types of Operators : 9 Marks
 Arithmetic Operator
Logical operator
Relational Operator
Equality Operator
Bitwise Operator
Reduction Operator
Shift Operator
Concatenation Operator
Conditional Operator

4:1 mux using conditional operator - 4 Marks

module m41(y, a, b, c, d, s0, s1);
output out;
input a, b, c, d, s0, s1;
assign y = s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule
(Or)
QB102 (b) (i) Design the 2:4 Decoder circuit using gate level modelling with relevant diagram
(8 Marks)
(ii) Provide a Verilog code for a 3-bit even parity generator module. (5)
i)
Diagram - 2 Marks
Verilog Code - 6 Marks
module decoder_2_to_4(d0,d1,d2,d3, a0, a1);
input a0, a1;
output d0,d1,d2,d3;
wire an0,an1;
not(an0,a0),(an1,a1);
and(d0,an0,an1),(d1,a0,an1),(d2,an0,a1),(d3,a0,a1);
endmodule
ii) 3-bit even parity generator module
module parity(
input x,y,z,
output result);
wire w;
 xor g1(w,x,y);
xor (result,w,z); // SIMPLE XOR OPERATION : Gate Level Modeling
endmodule

QB103 (a)* (i)Implement a Verilog-based full adder circuit by instantiating two half adder modules, ensuring that it
correctly performs binary addition for three input bits. (Use structural level modeling) (7)
(ii) Design a priority encoder circuit for 8 inputs and 3 outputs. Provide the Verilog code for the design using
case statement. (6)

(i)

//Half adder using Gatelevel modeling

module half_adder(a,b,sum,carry);
input a,b;
output sum,carry; // sum and carry
or(sum,a,b);
and(carry,a,b);
endmodule
//Full adder using half adder
module full_adder(s,c,a,b,c);
input a,b,c,
output s,c;
wire c1,c2,s1;
half_adder ha0(s1,c1,a,b);
half_adder ha1(s,c2,c,s1);
assign c = c1 | c2 ;
endmodule

(ii) module pri_Enc(dout, din);

input [7:0]din;
output reg [2:0]dout;
 always @ (din)
case (din)
8’b 1xxx xxxx : dout = 3’b111;
8’b 01xx xxxx : dout = 3’b110;
8’b 001x xxxx : dout = 3’b101;
8’b 0001 xxxx : dout = 3’b100;
8’b 0000 1xxx : dout = 3’b011;
8’b 0000 01xx : dout = 3’b010;
8’b 0000 001x : dout = 3’b001;
8’b 0000 0001 : dout = 3’b000;;
default : dout = 3’bxxx;
endcase
endmodule

(Or)
103 b) (i)Design 4-bit ripple counter using behavioral modeling of Verilog code (8)
(ii) Design a Serial In Serial Out Shift Register using Verilog (5)

i) 4-bit ripple counter

module D_FF(q,d,clk,reset);

input d,clk,reset;

output reg q;

always@(negedge clk or posedge reset)

begin

if(reset)

q<=1'b0;

else

q<=d;

end

endmodule

module T_FF(q,clk,reset);

input clk,reset;

output q;

wire d;

D_FF dff0(q,d,clk,reset);

not n1(d,q);

endmodule

module ripple_counter_4_bit(q,clk,reset);

input clk,reset;

output[3:0]q;

T_FF tff0(q[0],clk,reset);

T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);

T_FF tff3(q[3],q[2],reset);

endmodule

ii) SISO

module sisomod(clk,clear,si,so);

input clk,si,clear;

output so;

reg so;

reg [3:0] tmp;

always @(posedge clk )

begin

if (clear)

tmp <= 4’b0000;

else

tmp <= tmp << 1;

tmp[0] <= si;

 so = tmp[3];

end

endmodule

UNIT II

Q. No Questions

Infer the following in detail with an example.

QB201 (a)
Assign and Deassign statement With Program Example(7 Marks)
(i)
(ii) Force and Release With Program Example (6 Marks)
 (Or)
QB201 (b) (i)Determine how the sequential UDPs differ from Combinational UDP? (4 Marks)
–Truth table for combinational functions.
– State table for sequential functions.
For combinational functions, truth table entries are specified as:
<input1> <input2> ... <inputN> : <output>;
• For sequential functions, state table entries are specified as:
<input1> <input2> ... <inputN> : <present_state> : <next_state>
• The input terminals to a UDP can only be scalar variables.
– Multiple input terminals can be used.
– The input terminals are declared as “input”.
– Input entries in the table must be in the same order as the “input” terminal list.
• Only one scalar output terminal must be used.
– The output terminal must appear in the beginning of the terminal list.
– For combinational UDPs, the output terminal is declared as “output”.
– For sequential UDPs, the output terminal is declared as “reg”.
• For sequential UDPs, the state can be initialized with an “initial” statement.
– This is optional.

(ii)Design 4:1 multiplexer and 4 input AND function with UDP using Verilog HDL. (9Marks)

// A 4-to-1 multiplexer
primitive udp_mux41 (f, s0, s1, i0, i1, i2, i3);
input s0, s1, i0, i1, i2, i3;
output f;
table
// s0 s1 i0 i1 i2 i3 : f
0 0 0 ? ? ? : 0;
0 0 1 ? ? ? : 1;
1 0 ? 0 ? ? : 0;
1 0 ? 1 ? ? : 1;
0 1 ? ? 0 ? : 0;
0 1 ? ? 1 ? : 1;
1 1 ? ? ? 0 : 0;
1 1 ? ? ? 1 : 1;
endtable
endprimitive

// A 4-input AND function

primitive udp_and4 (f, a, b, c, d);
input a, b, c, d;
output f;
table
// a b c d f
0 ? ? ? : 0;
? 0 ? ? : 0;
? ? 0 ? : 0;
 ? ? ? 0 : 0;
1 1 1 1 : 1;
endtable
endprimitive

QB202 (a) (i)Explain the type of delay models in detail with examples.
(i) Lumped delay model (4)

(ii) Distributed delay model (4)

(iii) Pin – to – pin delay model (5)
 (Or)
QB202 (b) (i)Describe about Function and its syntax. (5)
 Function Definition(2Marks)
 Syntax(3Marks)
(ii) Write a Verilog code for implementing a 4:1 multiplexer circuit using a 2:1 mux with Function-based approach (8)
 .
Describe the types of procedural continuous assignments used in useful modeling techniques with relevant Verilog
examples.

(i) Assign and Deassign statement With Program Example (7 Marks)

QB203 (a) (ii) Force and Release With Program Example (6 Marks)

(Or)

QB203 (b)* Write the switch level Verilog code (i) 2 input XOR gate (ii) 2 input NOR gate.
(i) Xor gate (7)
 (ii) NOR gate (6)

UNIT – III

Q. No Questions
QB301 (a)* Develop VHDL code for an 8 to 3 priority encoder using behavior modeling.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity PRI_EN is
port (A: in STD_LOGIC_VECTOR (7 downto 0);
Y: out STD_LOGIC_VECTOR (2 downto 0));
end PRI_EN;
architecture behav of PRI_EN is
 begin
process (A)
begin
If (A(7) = '1') then Y <= "111";
elsif (A(6) = '1') then Y <= "110";
elsif (A(5) = '1') then Y <= "101";
elsif (A(4) = '1') then Y <= "100";
elsif (A(3) = '1') then Y <= "011";
elsif (A(2) = '1') then Y <= "010";
elsif (A(1) = '1') then Y <= "001";
elsif (A(0) = '1') then Y <= "000";
else
Y <= "XXX";
end if ;
end process ;
end behav;

Or

Write VHDL code for a 8:1 Multiplexer and 1:8 demultiplexer Gate and Dataflow modeling.
QB 301 (b)*
8:1 Mux
1 to 8 deMux:
 (i)Write VHDL code for 7 segment display using case statement. (7)
(ii)Write VHDL code for JK flip-flop using behavior modeling. (6)
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is
port (J, K, Clock, Reset : in std_logic;
Q : out std_logic);
end JK_FF;
architecture sig of JK_FF is
begin
process (Clock, Reset) is
begin
if (Reset = '0') then
QB302 (a)*
Q <= '0';
elsif (Clock=’1’ and Clock’event) then
case ((J&K)) is
when "11" => Q <= not Q;
when "10" => Q <= '1';
when "01" => Q <= '0';
when “00”=> Q<=Q;
when others => ‘0’;
end case;
end if;
end process;
end sig;

(or)

QB302 (b)* Illustrate the following with example.

(i) If Statement (7)
(ii) Case Statement (6)

(i)
Syntax
if (boolean-expression) then
sequential-statements
[ elsif boolean-expression then -- elsif clause; if stmt can have 0 or
sequential-statements ] -- more elsif clauses.
[ else -- else clause. sequential-statements ]
end if;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer_4_1 is
port(
din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC
);
end multiplexer_4_1;

architecture multiplexer4_1_arc of multiplexer_4_1 is

begin
mux : process (din,sel) is
begin
if (sel="00") then
dout <= din(3);
elsif (sel="01") then
dout <= din(2);
elsif (sel="10") then
dout <= din(1);
else
dout <= din(0);
end if;
end process mux;
end multiplexer4_1_arc;

(ii)
library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
port(a : in std_logic_vector (1 downto 0);
d : out std_logic_vector (3 downto 0));
end decoder;
architecture bhv of decoder is
begin
process(a)
begin
case a is
when "00" => d <= "0001";
when "01" => d <= "0010";
when "10" => d <= "0100";
when "11" => d <= "1000";
end case;
end process;
end bhv;
QB303 (a) Develop a VHDL code for Modulus 10 counter.

Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;

entity Modulus_CTR is
port (clk, rst: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end Modulus_CTR;

architecture Modulus_CTR_behav of Modulus_CTR is

begin
Process(clk,rst)
begin
If(clk = ‘1’ and clk’event) then
If(rst or count =”1001”) then
Count <=”0000”;
else
Count <= count + 1;
end if;
end if;
end process;
end Modulus_CTR_behav;

Test Bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_counters is
end tb_counters;

architecture Behavioral of tb_counters is

component Modulus_CTR is
port (clk, rst: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end Modulus_CTR;

signal rst_tb,clk_tb: std_logic;

signal count_tb:std_logic_vector(3 downto 0);

begin
dut: Modulus_CTR port map (clk => clk_tb, rst=>rst_tb, count =>
count_tb);
-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst_tb <= '1';
wait for 20 ns;
rst_tb <= '0';
 wait;
end process;
end Behavioral;

(Or)

(Or)

QB303 (b)* (i)Design SR flip flop in behavior modeling using if statement in VHDL. (7)
(ii)Design a 2 to 4 decoder in behavior modeling using case statement in VHDL.(6)

(i)
VHDL Code for SR FlipFlop
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity SR_FF is
PORT( S,R,CLOCK: in std_logic;
Q, QBAR: out std_logic);
end SR_FF;

Architecture behavioral of SR_FF is

begin
PROCESS(CLOCK)
variable tmp: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(S='0' and R='0')then
tmp:=tmp;
elsif(S='1' and R='1')then
tmp:='Z';
elsif(S='0' and R='1')then
 tmp:='0';
else
tmp:='1';
end if;
end if;
Q <= tmp;
QBAR <= not tmp;
end PROCESS;
end behavioral;
(ii)
library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
port(a : in std_logic_vector (1 downto 0);
d : out std_logic_vector (3 downto 0));
end decoder;
architecture bhv of decoder is
begin
process(a)
begin
case a is
when "00" => d <= "0001";
when "01" => d <= "0010";
when "10" => d <= "0100";
when "11" => d <= "1000";
end case;
end process;
end bhv;

UNIT IV

Q. No Questions
 Describe in detail about Generics in VHDL with a suitable example.
Definition for Generic Constant (3 Marks)
QB401 (a)*
Definition for Generic Statements (3 Marks)
Explanation of these with example (7 Marks)
(Or)
Develop a VHDL code for 8-bit counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity counter is
Port ( rst,clk,up_dwn : in std_logic;
count: out std_logic_vector(7 downto 0));
end counter;
architecture count_arch of counter is
QB401 (b) begin
process(rst,clk)
begin
if (rst = ‘1’) then count <= “0000”;
elsif (clk’event and clk = ‘0’) then
if (up_dwn = ‘1’) then count <= count – 1;
else count <= count + 1;
end if;
end if;
end process;
end count_arch;
Illustrate the concepts of procedure and function with appropriate examples.
Procedure & Function Syntax (3 Marks)
QB402 (a)
Procedure & Function Explanation (5 Marks)
Procedure & Function Example (5 Marks)
(Or)
QB402 (b) Design a 10 bit adder using VHDL by instantiating fulladder.
library IEEE
use IEEE.STD_LOGIC_1164.all;
 entity adder_10bit is
port(a : in STD_LOGIC_VECTOR(9 downto 0); b : in STD_LOGIC_VECTOR(9 downto 0);
sum : out STD_LOGIC_VECTOR(9 downto 0) ; carry : out STD_LOGIC);
end adder_10bit;
architecture adder_10bit_arc of adder_4bit is
Component fa is
port (a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC;
sum : out STD_LOGIC; carry : out STD_LOGIC);
end component;
signal s : std_logic_vector (8 downto 0);
begin
u0 : fa port map (a(0),b(0),'0',sum(0),s(0));
u1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
u2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
u3 : fa port map (a(3),b(3),s(2),sum(3),s(3));
u4 : fa port map (a(4),b(4),s(3),sum(4),s(4));
u5 : fa port map (a(5),b(5),s(4),sum(5),s(5));
u6 : fa port map (a(6),b(6),s(5),sum(6),s(6));
u7 : fa port map (a(7),b(7),s(6),sum(7), s(7));
u8 : fa port map (a(8),b(8),s(7),sum(8),s(8));
u9 : fa port map (a(9),b(9),s(8),sum(9),carry);
end adder_10bit_arc;

use IEEE.STD_LOGIC_1164.all;
entity fa is
port (a : in STD_LOGIC;b : in STD_LOGIC;c : in STD_LOGIC;
sum : out STD_LOGIC; carry : out STD_LOGIC);
end fa;
architecture fa_arc of fa is
begin
sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
end fa_arc

QB403 (a) Explain the package declaration and package body in detail.
Package declaration Syntax and Example – (7 Marks)
 Package body syntax and Example – (6 Marks)
(Or)

(Or)
Discuss about basic configuration declarations and write an example for the configuration of a four-bit register.

configuration_declaration ⇐
Configuration Declarations (7Marks)

configuration identifier of entity_name is

for architecture_name
{ for component_specification
binding_indication ;
end for ; }
end for ;

component_specification ⇐
end [ configuration ] [ identifier ] ;

binding_indication ⇐ use entity entity_name [ ( architecture_identifier ) ]

( instantiation_label { , … } I others I all ) : component_name
QB403 (b)
Configuration of a four-bit register (6Marks)
library star_lib;
use star_lib.edge_triggered_Dff;
configuration reg4_gate_level of reg4 is
for struct -- architecture of reg4
for bit0 : flipflop
use entity edge_triggered_Dff(hi_fanout);
end for;
for others : flipflop
use entity edge_triggered_Dff(basic);
end for;
end for; -- end of architecture struct
end configuration reg4_gate_level;
 UNIT V

Q. No Questions

Illustrate about Verilog HDL synthesis and draw the logic synthesis design flow from RTL to Gates.
Verilog HDL Synthesis (7 Marks)
Verilog Constructs
Verilog Operators
Interpretation of a Few Verilog Constructs
Synthesis Design Flow (6 Marks)
RTL to Gates

QB501 (a)*

(Or)
 Describe useful modelling tips for logic synthesis.
Verilog coding styles(13Marks)
 Use meaningful names for signals and variables
 Avoid mixing positive and negative edge triggered flipflops
 Use bsic building blocks vs use continuous assign statements
QB501 (b)*
 Instantiate multiplexers vs use if-else or case statements
 Use parenthesis to optimize logic structure
 Use arithmetic operators *,/,and % vs Design buiding blocks
 Becareful with multiple assignments to the same variables
Define if-else or case statements explicitly
Write short notes on horizontal partitioning and vertical partitioning.

Horizontal Partitioning Vertical Partitioning

Explanation[4 Marks] Explanation[3 Marks]
Diagram[3 Marks] Diagram[3 Marks]

QB502 (a)*

(or)
 Describe about the synthesis of combinational circuits with a suitable example.
Styles for Synthesizable Combinational Logic (10Marks)
• The possible styles for modeling combinational logic with example.
– Netlist of Verilog built-in primitives like gate instances (AND, OR, NAND, etc.).
– Combinational UDP (not all synthesis tools support this).
– Continuous assignments.
– Functions.
– Behavioral statements.
– Tasks without event or delay control.
QB502 (b)*
– Interconnected modules of one or more of the above.
synthesis rules for combinational logic.(3Marks)
The output of a combinational logic circuit at time t should depend only upon the inputs applied at time t.
• Rules to be followed:
– Avoid technology dependent modeling (i.e. implement functionality, not timing).
– There must not be any feedback in the combinational circuit.
– For “if…else” or “case” constructs, the output of the combinational function must be specified for all possible input
cases.
– If the rules the not followed, the circuit may be synthesized as sequential.

Describe about the synthesis of sequential circuits with a suitable example.(13 Marks)

Design Specification
Circuit Requirements
Finite State Machine (State Diagram)
Verilog Description (Program of FSM)
QB503 (a)*
Technology Library
Design Constraints
Logic Synthesis
Optimized Gate Level Netlist(Gate Level Diagram)
Verification

(Or)
*
QB503 (b) Write a Verilog module to implement a J-K master-slave flip-flop with asynchronous set and reset at the gate
level. The module will take as arguments the following:
1-bit data input “J”, 1-bit data input “K”, 1-bit clock input “Clk”, 1-bit data input “Set”, 1-bit data input “Rst”,
1-bit output “Q” and 1-bit output “Qb”
Gate level Diagram (4 Marks)
Verilog Description (9 Marks)
 (PART C – 15 Marks - Either Or Type)

UNIT - I

Q. No Questions

QC101 (a) Develop and verify an HDL behavioral description of 16-bit arithmetic logic unit (ALU). The circuit has 4-bit select bus (Sel),
sixteen-bit input A[15:0] and B[15:0], and an 16-bit output Y.

/* ALU Arithmetic and Logic Operations case(ALU_Sel)

|ALU_Sel| ALU Operation 4'b0000: // Addition
| 0000 | Y = A + B; {CarryOut, Y} = A + B ;
| 0001 | Y = A - B; 4'b0001: // Subtraction
 | 0010 | Y = A * B; Y=A-B;
| 0011 | Y = A / B; 4'b0010: // Multiplication
| 0100 | Y = A << 1; Y = A[7:0] * B[7:0];
| 0101 | Y = A >> 1; 4'b0011: // Division
| 0110 | Y = A rotated left by 1; Y = A/B;
| 0111 | Y = A rotated right by 1; 4'b0100: // Logical shift left
| 1000 | Y = A and B; Y = A<<1;
| 1001 | Y = A or B; 4'b0101: // Logical shift right
| 1010 | Y = A xor B; Y = A>>1;
| 1011 | Y = A nor B; 4'b0110: // Rotate left
| 1100 | Y = A nand B; Y = {A[6:0],A[7]};
| 1101 | Y = A xnor B; 4'b0111: // Rotate right
| 1110 | Y = 1 if A>B else 0; Y = {A[0],A[7:1]};
| 1111 | Y = 1 if A=B else 0; 4'b1000: // Logical and
module alu( Y = A & B;
input [15:0] A,B, // ALU 8-bit Inputs 4'b1001: // Logical or
input [3:0] ALU_Sel,// ALU Selection Y = A | B;
output [15:0] Y, // ALU 8-bit Output 4'b1010: // Logical xor
output CarryOut // Carry Out Flag ); Y = A ^ B;
reg [7:0] Y; 4'b1011: // Logical nor
Y = ~(A | B);
4'b1100: // Logical nand
Y = ~(A & B);
always @(*) // Combinational circuits 4'b1101: // Logical xnor
begin Y = ~(A^B);
4’b1110: Y = (A>B)?1’b1:1’b0;
4’b1111: Y= (A==B)?1’b1:1’b0;
default: Y = 16’bx;
endcase
end
endmodule
(Or)

Write a verilog code for a BCD to 7 segment decoder using case statement in behavioral description. The seven segments of the
QC101 (b)* decoder display are a, b, c, d, e, f and g. A segment glows when the corresponding bit if segment is zero.
 UNIT – II

Q. No Questions

QC201 (a)* (i)Write the Verilog description of positive edge sensitive SR Flip Flop using UDP. (7 Marks)
// A positive edge sensitive SR flip-flop
Primitive SRFF (q, s, r, clk, clr);
input s, r, clk, clr;
output reg q;
table
// s r clk clr q q_new
? ? ? 1 : ? : 0; // clear
 ? ? ? (10) : ? : -; // ignore .. no change
0 0 (01) 0 : ? : -; // no change
0 1 (01) 0 : ? : 0; // reset condition
1 0 (01) 0 : ? : 1; // set condition
1 1 (01) 0 : ? : x; // invalid condition
? ? (10) 0 : ? : -; // ignore .. no change
endtable
endprimitive
(ii) Write a Verilog program for a full adder circuit using a task. Define the task 'FA' that takes three inputs (A, B, and Cin)
and produce two outputs (Sum and Cout). Ensure that your program invokes the task for the generation of Sum and Cout
after a delay of 2 time units. (8Marks)

module fullader (s.cout,a,b,cin);

input a,b,cin;
output reg s,cout;
always @(a or b or cin)
FA (s,cout,a,b,cin);
task FA;
output sum,carry;
input A,B,C;
begin
#2 sum=A ^B ^C;
carry = A&B | B&C | C&A;
end
endtask
endmodule

(Or)

QC201 (b)*
(ii) Write the switch level modeling for D flip flop.(7Marks)
(i)Write the switch level Verilog code for 2:1 Multiplexer.(8Marks)

module my_mux (out, s, i0, i1);

output out;
input s, i0, i1;
//internal wire wire sbar;
not (sbar, s);
//cmos switches
cmos (out, i0, sbar, s);
cmos (out, i1, s, sbar);
endmodule
 UNIT – III

Q. No Questions

QC301 (a)*

Develop a VHDL code for 4 bit Asynchronous counter by instantiating JK flip-flips.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkc is
Port ( clock : in std_logic;
reset : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end jkc;

architecture rtl of jkc is

COMPONENT jkff
PORT(
clock : in std_logic;
reset : in std_logic;
j : in std_logic;
k : in std_logic;
q : out std_logic
);
END COMPONENT;

signal temp : std_logic_vector(3 downto 0) := "0000";

begin
d0 : jkff
port map (
reset => reset,
 clock => clock,
j => '1',
k => '1',
q => temp(3)
);

d1 : jkff
port map (
reset => reset,
clock => temp(3),
j => '1',
k => '1',
q => temp(2)
);

d2 : jkff
port map (
reset => reset,
clock => temp(2),
j => '1',
k => '1',
q => temp(1)
);

d3 : jkff
port map (
reset => reset,
clock => temp(1),
j => '1',
k => '1',
q => temp(0)
);

count(3) <= temp(0);

count(2) <= temp(1);
count(1) <= temp(2);
count(0) <= temp(3);
 end rtl;

(Or)

QC301 (b)* Design the following code converters using dataflow modeling in VHDL.
(i) Gray to Binary (8)
(ii) Binary to Gray (7)

(i)

(ii)
 UNIT IV

Q. No Questions

QC401 (a)* (i)Design a Parallel In serial Out Shift Register using VHDL. (7 Marks)

library ieee;

use ieee.std_logic_1164.all;

entity piso is

port(

clk,rst : in std_logic;

D: in std_logic_vector(3 downto 0);

Q: out std_logic;

);

end piso;

architecture arch of piso is

signal temp: std_logic_vector(3 downto 0)=”0000”;

begin

process (clk,rst)

begin

if (CLK'event and CLK='1') then

if(rst=’1’)then

temp<=D;

else

temp <= (temp(2 downto 0)&’0’);

end if;

end if;

end process;

q<= temp(3);

end arch;
(ii)Design a Serial In Parallel Out Shift Register using VHDL. (8 Marks)

library ieee;

use ieee.std_logic_1164.all;

entity sipo is

port(

clk, clear : in std_logic;

Input_Data: in std_logic;

Q: out std_logic_vector(3 downto 0) );

end sipo;

architecture arch of sipo is

begin

process (clk)

begin

if clear = '1' then

Q <= "0000";

elsif (CLK'event and CLK='1') then

Q(3 downto 1) <= Q(2 downto 0);

Q(0) <= Input_Data;

 end if;

end process;
end arch;

(Or)

QC401 (b)* Develop a VHDL code for 4-bit Ring Counter using D Flip-Flop.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Ring_counter is

Port ( CLOCK : in STD_LOGIC;

RESET : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR (3 downto 0));

end Ring_counter;

architecture Behavioral of Ring_counter is

signal q_tmp: std_logic_vector(3 downto 0):= "0000";

begin

process(CLOCK,RESET)

begin
 if RESET = '1' then

q_tmp <= "0001";

elsif (CLOCK=’1’ and CLOCK’EVENT) then

q_tmp(1) <= q_tmp(0);

q_tmp(2) <= q_tmp(1);

q_tmp(3) <= q_tmp(2);

q_tmp(0) <= q_tmp(3);

end if;

end process;

Q <= q_tmp;

end Behavioral;

UNIT V

Q. No Questions

QC501 (a)* Write a Verilog description of a Mealy sequence detector circuit that accepts a serial bit stream “x” as input and produces
a serial bit stream “z” as output. Whenever the bit pattern “1101” appears in the input stream, it outputs z = 1; at all
other times, z = 0.
//1101 Mealy Sequence Detector
module mealy_1101(
input x,clk,reset,
output reg z
);

parameter S0 = 2'b00 , S1 = 2'b01 , S2 = 2'b10 , S3 = 2'b11;

reg [1:0] PS,NS;

always@(posedge clk or posedge reset)

begin
if(reset)
PS <= S0;
else
PS <= NS;
end

always@(PS or x)
begin

case(PS)
S0 : begin
z=0;
NS = x ? S1 : S0 ;
$display(PS);
end
S1 : begin
z=0;
NS = x ? S2 : S0 ;
$display(PS);
end
S2 : begin
z=0;
NS = x ? S2 : S3 ;
$display(PS);
end
S3 : begin
z=x?1:0;
 NS = x ? S1 : S0 ;
$display(PS);
end

endcase
end
endmodule

(Or)
QC501 (b)* Design a state machine in Verilog to manage the different traffic light states (e.g., green, yellow, red) and transitions
between these states.

There are three lamps, RED, GREEN and YELLOW, that should glow cyclically with a fixed Fme interval (say, 1 second)
– The FSM will have three states, corresponding to the glowing state of the lamps.
– The input set is null; state transition will occur whenever clock signal comes.
– This is a Moore Machine, since the lamp that will glow only depends on the state and not on the inputs (here null).

module cyclic_lamp (clock, light,rst);

input clk,rst;
output reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100, GREEN=3’b010, YELLOW=3’b001;
reg [0:1] state;
always @(posedge clock)
begin
if(rst)
state <= s0;
else
begin
case (state)
S0: begin // S0 means RED
light <= GREEN; state <= S1;
end
S1: begin // S1 means GREEN
light <= YELLOW; state <= S2;
end
S2: begin // S2 means YELLOW
light <= RED; state <= S0;
end
default: begin
light <= RED;
state <= S0;
end
endcase
end
end
endmodule