5 TA Modelling
5 TA Modelling
José Proença
System Verification (CC4084) 2024/2025
CISTER – U.Porto, Porto, Portugal https://fm-dcc.github.io/sv2425
Motivation
Motivation
Specifying an airbag saying that in a car crash the airbag eventually inflates maybe not enough,
but:
Correctness in time-critical systems not only depends on the logical result of the com-
putation, but also on the time at which the results are produced
Lip-synchronization protocol
Synchronizes the separate video and audio sources bounding on the amount of time
mediating the presentation of a video frame and the corresponding audio frame. Humans
tolerate less than 160 ms.
1. Motivation
2. Timed Automata
3. Semantics
4. Modelling in Uppaal
• timed transition systems, timed Petri nets, timed IO automata, timed process algebras
and other formalisms associate lower and upper bounds to transitions, but no time
constraints to transverse the automaton.
• Expressive power is often somehow limited and infinite-state LTS (introduced to express
dense time models) are difficult to handle in practice
Example
Typical process algebra tools are unable to express a system which has one action a which
can only occur at time point 5 with the effect of moving the system to its initial state.
This example has, however, a simple description in terms of time measured by a stopwatch:
Associated tools
www.uppaal.org
Finite-state machine equipped with a finite set of real-valued clock variables (clocks)
Clocks
• dense-time model
• clocks can only be inspected or
• reset to zero, after which they start increasing their value implicitly as time progresses
• the value of a clock corresponds to time elapsed since its last reset
• all clocks proceed synchronously (at the same rate)
where C(C ) denotes the set of clock constraints over a set C of clock variables
System Verification 2024/25 @ FCUP Timed Automata 11 / 48
Example: the lamp interrupt
C(C ) denotes the set of clock constraints over a set C of clock variables. Each constraint is
formed according to
g ::= x □ n | x − y □ n | g ∧ g | true
where x , y ∈ C , n ∈ N and □ ∈ {<, ≤, >, ≥, =}
used in
Note
Invariants are the only way to force transitions to occur
Let H ⊆ (Act1 ∩ Act2 ) − {τ }. The parallel composition of ta1 and ta2 synchronizing on H is
the timed automata
where
Uppaal:
• takes H = Act1 ∩ Act2 (actually as
complementary actions denoted by the ?
and ! annotations)
User
UserUser • only deals with closed systems
Worker
Worker Worker
Ex. 5.3: Define the TA of the composition.
Hammer
HammerHammer
Syntax Semantics
(How to write) (How to execute)
Process Languages LTS (Labelled Transition Systems)
Timed Automaton TLTS (Timed LTS)
Syntax Semantics
(How to write) (How to execute)
Process Languages LTS (Labelled Transition Systems)
Timed Automaton TLTS (Timed LTS)
Timed LTS
Introduce delay transitions to capture the passage of time within a LTS:
a
s−
! s ′ for a ∈ Act, are ordinary transitions due to action occurrence
d
s−
! s ′ for d ∈ R0+ , are delay transitions
Timed LTS
• time additivity
d d′ d−d ′
(s −
! s ′ ∧ 0 ≤ d ′ ≤ d) ⇒ s −! s ′′ −−−! s ′ for some state s ′′
Semantics of TA:
Every TA ta defines a TLTS
T (ta)
whose states are pairs
⟨location, clock valuation⟩
with infinitely, even uncountably many states, and infinite branching
Definition
A clock valuation η for a set of clocks C is a function
η : C −! R+
0
η |= x □ n ⇔ η x □ n
η |= x − y □ n ⇔ (η x − η y ) □ n
η |= g1 ∧ g2 ⇔ η |= g1 ∧ η |= g2
Delay
For each d ∈ R+
0 , valuation η + d is given by
(η + d) x = η x + d
Reset
For each R ⊆ C , valuation η[R] is given by
(
η[R] x = η x ⇐ x ̸∈ R
η[R] x = 0 ⇐x ∈R
T (ta) = ⟨S, S0 ⊆ S, N, T ⟩
where
• S = {⟨l, η⟩ ∈ L × (R+ C
0 ) | η |= Inv (l)}
• T ⊆ S × N × S is given by:
a
⟨l, η⟩ −
! ⟨l ′ , η ′ ⟩ ⇐ ∃ η |= g ∧ η ′ = η[U] ∧ η ′ |= Inv (l ′ )
l −−−!l ′ ∈Tr
g,a,U
d
⟨l, η⟩ −
! ⟨l, η + d⟩ ⇐ ∃d∈R+0 η + d |= Inv (l)
S=
S = {⟨off , t⟩ | t ∈ R+
0 } ∪ {⟨on, t⟩ | 0 ≤ t ≤ 2}
T = ...
undesirable paths:
• time-convergent paths
• timelock paths
• zeno paths
d d d d
⟨l, η⟩ −!
1
⟨l, η + d1 ⟩ −!
2
⟨l, η + d1 + d2 ⟩ −!
3
⟨l, η + d1 + d2 + d3 ⟩ −!
4
···
such that X
∀i∈N . di > 0 ∧ di = d
i∈N
• Time-convergent path are counterintuitive; as their existence cannot be avoided, they are
simply ignored in the semantics of Timed Automata
• Time-divergent paths are the ones in which time always progresses
Definition
δ δ
An infinite path fragment ρ = s0 −!
0
s1 −!
1
. . . is time-divergent if ExecTime(ρ) = ∞
Otherwise is time-convergent.
where
X
ExecTime(ρ) = ExecTime(δi )
i=0..∞
(
0 ⇐ δ ∈ Act
ExecTime(δ) =
δ ⇐ δ ∈ R+
0
Definition
A path is timelock if it contains a state with a timelock, ie, a state from which there is not
any time-divergent path
A timelock represents a situation that causes time progress to halt (e.g. when it is impossible
to leave a location before its invariant becomes invalid)
State ⟨on, 2⟩ . . .
and is terminal
Timelock
Timelock
Timelock
- NotTerminal
- NotTerminal
- NotTerminal
State ⟨on, 2⟩ . . .
Timelock
Timelock
Timelock
- NotTerminal
- NotTerminal
- NotTerminal
In a Timed Automaton
• The elapse of time only takes place at locations
• Actions occur instantaneously: at a single time instant several actions may take place
In a Timed Automaton
• The elapse of time only takes place at locations
• Actions occur instantaneously: at a single time instant several actions may take place
Definition
An infinite path fragment ρ is zeno if it is time-convergent and infinitely many actions occur
along it
A timed automaton ta is non-zeno if there is not an initial zeno path in T (ta)
Example
Suppose the user can press the in button when the light is on in
In doing so clock x is reset to 0 and light stays on for more 2 time units (unless the button is
pushed again ...)
Example
Typical paths: The user presses in infinitely fast:
in in in in in
⟨off , 0⟩ −
! ⟨on, 0⟩ −
! ⟨on, 0⟩ −
! ⟨on, 0⟩ −
! ⟨on, 0⟩ −
! ···
y<=3600
1. x ∈ Ui (for 0 ≤ i ≤ n)
2. for all clock valuations η, there is a c ∈ N>0 such that
Both
• timelocks
• zenoness
Simulator.
• Viewers: automata animator and message sequence chart
• Control (eg, trace management)
• Variable view: shows values of the integer variables and the clock constraints defining
symbolic states
Verifier.
• (see next session)
System Verification 2024/25 @ FCUP Modelling in Uppaal 41 / 48
Extensions (modelling view)