1.

A Synchronus event occurs at a pre-determined or anticipated time during execution of the

program while an asynchronus event can occur at any given time and is not scheduled. Hardware
interrupts are called asynchronus because they are can occur at any time. On the other hand,
software interrupts occur during normal execution of the program when a special instruction is
executed.
2. I/O devices are much slower than the processor. Waiting idly for the device to get ready again
(polling) wastes time that could be otherwise utilized. Especially if more than one I/O devices
are connected then polling them one by one in an endless loop will require considerable time
due to which the system can break the execution of certain real-time tasks. On the other hand,
hardware interrupts are asynchronous events that are independent of currently executed
program. This allows for parallelism or multi-tasking.
3.
4. When an interrupt occurs, the CPU suspends the execution of the current program to service the
IRQ. To restore normal program operation after execution of ISR it is important to save the
context of the program. This is also required if a higher priority interrupt occurs during the
execution of an ISR. By pushing the current context onto the interrupt stack, important
information such as value of PCR, status registers and other commonly used registers is
preserved. This ensures restoration of exact state of the program after the interrupt handling is
completed.
5. An interrupt source can only be disabled if it is a maskable one. A PIC has an interrupt mask
register (IMR) that allows individual interrupts to be enabled or disabled. Writing a 1(or 0) to the
bit in IMR corresponding to the particular IRQ line disables interrupts on that line.
6. Interrupt nesting allows interrupts with an equal or higher priority to interrupt an existing
interrupt. interrupt nesting is prohibited at the two ends of an ISR, referred to as the context
switching sections.
7. To send an interrupt signal to the PIC, a level-sensitive device needs to drive its IRQ line to the
active level, and then hold it at that level until it has been cleared (say, upon service completion).
An edge-triggered device needs to drive a level transition on the interrupt line, either a falling
edge (high to low) or a rising edge (low to high). In other words, a PIC detects IRQs from edge-
triggered devices by clear-assert transitions.
8. In the interrupt acknowledge cycle, the processor asserts the INTA (interrupt acknowledge) line
to the PIC, expecting an interrupt vector number. The PIC drives the interrupt vector number
associated with device A to the system bus.
9. Software interrupts are synchronous events generated by special processor instructions placed
in a program. Software interrupts are an essential component of an operating system and serve
several important purposes. An operating system can make use of the services provided by
operating system kernel to communicate with the installed hardware. It provides user-OS
interaction by transitioning from user mode (where application code runs) to kernel mode
(privileged mode where operating system operates).
10. In real-time applications, timely servicing of the interrupts is crucial. If an ISR of an interrupt is
very lengthy it may suspend the execution of other interrupts and critical tasks. the servicing
deadline will be exceeded. To prevent this from happening the lengthy processing code from the
ISR can be moved to a separate server task that only performs the critical servicing such as
 copying the incoming data from a communications channel. Processing of the data can be
deferred to a later time.
11. Interrupt chaining allows multiple ISRs to share a single interrupt vector. It links multiple ISRs in a
sequential manner, where each ISR is responsible for handling a portion of the interrupt
processing. When an interrupt occurs, the first ISR in the chain is invoked. It may perform some
processing related to the interrupt and then call the next ISR in the chain to handle additional
tasks. This continues until the last ISR in the chain completes the interrupt processing. Chaining
allows multiple pieces of code, such as BIOS routines, operating system services, and user
programs, to collaborate in handling the same interrupt while preserving the functionality of the
original interrupt vector.
12. Interrupt cascading refers to a technique used in computer systems where multiple interrupt
sources share a single interrupt vector. This approach allows for the organization of related
services or functionalities under a common entry point, typically referred to as a level 1 ISR
(Interrupt Service Routine). The level 1 ISR, associated with the interrupt vector, serves as the
primary handler for various interrupt sources. The branching typically happens at the beginning
of an ISR (switching points): an appropriate next-level ISR is invoked according to the specified
function number (software interrupts) or by checking the status registers of hardware devices
(hardware interrupts). It is also worth noting that for each IRQ there is only one ISR to be
executed to completion, and after that the control is immediately returned to the interrupted
program.
13. The shared data issue in a system with concurrent processes, including user tasks and interrupt
service routines (ISRs), can be resolved through two methods: interrupt disabling and double
buffering.
Interrupt Disabling: One solution involves the user program marking a critical section, which
needs to access shared data, as protected by disabling interrupts before entering and enabling
them afterward. While interrupts are disabled, the current task has exclusive access to the
processor, ensuring data consistency. However, this approach may affect the timely update of
shared data and cause missed deadlines for other ISRs.
Double Buffering: Another solution utilizes double buffers, where two sets of variables are used
for shared data. The ISR modifies one set of variables that is not currently being used by the user
task. This approach avoids interrupt-related delays and missed deadlines. However, it requires
additional memory for the duplicated data and may result in slight time drift in displayed
information due to data copying.
Each approach has its advantages and drawbacks, and the choice depends on the specific
requirements and trade-offs in the system design.
14. There are two major causes for interrupt latency. First, when a device X raises an IRQ, the
processor might be executing an ISR at a higher priority level. Second, interrupts might have just
been temporarily disabled by a user task. In embedded systems and many real-time operating
systems, it is not uncommon for a user application to disable/enable interrupts in order to
obtain greater control of system resources. However, this ought to be done carefully. If a user
program occupied the processor for too long, the interrupts would not be handled in a timely
manner, and the whole system would suffer owing to a ripple effect.
 The scheduling delay also has two causes. First, the processor might have been executing an ISR:
the execution of a lowest-priority ISR blocks the highest-priority task from running. Second, a
higher-priority task may be running.
15. 256
16. the BIOS (and DOS) on a PC traditionally maps the master 8259A’s IRQ0 to interrupt vector
number 0x08 and the slave 8259A’s IRQ8 to interrupt vector number 0x70. Some OS that do not
honor processor’s default vectors can remap the master and slave.
17.
18. ARM processors use memory-mapped I/O. This means that I/O devices are mapped into the
same address space as memory, and are accessed using the same instructions. This simplifies
programming, as the same instructions can be used to access both memory and I/O devices. It
also makes more efficient use of memory space, as the same memory address space can be used
for both memory and I/O devices.
19. Owing to the ARM pipelining mechanism, while the processor is executing an instruction j, it is
also fetching the instruction j + 2—the second instruction after j. Since each ARM instruction has
4 bytes, while the processor is executing the instruction LDR PC, [PC, #-0xF20] at address
0x00000018, the program counter value is actually 0x00000018 + 2 × 4 = 0x00000020. Then, by
executing the instruction LDR PC, [PC, #-0xF20], the new program counter value becomes PC -
0xF20 = 0x20 − 0x F20 = 0xFFFFF100 (wrapped around at 0x0), which is the address of the
interrupt vector register.
20. Interrupt cascading allows multiple interrupt sources to share one interrupt vector. This pattern
is typically used by an operating system to group multiple relevant services together under one
entry point. all software interrupts on ARM processors share a single vector, 0x0008. for a
software interrupt, the ISR can trigger other ISRs by switching on the value of the function
number specified in the swi instruction.