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 21 Technical Series
Computer Org. & Arch.
control unit, which
and performing calculations. It consists of the
coordinates the activities of the other components, and the
mathemnatical
arithmetic logic unit (ALU), which performs
operations.
instructions. It is
4. Memory: This component stores data and
divided into two main types:
Primary Memory (RAM): Volatile memorythat storesdata
temporarily while the computer is in use.
Secondary Memòry: Non-volatile memory that stores data
permanently, such as hard drives, solid-state drives, and
optical drives.
connects all the
5. Motherboard: This is the physical board that for data
components of the computer. It provides the pathways
and control signals to flow between the components.
Buses: These are electrical pathways that
connect the various
6. communicate with
componentsof the computer,allowing them to
each other.
Ans.(b) Microprogram Sequence Design and Logic
Microprogramming is a technique used to imnplement the control
microinstructions
of
unit of a CPU.It involves storing a sequence
microprogram control store. These
in a speciaimemory called a CPU
microinstructions define the sequence of operations that the
should perform to execute a machine instruction.
Design and Logic:
1. Microinstruction Format:Each microinstruction contains a
performed. These
set of fields that specify the operations to be
fields typically include:
Opcode: Specifies the type of operation (e.g., fetch, decode,
execute).
Address fields; Specify the addresses of memory locations or
registers to be accessed.
Control signals:Control the operation of the ALU, registers,
and other components.
microinstructions
2. Microprogram Sequencing: The sequence of
is determined by a microprogram sequencer. This component
selects the next microinstruction to be executed based on the
current microinstruction and the status of the CPU.
3. Microcode ROM: The microprogram is typically stored in a read
ensures that
This
Only memory (ROM) called a microcode ROM.
 Computer Org. & Arch. 22
Technical Series
the microprogram cannot be modified during operation.
Advantages of Microprogramming:
Flexibility: Microprogramming allows for easy modification of
the instruction set of a CPU.
Emulation: It can be used to emulate different CPUarchitectures
on asingle hardware platform.
Debugging: Microprogramming can aid in debugging hardware
and software problems.
Disadvantages of Microprogramming:
Performance overhead: Microprogramming can introduce
additional overhead, as the CPUmust fetch and execute
microinstructions.
Con1plexity: Designing and implementing microprograms can
be complex.
Q.3. Consider a hypothetical 32-bit micro- processor having
32-bit instructions composed of two fields the first byte
contains the opcode and the remainder the immediate
operand or an operand address.
(a) What is the maximum
directly addressable bytes)?
memory capacity (in bytes)
(b) Discuss the impact on the
system speed if the
microprocessor bus has
(i) a 32-bit local address bus
Or
and a 16-bit local data bus,
(ii) a 16-bit local address bus
and a l6-bit local data bus.
(c) How many bits are
needed for the program counter and
the instruction register?
Ans.(a) Maximum Directly
Opcode Field: 1 byte (8Addressable
bits)
Memory Capacity
Operand/Address
Since the
Field: 32 -8= 24 bits
operand/address field is 24 bits, it can directly address
224 bytes of memory.
Therefore, the maximum directly
(b)
is 2% bytes, which is 16 MB. addressable memory capaci)
Impact on System Speed
()32-bit Local
Address Bus and 16-bit Local DataBus
Advantages:
Can access 2* bytes (4
GB) of memory directly.
 Computer Org. &Arch
23 Technical Series
Can transfer 16 bits of data at atime, which is generally faster
than a 8-bit bus.
Disadvantages:
Mav require additional memory accesses to transfer 32-bit data.
(i) 16-bit Local Address Bus and 16-bit Local Data Bus
Advantages:
Simpler and potentially cheaper design.
Disadvantages:
Canonly access 2° bytes(64 KB) of memory directly.
Requires more memory accesses to transfer 32-bit data,
significantly impacting performance.
Overall. a 32-bit local address bus and 16-bit local data bus provides
abetter balance between addressability and data transfer speed.
(c) Number of Bits for Program Counter and Instruction
Register
Program Counter (PC): The PC needs to address any byte
within the directly addressable memory space. Therefore, it
requires 24 bits.
Instruction Register (IR): The IR holds a complete 32-bit
instruction. Therefore,it requires 32 bits.
16-bit
Q.4.(a) A set-associative cache has a block size of four
accommodate a
Words and a set size of 2. The cache can
is
total of 4096 wòrds. The main memory size that
cacheable is 64K 32 bits. Design the cache structure and
Show how the processor's addresses are interpreted.
(D) Explain two techniques for enhancing the performance of
Computers with multiple execution pipelines.
Ans.(a) Set-Associative Cache Design
Cache Parameters:
Block size: 4 × 16 bits = 64 bits
Set size: 2
Total cache size: 4096 words
Computer Org. & Arch. 24 Technical Series
4096 × 32 bits
= 131,072 bits
Cache Structure:
contains
The cache can be divided into 4096/64 =64 sets. Each set
2 blocks.

Set0 Setl Set3

Block 0 Block 0 Block 0

Block I Block I Block 1

Address Interpretation:
Tag: Themost significant bits ofthe address are used to identify
the set in the cache.
Index: The next bits of the address are used to select the block
within the set.
Offset: The least significant bits of the address areused to select
a word within the block.
For a64K 32-bit memory, the address is 16 bits. Let's assume:
Tag: 6 bits
Index:6 bits
Offset: 4 bits
This allows for 64 sets (2), 2 blocks per set, and 16 words per
block.

Example: If the memory address is 0x1234, the tag would be

Ox12, the index would be Ox3, and the offset would be Ox4. The
cache would search for set Ox3 and check if block 0 or
block 1
contains the desired data.
Ans.(b) Techniques for Enhancing Performance of
Multiple Execution
Pipelines
Branch Prediction:
This technique attempts to predict
will be taken o not. whethera branch instructioß
If the prediction is correct, the pipeline can continue fetchi
instructions from the predicted path, reducing stalls.
 Computer Org. &Arch. "25
Technical Series
Techniques include static branch prediction (based on past patterns)
and dynamic branch prediction (using a branch predictor table).
Out-of-Order Execution:
This technique allows instructions to execute in a different order
than the progranm sequence if they are independent and their
operands are available.
. It helps to hide the latency of memory accesses and other slow
instructions.
. A.reorder buffer is used to track the order of instructions and
ensure correct execution.
0.5 (a) Calculate (72530-13250) using ten's complement
arithmetic. Assume rules similar to those for two's
complement arithmetic.
(b) List and briefly explain five important instruction set
design issues.
Ans.(a) Ten's Comnplement Arithmetic
Step 1: Find the ten's complenent of 13250.
Tofind the ten's complement,subtract each digit from 9 and add
ltothe result.
13250 becomes 86749 +1=86750.
Step 2: Add the minuend (72530) and the ten's complement
of the subtrahend (86750).
72530
+ 86750

159280
Step 3: Discard the carry if it exists.
Since there's a carry,discard it.
Therefore, 72530- 13250=59280.

Ans.Orthogonality:
(b)
Important Instruction Set Design Issues
This refers to the ability of instructions to be
A well-designed
combined in various ways without restrictions. operations and
instruction set should allow for a wide range of
addressing modes.
 Computer Org. & Arch. 26
Technical Series
Completeness: An instruction set should provide a complete set
of instructions to perform all necessary tasks. This includes
arithmetic, logical, data transfer, and control flow instructions
Eficiency: Instructions should be designed to be efficient in terms
of execution time and memory usage. This involves considering
factors like the number of clock cycles required to execute an
instruction and the amount of memory needed to store the
instruction.
Regularity: A regular instruction set is easier to learn and use.
It often involves a uniform format for instructions and a
consistent.
set of addressing modes.
Modularity: A modular instruction set can be extended or
customized to meet specific needs. This can be achieved through
the use of optional instructions or coprocessors.
Q.6. The x86 architecture includes an instruc- tion called decimal
adjust after addition (DAA). DAA performs the following sequence
of instructions:
if((AL AND OFH) >9) OR (AF = 1)then
AL-AL + 6;
AF ¬-1;
else
AF -0;
endif
if (AL > 9FH) OR (CF = 1)then
ALAL + 60H;
CF -1;
else
CF -0;
endif.

"H"indicates hexadecimal. AL is an 8-bit register that

holds the
result of addition of twounsigned 8-bit
there is a carry from bit 3 to bit.4 in theintegers.ofAF is a flag set1
1S a flag set if there is a carrv
result an addition. CF
from bit 7to bit 8. Explain the
function performed by the DAA
instruction.
 27 Technical Series
Computer Org. & Arch.
Ans.The DAA Instruction:A Decimal Adjuster
instruction
Purpose: The DAA (DecimalAdjust After Addition)
performing decimal
in x86 architecture is primarily used for
Decimal)
arithmetic operations on packed BCD (Binary-Coded
using
numbers. BCD is a way of representing decimal numbers
decimal
binary digits, whereeach four-bit group representsa single
digit.
Functionality:
1. Checks for carry from lower digit:
are greater
" if the least significant four bits of AL (ALAND OFH)
than 9or if the auxiliary carry flag (AF) is set, it indicates a carry
from the lower decimal digit.
" In this case, 6is added to AL to
adjust the value to the correct
decimal digit, and AF is set to 1.
2. Checks for carryfromn upper digit:
are greater
" If the most significant four bits of AL(AL > 9FH)
from the
than 9or if the carry flag (CF)is set, it indicates a carry
upper decimal digit.
value to the correct
In this case, 60H isadded to AL to adjust the
decimal digit, and CF is set to 1.
of an addition
Overall, the DAA instruction ensures that the result
BCDnumber.
operation on packedBCD numbers is a valid
Example:
and 45. In BCD.
Suppose we want to add the decimal numbers 23
respectively. Adding
these are represented as 0x23and 0x45,
is not a valid BCD
them in binary gives 0 x68. However, this
number 104.
number because 0 X68 represents the decimal
adjust the
Using the DAA instruction after the addition would
decimal number
result to Ox73, which correctly represents the
68.
rate of 2.5 GHz
27. A non-pipelined processor has a clock
instruction) of 4. An
and an average CPI (cycles per
five-stage pipeline.
upgrade to the processor introduces a
However, due to internal pipeline delays, such as iatcn
Computer Org.& Arch.
28 Technical Series
new processor has to be
delay, the clock rate of the
reduced to2 GHz.
a typical program9
(a)What is the speedup achieved for
each processor?
(b)What is the MIPSrate for
Ans.Analyzing the Pipelined Processor
Given:
CPI= 4
Non-pipelined processor: Clock rate= 2.5GHz,
Pipelinedprocessor: Clock rate =2 GHz, 5-stage pipeline
Assumptions:
The pipeline is fully utilized without stalls.
The pipeline is ideal, meaning there are no structural hazards or
data hazards.
(a) Speedup Achieved
Non-pipelined execution time:
" Execution time= Clock cycles /Cock rate
Execution time = (CPIx Number of instructions) / Clock rate
Pipelined execution time:
Assuming ideal pipelining, the execution time for a sequence of
instructions is equal to the pipeline depth (number of stages) plus
the initial pipeline fill time.
Execution time=5+ (Number of instructions - 1)
Speedup:
Non - pipelinedexecution tine
Speedup =
Pipeline execution time
Speedup=(CPIxNumber of instructions) / Clock rate) /(5 +
(Number of instructions 1)
Simplifying:
Speedup (CPI x Clock rate) / (Clock rate + 4)
Substituting values:
Speedup s (4 x 2.5 GHz) /(2.5 GHz+ 4)
3.2
Therefore, the speedup achieved is
(b) MIPSRate for Each
Processor approximately
3.2.
MIPS (Million Instructions Per
MIPS = (Number of Second) is calculated as:
instructions) / (Execution time in seconds)
 Arch. 29 Technical Series
Computer Org. &
Non-pipelined processor:
instruc
MIPS= (Number of instructions) / ((CPI x Number of
tions) / (2.5 x 10))
MIPS=2.5 x 10°/CPI
=2.5 x 10°/ 4
625 MIPS
Pipelined processor:
MIPS =(Number of instructions) / ((5 + (Number of instructions
- 1)) /(2x10))
As the number of instructions increases, the term (5 + (Number
of
of instructions 1)) becomes approximately equal to Number
instructions.
MIPS 2x 109
Therefore, the MIPS rate for the non-pipelined processor is
approximately 625 MIPS, and the MIPS rate for the pipelined
processor is approximately 2000 MIPS.
used to minimize
Q.8. (a)Briefly explain the two approachesmachines.
register-memory operations on RISC
32 operations,
(b) A computer has 16 registers, an ALUwith common
and a shifter with 8 operations, all connected to a
bus sytem.
word for micro
i) Formulate a micro-operation. controi
operation
specify the
(ii) Show the bits of the control word & that
micro-operation R4 4-R5 + R6.
Ans.(a)Register Windows:
registers,
This technique involves using a circular buffer of
allowing for efficient function calls and returns without frequent
memory accesses.
By separate window of registers for each active
maintaining a
compiler can minimize the number of load and store
runction,the
instructions.
Compiler Optimizations:
techniques to reduce register-
Compilers can employ various
memory operations, such as:
 ComputerOrg. &Arch. 30
Technical Series
Register allocation: Assigning frequently used variables o
registersto avoid unnecessary nemory accesses.
" Loop invariant code motion: Moving code that is invarians
within a loop out of theloop to reduce the number of computations
" Common subexpression elimination: Identifying and
eliminating redundant computations.
Ans(b).(i) Micro-operation Control Word
Micro-operation: Abasic operation performed by a computerg
control unit in a single clock cycle. It involves transferring data
between registers, performing arithmetic or logical operations on
data,or controlling the flow of the program.
Control Word: A binary code that specifies the micro-operation
to be executed by the control unit. It typically
consists of several
fields,each controlling adifferent aspect of the
such as: micro-operation,
e
Register field:Specifies the registers involved in the operation.
Operation field: Specifies the type of operation to be performed
(e.g., arithmetic, logical, data transfer).
Shifter field: Specifies the type of shift operation to be
ALUfield: Specifies the specific AL¯ performed.
operation tobe performed.
Memory control field: Specifies whether to access
the type of memory access. memory and
(ii) Control Word for R4 4-
R5 + R6
Micro-operation: Transfer the sum of R5 and R6 into R4.
Control Word:
Register field: 0100 (R4), 0101 (R5), 0110 (R6)
"
Operation field: 0001(addition)
Shifter field: 000(no shift)
ALUfield: 00000
(addition
Memory control field: 00operation)
(no memory
Combining the fields, the access)
0100 010101100001 000 control word would be:
Q.9. Let a be
the
0000000
executed percentage byof na program code that can
simultaneusiv proeassor be
 Arch 31 Technical Series
Computer Org. &
etem,Assume that the remaining code must be executed
sequentially by a single processor. Each processor has
an execution rate ofx MIPS.
la) Derive an eXpression for the effective MIPSrate when
cing the system for exclusive execution of this program,
in terms of n, a and x.
(b)lfn16 and x=4 MIPS, determine the value of that will
yield a system performance of 40 MIPS.
Ans.(a) To derive an expression for the effective MIPSrate, we need
to consider two parts:
. Parallel Execution: a portion of the code can be executed
simultaneously by n processors. So, the parallel execution time is
(a/n) /x.
Sequential Execution: the remaining (1- a) portion must be
executed sequentially by a single processor. So, the sequential
execution time is (1-a) /x.
The totalexecution time is the sum of these two times:
Total execution time = (a/n) /x+ (1-a) /x
The effective MIPS rate is the reciprocal of the total
execution time:
Effective MIPSrate = 1/(an) fx + (1- a) /x)
Simplifying the expression:
Effective MIPS rate = nx/(a tn- an)
(b) Given n= 16. x =4 MIPS, and desired effective MIPS rate = 40
MIPS, we can plug these values into the expression and solve for
a:

40=16 x 4/(a+ 16 16a)

Simplifying: 10 =a+ 16 - 16a
15a =6
a = 2/5
Therefore, aa=40% will yield a system performance of 40 MIPS.