2 August 2023 1445 ‫ محرم‬16

ً ‫َو َما أُوتِيت ُ ْم مِ نَ ْالع ِْل ِم إِ اَّل قَل‬

‫ِيل‬
Dr. Hesham Omran
Ain Shams University – Master Micro LLC

Analog IC Design
Lab 04
Common Drain Frequency Response

Intended Learning Objectives

In this lab you will:
• Learn how to use the Sizing Assistant (SA) to size the transistors.
• Design and simulate a common-drain amplifier.
• Use PMOS input transistor to avoid body effect in a CD amplifier.
• Investigate the ringing and peaking problem in a capacitive-loaded CD amplifier with a large source
resistance (Rsig) and learn how to solve it.

NOTE: To get access to the Sizing Assistant please register at https://adt.master-micro.com/ and
create a support ticket from your dashboard. Verified instructors may also request access to an
editable MS Word version of the lab and the lab model answer.

NOTE: The values and charts used in the lab document assume the provided 180 nm educational
device model and 1.8 V supply. Other models/technologies can be used by applying reasonable
adjustments to the lab values.

Part 1: Device Sizing Using SA

1) From the square law, we have
2𝐼𝐷 2
𝑔𝑚 = → 𝑉𝑜𝑣 =
𝑉𝑜𝑣 𝑔𝑚 /𝐼𝐷
2
For a real MOSFET, if we compute 𝑉𝑜𝑣 and 𝑔 they will not be equal. Let’s define a new parameter
𝑚 /𝐼𝐷
called V-star (𝑉 ∗ ) which is calculated from actual simulation data using the formula
2 2𝐼𝐷
𝑉∗ = ↔ 𝑔𝑚 = ∗
𝑔𝑚 /𝐼𝐷 𝑉
∗
The lower the 𝑉 the higher the 𝑔𝑚 , but the larger the area and the lower the speed. An often used
sweet-spot that provides good compromise between different trade-offs is 𝑉 ∗ = 200𝑚𝑉.

2) Although the 𝑉 ∗ is a nice parameter that is inspired by the square-law, it does not have an intuitive
or a physical meaning (it is not an actual voltage in the circuit). We actually defined 𝑉 ∗ in order to be
able to define a relation between the 𝑔𝑚 and 𝐼𝐷 . Thus, the real parameter that we should care about
is the 𝑔𝑚 over 𝐼𝐷 ratio (𝑔𝑚 /𝐼𝐷 ).
 If the square-law is valid
2𝐼𝐷 𝑔𝑚 2
𝑔𝑚 = → =
𝑉𝑜𝑣 𝐼𝐷 𝑉𝑜𝑣
Using 𝑉 ∗
𝑔𝑚 2
= ∗
𝐼𝐷 𝑉
A small 𝑔𝑚 /𝐼𝐷 means large 𝑉𝑜𝑣 (biasing in strong inversion) and a large 𝑔𝑚 /𝐼𝐷 means small 𝑉𝑜𝑣
(biasing in weak inversion).
3) There are many good things about using the 𝑔𝑚 /𝐼𝐷 as a design knob:
a. The 𝑔𝑚 /𝐼𝐷 gives a direct relation between the most important MOSFET parameter (𝑔𝑚 ) and
the most valuable resource (𝐼𝐷 ). For example, a 𝑔𝑚 /𝐼𝐷 = 10 𝑆/𝐴 means you get 10 𝜇𝑆 of
𝑔𝑚 for every 1 𝜇𝐴 of bias current.
b. The 𝑔𝑚 /𝐼𝐷 is a normalized knob: it has a limited search range (typically from 5 to 25 S/A)
independent of the technology or the device type.
c. The 𝑔𝑚 /𝐼𝐷 is intuitive because it tells you directly about the inversion level (bias point) and
consequently all related trade-offs. For example, 𝑔𝑚 /𝐼𝐷 = 5 𝑆/𝐴 means strong inversion
(SI), 𝑔𝑚 /𝐼𝐷 = 15 𝑆/𝐴 means moderate inversion (MI), and 𝑔𝑚 /𝐼𝐷 = 25 𝑆/𝐴 means weak
inversion (WI).
d. The 𝑔𝑚 /𝐼𝐷 is an orthogonal knob: If we define the 𝑔𝑚 /𝐼𝐷 then we define the inversion level
(bias point). If you change 𝐼𝐷 or 𝐿 while keeping 𝑔𝑚 /𝐼𝐷 fixed, then the inversion level (bias
point) is kept fixed. The 𝑊 is treated as an output variable instead of being treated as an
input variable.
e. The higher the 𝑔𝑚 /𝐼𝐷 (the lower the 𝑉 ∗) the higher the efficiency and the headroom (the
available swing), but the larger the area and the lower the speed. An often used sweet-spot
that provides good compromise between different trade-offs is 𝑔𝑚 /𝐼𝐷 = 10 𝑆/𝐴 (𝑉 ∗ =
200𝑚𝑉).

4) We want to design a CD amplifier that has ideal current source load with the parameters below.

Parameter

Input transistor PMOS

𝑳 1𝜇𝑚

𝑽∗ 200𝑚𝑉

Quiescent (DC) input voltage 0𝑉

Supply 1.8𝑉

Current consumption 10𝜇𝐴

5) We assume we use a PMOS transistor that is placed in a dedicated n-well to be able to connect the
body and source terminals. This will avoid the degradation of the CD amplifier gain due to body
effect.
6) Since the square-law is not accurate, we cannot use it to calculate the sizing. Instead, we will use the
Sizing Assistant (SA) which is a powerful analog calculator that uses LUTs that are pre-generated
from the simulations. The input and output of SA are shown below. Note that since we assume body

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 and source are connected, we can set VDS = VGS. Draw the circuit schematic to be able to
understand this properly. Note that the load is connected to the source, not to the drain.

Part 2: CD Amplifier
1. OP (Operating Point) Analysis
1) Create a new schematic for the CD amplifier (the schematic is not included in the lab document and
is left for the student as an exercise). Use a PMOS transistor and use a 10𝜇𝐴 ideal current source
load for biasing (note that the current source will be connected to the source terminal). Connect the
source to the bulk. Use 𝐿 = 1𝜇𝑚 and 𝑊 as determined in Part 1. Use 𝐶𝐿 = 2𝑝𝐹, input source
resistance 𝑅𝑠𝑖𝑔 = 2𝑀Ω, and a DC input voltage = 0V.
2) Simulate the OP point. Report a snapshot clearly showing the following parameters.
➔ Cadence Hint: You can use Info Balloons (View -> Info Balloons) to show the device parameters.
Use (View -> Annotations -> Setup) to customize the Info Balloons.

ID
VGS
VDS
VTH
VDSAT
GM
GDS

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 GMB
CDB
CGD
CGS
CSB
Region
3) Check that the transistor operates in saturation.

2. AC Analysis
1) Perform AC analysis (1Hz:10GHz, logarithmic, 20points/decade) to investigate the frequency domain
peaking.
2) Report the Bode plot magnitude.
3) Do you notice frequency domain peaking? How much is the peaking?
➔ Cadence Hint: Use the following expression to calculate the peaking in dB:
ymax(dB20(VF("/vout")))
4) Analytically calculate the quality factor (use approximate expressions). Is the system underdamped
or overdamped?
5) [Optional] Perform parametric sweep: CL = 2p, 4p, 8p.
• Report Bode plot magnitude overlaid on same plot.
• Report the peaking vs CL.
• Comment on the results.
6) [Optional] Perform parametric sweep: Rsig = 20k, 200k, 2M.
• Report Bode plot magnitude overlaid on same plot.
• Report the peaking vs Rsig.
• Comment on the results.

3. Transient Analysis
1) Use a pulse source as your transient stimulus and set it as follows: delay time = 2us, initial (zero
value) = 0V, period = 8us, pulse (one value) = 100mV, fall time = 1ns, rise time = 1ns, pulse width =
4us.
➔ Cadence Hint: Use analogLib -> vsource and set the type as pulse.
2) Run transient analysis for 10us to investigate the time domain ringing.
➔ Cadence Hint: If the simulator time step is too large, set (max step = 10n) in the transient
analysis options.
3) Report Vin and Vout overlaid vs time.
4) Calculate the DC voltage difference (DC shift) between Vin and Vout.
• What is the relation between the DC shift and VGS of the transistor?
• How to shift the signal down instead of shifting it up?
5) Do you notice time domain ringing? How much is the overshoot?
➔ Cadence Hint: Use the overshoot function to calculate the maximum overshoot as a percentage.
Compare the function output to the plot to make sure you have set up the function properly.
6) [Optional] Perform parametric sweep: CL = 2p, 4p, 8p.
• Report Vout vs time overlaid on same plot.
• Report the overshoot vs CL.
• Comment.
7) [Optional] Perform parametric sweep: Rsig = 20k, 200k, 2M.
• Report Vout vs time overlaid on same plot.

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 • Report the overshoot vs Rsig.
• Comment on the results.

4. 𝑍𝑜𝑢𝑡 (Inductive Rise)

1) We want to simulate the CD amplifier output impedance. Replace CL with an AC current source with
magnitude = 1. Remove the AC input signal.
2) Perform AC analysis (1Hz:10GHz, logarithmic, 10points/decade). The voltage across the AC current
source is itself the output impedance.
3) Plot the output impedance (magnitude and phase) vs frequency. Do you notice an inductive rise?
Why?
4) Does 𝑍𝑜𝑢𝑡 fall at high frequency? Why?
Hint: 𝐶𝑔𝑑 appears in parallel with 𝑅𝑠𝑖𝑔 .
5) Analytically calculate the zeros, poles, and magnitude at low/high frequency for 𝑍𝑜𝑢𝑡 . Compare with
simulation results in a table.

5. [Optional] How to solve the peaking/ringing problem?

1) Place the input/output poles away from each other (as we did when we swept CL and Rsig).
2) A compensation network can be used to compensate for the negative input impedance and prevent
overshoots. Read [Johns and Martin, 2012] Section 4.4 and try to implement the compensation
network.

Lab Summary
In Part 1 you learned:
• How to find transistor sizing using the Sizing Assistant (SA).
• How to design a PMOS common-drain amplifier.

In Part 2 you learned:

• How to do AC, DC and transient simulations of a CD amplifier.
• How the peaking in the frequency response of a CD amplifier changes with the load capacitor and
source resistance.
• How the ringing in the transient response of a CD amplifier changes with the load capacitor and
source resistance.
• How the output impedance of a CD amplifier shows inductive behavior.

Acknowledgements
Thanks to all who contributed to these labs. Special thanks to Dr. Sameh A. Ibrahim for reviewing and editing
the labs. If you find any errors or have suggestions concerning these labs, contact
[email protected].

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