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VLSI Test Workshop 11feb Final

The VLSI Test Workshop, hosted by IIIT Guwahati from March 7-9, 2025, will cover key topics such as Design for Testing, Fault Modeling, and Memory Testing. Participants can benefit from hands-on lab sessions, networking opportunities, and career guidance, with registration fees varying based on participant category. For more information, attendees can contact the coordinators Dr. Rakesh Biswas or Dr. Sheikh Wasmir Hussain.

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36 views3 pages

VLSI Test Workshop 11feb Final

The VLSI Test Workshop, hosted by IIIT Guwahati from March 7-9, 2025, will cover key topics such as Design for Testing, Fault Modeling, and Memory Testing. Participants can benefit from hands-on lab sessions, networking opportunities, and career guidance, with registration fees varying based on participant category. For more information, attendees can contact the coordinators Dr. Rakesh Biswas or Dr. Sheikh Wasmir Hussain.

Uploaded by

joy678joy678
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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IIIT Guwahati & TTTC INDIA Presents

7th to 9th March 2025

VLSI TEST 09:00 AM to 06:00 PM

WORKSHOP
IIIT Guwahati

Key Features
Design for Testing
Fault Modeling
Test Generation
Test Standards
Test Diagnosis
Scan Compression and
Logic BIST
Memory Testing

Perks
Learn from Industry Leaders
Networking opportunities
Hands-on Lab Session on VLSI Testing
Career Guidance
Internship/Placement Opportunities

Coordinator : Dr. Rakesh Biswas


[email protected]
+91 9831820990

Please scan the QR code to Register


REGISTRATION
PATRON IIITG Students FREE
Prof. Sarat Kumar Patra Students other than IIITG Rs 850/- *
Director
IIIT GUWAHATI Faculties other than IIITG Rs 1500/- *

Industry Professionals Rs 2000/- *


ADVISORY COMMITTEE * Includes Registration Kit, Refreshment & Lunch
Dr. Mourina Ghosh Participation Certificate
Head of the Department Limited seats based on FCFS basis
ECE, IIIT GUWAHATI Accommodation in student hostels to limited
participants, subject to availability, on a paid basis.
Dr. Subhasish Dhal
Head of the Department
CSE, IIIT GUWAHATI RESOURCE PERSONS
COORDINATOR INDRANIL SENGUPTA
Dr. Rakesh Biswas Professor
Co-COORDINATOR Department of Computer Science,
Dr. Sheikh Wasmir IIT Kharagpur
Hussain
ABHISHEK CHAUDHARY
Principal Member of Technical
Staff,
AMD

JYOTIRMOY SAIKIA
Software Architect,
Cadence

RAJIT KARMAKAR
Member of Technical Staff,
Silicon Design Engineering,
AMD

For more details, please contact


Dr. Rakesh Biswas (+91 9831820990)
Dr. Sheikh Wasmir Hussain (+91 9402746256)
EVENT SCHEDULE
7th March, 2025, FRIDAY
Day 1
09:00AM - 09:30AM Inauguration and Introduction
09:30AM - 10:30AM Introduction to Design for Test-1
10:30AM - 11:00AM Networking over Tea/Coffee
11:00AM - 12:30PM Introduction to Design for Test-2
12:30PM - 01:30PM Networking over Lunch
01:30PM - 02:45PM Fault models
WORKSHOP
02:45PM - 03:00PM Networking over Tea/Coffee
03:00PM - 04:30PM Test generation and fault
VLSI TEST

simulation
04:30PM - 05:30PM DFT as a career

8th March, 2025, SATURDAY


Day 2
09:00AM - 10:30AM Scan Based Testing
10:30AM - 11.00AM Networking over Tea/Coffee
11.00AM - 12:30PM Scan Compression & Logic BIST
12:30PM - 01:30PM Networking over Lunch
01:30PM - 02:30PM Test Diagnosis
02:30PM - 02:45PM Networking over Tea/Coffee
02:45PM - 04:00PM Memory Testing
04.00PM - 05:45PM Test Standards

9th March, 2025, SUNDAY


Day 3
09:00AM - 10:30AM Lab session - 1
10:30AM - 10.45AM Networking over Tea/Coffee
10.30AM - 12:30PM Lab Session – 2
12:30PM - 01:30PM Networking over Lunch
01:30PM - 02:00PM Open house and conclusion
02:00PM - 03:30PM Lab session – 3
03:30PM - 03:45PM Networking over Tea/Coffee

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