Session 3

Design Constraints
Logic Synthesis
Prepared by:
DFT
ICpedia PnR Team
LEC
Contents
• Design Constraints

• Logic Synthesis

• DFT

• LEC
Timing Constraints
• “Simple Question”:
• How does the STA tool know what the required clock period is?
• Obvious Answer…
• We have to tell it! • We have to define constraints for the design.
• This is usually done using the Synopsys Design Constraints (SDC) syntax,
which is a superset of TCL.
• Three main categories of timing constraints:
• Clock definitions
• Modeling the world external to the chip
• Timing exceptions

3
Design Objects [for all Synopsys tools]
• Design: A circuit description that performs some logical function.
• The design may be stand-alone or may include other sub-designs.

• Cell: It is the instantiated name of the sub-design in the design.

• Reference: The original design to which the cell or instance refers.

• For example, a leaf cell in the netlist must be referenced from the link library, which
contains the functional description of the cell. Similarly an instantiated sub-design
must be referenced in the design, which contains functional description of the
instantiated sub-design.

• Port: These are the primary inputs, outputs or IO’s of the design.

• Pin: It corresponds to the inputs, outputs or IO’s of the cells in the design. (Note the
difference between port and pin).

• Net: These are the signal names, i.e., the wires that hook up the design together by
connecting ports to pins and/or pins to each other.

• Clock: The port or pin that is identified as a clock source. The identification may be
internal to the library or it may be done using dc_shell commands.

4
 Timing Constraints

• Three main categories of timing constraints:

1. Timing definitions
2. Optimization goals and timing exceptions.
3. Modeling the world external to the chip.

5
Timing Constraints: Categories

Timing Modeling outside Optimization goals and

world Timing exceptions

create_clock set_driving_cell set_false_path

create_generated_clock set_load set_multicycle_path
set_input_delay
set_output_delay set_max_area
set_max_delay set_max_transition
Set_min_delay set_max_capacitance
set_clock_uncertainty set_max_fanout

6
• Create_clock → The create_clock command creates a clock object in the current design. The command defines the
specified source_objects as clock sources in the current design. A pin or port can be a source for a single clock.

EX:

create_clock -name CLKP 10 [get_pins UPLL0/CLKOUT]

# Create a master clock with name CLKP of period 10ns

# with 50% duty cycle at the CLKOUT pin of the PLL.

• create_generated_clock → The create_generated_clock command creates a generated clock object in the current design.
This command defines a list of objects as generated clock sources in the current design. You can specify a pin or a port as a
generated clock object. The command also specifies the clock source from which it is generated. The advantage of using
this command is that whenever the master clock changes, the generated clock changes automatically.

EX:

The following example creates a frequency -divide_by 2 generated clock:

#create_generated_clock -divide_by 2 -source CLK [get_pins foo]

7
• set_input_delay: • set_output_delay

NAME: set_input_delay, NAME: set_output_delay

Sets input delay on pins or input ports relative to a clock Sets output delay on pins or output ports relative to a clock
signal. signal.

EX: EX:

The following example sets an input delay of 2.3 for ports The following example sets an output delay of 1.7 relative to
IN1 and IN2 on a combinational design. Because the design the rising edge of CLK1 for all output ports in the design.
is combinational, no clock is needed.
#set_output_delay 1.7 -clock [get_clocks CLK1] [all_outputs]
#set_input_delay 2.3 {IN1 IN2}

The following example uses a clock collection and sets an

input delay of 1.2 relative to the rising edge of CLK1 for all
input ports in the design:

#set_input_delay 1.2 -clock [get_clocks CLK1] [all_inputs]

8
Clock Specification for Synthesis
• Each clock in the design must be defined using the
create_clock command.
• It is recommended that the set_dont_touch_network
command be used for clocks to prevent synthesis from
buffering clock trees.
• Input delay constraint, and output delay constraint:
define the length of the path OUTSIDE the block.

Example.
set_input_delay –max 0.8 –clock clk\
[remove_from_collection[all_inputs] [get_portsclk]]
set_output_delay –max 2.5 –clock clk[all_outputs]
9
• set_min_delay • set_max_delay
This command sets the minimm delay target for paths in the This command Specifies the desired maximum delay for paths
current design. Minimum delay is considered as an in the current design.This command specifies that the
optimization constraint by the compile command. If a path maximum path length for any start point in from_list to any
violates the requirement given in a set_min_delay command, endpoint in to_list must be less than delay_value.
compile adds delay to fix the violation.
EX:
EX:
The following example shows how to optimize the design so
In the following example, the set_min_delay command that any delay path to a port named Y is less than 10 units.
requires that any delay path that passes through the UI cell
and ends at the Y port is greater than 12.5 time units:

#set_min_delay 12.5 -through U1 -to Y #set_max_delay 10.0 -to {Y}

10
Area Constraints
• Area constraints are given by limiting maximum area value
• As timing has greater priority in Design Compiler it is used to set maximum area
to zero, thus optimization achieves the best possible area with timings met.

11
Constraining Timing: Modeling Clock
• In Design Compiler clock is treated as ideal (global skew = 0)
• Clock tree is built at physical synthesis
• To get realistic design clock skew effect needs to be modeled in logic synthesis to
avoid optimistic design
D_In D Q
D_In D Q D Q FF1
FF1 FF2
CLK
CLK CLK Q
D
CLK
FF2
CLK
CLK

Logic Circuit Post-Layout Circuit

12
 Modeling Latency or Insertion Delay
• Network latency models the average ‘internal’ delay from the create_clock port or pin to the
register clock pins
• Source latency models the delay from the actual clock origin to the create_clock port or pin:
• Used for either ideal or propagated clocks (post layout)

create_clock -period 10 [get_ports CLK]

set_clock_latency -source –max 3 [get_clocks CLK]
set_clock_latency –max 1 [get_clocks CLK] ;# pre layout
#set_propagated_clock [get_clocks CLK] ;# post layout
YOUR_DESIGN

Source Latency Network Latency

CLK D Q

3ns 1ns CLK

Origin of Clock
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set_clock_uncertainty and Setup Timing

Example:
create_clock -period 2 [get_ports CLK]
set_clock_uncertainty –setup 0.14 [get_clocks CLK]

D Q X D Q
FF1 FF2 FF2 setup check at:
2 - 0.14 - 0.08 = 1.78

FF1 Data Launch Edge

(No uncertainty!) / /
.14 .08

0 1 1.78 1.92 2
Max allowable delay
for block “X” Assume lib
setup = 0.08ns
14
Combinational Designs
• Sometimes the design is a combinational circuit
• There is no clock to constraint timing

Circuit under design

Combinational
Logic

15
 Combinational Designs (2)
• Combinational circuit is put in the same clocked environment as the clocked one

• An abstract clock called “Virtual clock” is defined for this environment

• By setting correct clock period, input/output delays, the delay of the combinational logic
can be controlled

Combinational D Q
D Q Logic DFF
DFF
CLK
CLK

Clock
Delaymax= Tclk– Delayin – Delayout=7ns Delayout=3ns
Delayin=1ns

16
Boundary Conditions: Effect of Input Transition
Time
Design

IN … D Q …

CLK
…

• Rise and fall transition times on an input port affect the cell delay of the input
gate.
• It is therefore important to accurately model transition times on all inputs.

17
Modeling Input Transition

Design Design

IN … D Q … Driving IN … D Q …
Cell

Transition Time = 1.4ns

CLK CLK
… …

• For modeling input transition a specific transition time value or a

driving cell on the input pin can be used.

18
Boundary Conditions: Effect of Output Capacitive
Load

A B
… D Q …

CLK
…

Signal at A Signal at B

• Capacitive load on an output port affects the transition

time, and thus the cell delay of the output driver is
occurred.
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Boundary Conditions
• For modeling the world outside the block, we need to model:

1) The transitions on the input

2) A load capacitance on the output.

Example.

set_driving_cell –cell [get_lib_cells LIB/BUF2]

-pin X [remove_from_collection [all_inputs]

[all_clocks] ]

OR:

set_input_transition 0.02 [remove_from_collection [all_inputs]

[all_clocks] ]

set_load 0.12 [all_outputs] 20

Exercise 0.3ns 0.3ns
Setup Time
Requirement
TO_BE_SYNTHESIZED

D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
QB QB

Clk
Tclk= 2ns
◼ set_output_delay –max:
⚫ Describes the maximum time requirement of the external logic on the output
ports
Note: we should make sure that our design helps the assumed FF outside the
block to meet its setup requirements! By choosing the appropriate value for
max_output_delay

If FF has TSETUP = 0.3ns and TT = 0.3ns:

What is the max output_delay?
21
24
 Constraining Input Paths: Example 1
Spec:
Latest Data Arrival Time at Port A, after Jane’s launching clock edge = 0.6ns
mydesign.con
create_clock -period 2 [get_ports Clk] set_input_delay -max 0.6 -
clock Clk [get_ports A]

MY_DESIGN
JANE’s_DESIGN TSetup, FF2
0.2ns
Tmax
A
D Q M N D Q X D Q S
FF1 FF2 FF3
0.6ns
QB QB QB

Clk

What is the maximum delay Tmax for the input path N in

MY_DESIGN? __________________________
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Constraining Output Paths : Example 1
Spec:
Latest Data Arrival Time at Port B, before Joe’s capturing clock = 0.8ns mydesign.con
create_clock -period 2 [get_ports Clk] set_input_delay -max 0.6 -
clock Clk [get_ports A]
set_output_delay -max 0.8 -clock Clk [get_ports B]

JOE’s_DESIGN
MY_DESIGN TT + Tsetup
Tmax 0.7ns 0.1ns
B
N D Q X D Q S T D Q
FF2 FF3 FF4
QB QB QB
Clk

What is the maximum delay Tmax for the output path through

S in MY_DESIGN? __________________________
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 Multiple Inputs/Outputs - Same Constraints
MY_DESIGN
A Out1
D Q S
B M

C Out2
N D Q T
Clk

To constrain all inputs the same, except for the clock port:

set_input_delay –max 0.5 –clock Clk \

[remove_from_collection [all_inputs] [get_ports Clk]]

To constrain all outputs the same:

set_output_delay –max 1.1 –clock Clk [all_outputs]

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 Time Budgeting Example
timing_budget.tcl

# A generic Time Budgeting script file

# for MY_BLOCK, X_BLOCK and Y_BLOCK
create_clock -period 10 [get_ports CLK]

set_input_delay -max 6 -clock CLK [all_inputs]

remove_input_delay [get_ports CLK]
set_output_delay -max 6 -clock CLK [all_outputs]

X_BLOCK MY_BLOCK Y_BLOCK

X D Q S N D Q X D Q S N D Q X
FF1 FF2 FF3 FF4
10 4 4 10 4 4 10

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 False Paths

Timing paths that are logically impossible!

Even if they violate a timing requirement according to STA, the data would never
propagate through this path in actual circuit operation.. No need to meet any timing
constraint ☺

Therefore, we need to specify it to STA tools to avoid analyzing/reporting it.

Example.
set_false_path –through [get_pins Mux1/In0] –through [get_pins Mux2/In1] 26
False Paths
• It is possible that certain timing paths are not real (or not possible) in the actual
functional operation of the design. Such paths can be turned off during STA by setting
these as false paths.
• Even if they violate a timing requirement according to STA, the data would never
propagate through this path in actual circuit operation.. No need to meet any timing
constraint ☺

• A false path is ignored by the STA for analysis.

• A false path is set using the set_false_path specification.
• Examples could be
• from one clock domain to another clock domain

• When a false path is specified through a pin of a cell, all paths that go through that pin
are ignored for timing analysis.
27
False Paths
Advantage
➢ The false paths is that the analysis space is reduced, thereby allowing the analysis to focus
only on the real paths. This helps cut down the analysis time as well.
Disadvantage
➢ However, too many false paths which are wild carded using the through specification can slow
down the analysis.

28
False path examples
set_false_path -from [get_clocks SCAN_CLK]

-to [get_clocks CORE_CLK] set_false_path -to [get_ports TEST_REG*]

# Any path starting from the SCAN_CLK domain to the # All paths that end in port named TEST_REG* are false
paths.
# CORE_CLK domain is a false path.

set_false_path -through UINV/Z -through UAND0/Z

set_false_path -through [get_pins UMUX0/S]
# Any path that goes through bothof these pins
# Any path going through this pin is false.
# in this order is false.

set_false_path -through [get_pins SAD_CORE/RSTN]]

# The false path specifications can also be specified

to,

# through, or from a module pin instance.

29
Multi-cycle Paths

• There are data paths that require more than one clock period for
execution.

2 clock period delay

30
Multi_cycle Paths
• In some cases, the combinational data path between two flip-flops can take more
than one clock cycle to propagate through the logic.

• In such cases, the combinational path is declared as a multi cycle path.

• Even though the data is being captured by the capture flip-flop on every clock edge,
we direct

• STA that the relevant capture edge occurs after the specified number of clock
cycles.

• Since the data path can take up to three clock cycles, a setup multi cycle check of
three cycles should be specified.

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Multi_cycle Paths
• The multi cycle setup constraints specified to achieve this are given below.

create_clock -name CLKM -period 10 [get_portCLKM]

set_multicycle_path 3 -setup \

-from [get_pins UFF0/Q] \

-to [get_pins UFF1/D]

• The setup multi cycle constraint specifies that the path from UFF0/CK to UFF1/D
can take up to three clock cycles to complete for a setup check.

• This implies that the design utilizes the required data from UFF1/Q only every third
cycle instead of every cycle.

32
A three cycle multipath

33
 Exercise
-Do we need to specify false paths to synthesis and
physical synthesis as well?

-What are the consequences of not accurately

specifying false paths? [list two of them]

34
 Case analysis
A common case for designs is that some value should be assumed constant.
-For example; if the constant sets a multiplexer selector

-To propagate this constant through the design and disable irrelevant timing arcs, a
set_case_analysis constraint is used

-Example.
set_case_analysis 0 [get_ports testMode]

35
 Logical Design Rules
set_max_transiion 0.15
→ Sets the maximum transition time for all nodes of the design.

set_max_capacitance 0.08
→ Sets the maximum capacitance of a net for all nodes of the design.

set_max_fanout 10
→ Set the maximum number of load cells a pin can be connected to.

36
 Exercise
-What are the pros and cons of:
A. Setting a relatively high value for max. transition.
B. Setting a very tight value for max. transition.

-What are the pros and cons of setting a relatively low

value for max. fanout?

37
Exercise
4ns For all FFs:
Buf2 1ns 2ns 3ns 1ns 1ns 2ns
- Tcq=0.04ns
- Tsetup=0.05ns
10 fF
- Thold=0.03ns

4ns 1ns
2ns 2ns

PLL jitter= 0.1ns

/2 /2

Write and SDC file for each of BLOCK A and BLOCK B

- For each input port; specify a suitable I/P delay constraint and boundary conditions.
- For each output port; specify a suitable O/P delay constraint and boundary conditions.
- For each clock and generated clock, specify it properly for each block.
- Clarify that CK1 and CK2 don’t have inter-clk paths.
38
Contents
• Design Constraints

• Logic Synthesis

• DFT

• LEC
Logic Synthesis Definition
• “Synthesis is achieving an optimal gate level netlist from HDL code.”

• The logic synthesis process consists of two steps - translation and

optimization.
• Translation involves transforming a HDL (RTL) description to gates,
• optimization involves selecting the optimal combination of ASIC technology library cells
to achieve the required functionality.

• Synthesis is an iterative process aimed at achieving design goals

40
Logic synthesis and Formality: Basic Flow

RTL & SC
Uncertainties Constraints header .libs

Logic Synthesis (DC/Yosys)

RTL & Prefloorplan SC

header .svf files netlist (.v) .libs

Formal Verification (Formality)

41
Basic Steps of Logic Synthesis

y=(a+b)&(c⊕d)&e
RTL

Logic Synthesis
a
b y Structural netlist
Gate c
d
e
Physical Synthesis

Layout after PnR

Layout

42
Synthesis and Optimization
• Synthesis/ Translation
• The process which converts an abstract
form of desired circuit behavior into a y=(a+b)&(c⊕d)&e
design implementation in terms of logic
gates
a
b y
• Optimization c
d
• Changing design to achieve design goal e
(required by specification)
• For example. Meeting a design rule (ex.
max_transition, max_fanout) a
2
• For example. Optimizing the design to b 3 y
meet a certain design criteri (ex. c
1
minimumu leakage, minimum d
area…etc.) e

43
OpenLane
• https://github.com/The-OpenROAD-Project/OpenLane
• OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-
Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC
implementation steps from RTL all the way down to GDSII.

44
OpenLane Entire Flow Run
• https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/README.md

45
OpenLane Interactive Mode
• https://openlane.readthedocs.io/en/latest/docs/source/advanced_readme.html

46
Synthesis By Yosys Vs DC:
Yosys is free software licensed and it is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 sup.port and provides
a basic set of synthesis algorithms for various application domains.

• DesignCompiler Mega Comands:

• Yosys Mega Commands:
→ read_verilog design.v : import the rtl file and Translates the
→ read_verilog design.v : import the rtl file intermediate design into a technology-independent logic design
using generic technology (GTECH) library elements OR you can use
→ hierarchy –check –top top_design : Elaborate the design hierarchy “analyze & elaborate” instead

→ Opt: Perform design optimization. → target_library: variable specifies the library that Design Compiler
uses to select cells for optimization and mapping. It is typically set
→ techmap: Technology mapping to yosys's internal gatelibrary. only to the standard cell library.

→ dfflibmap: Mapping FFs to FFs in SC library → link_library: variable specifies every library that has cells referenced
by the netlist. The tool uses the libraries specified in the link_library
→ abs –liberty std_cell.lib : used for technology mapping of yosys's variable for resolving references (linking). The link_library variable
internal gatelibrary to a target architecture (SC library) can include memory libraries (RAM, ROM, or any macro)

→ write_verilog synthesized_design.v : Genetare the gate level netlist. → compile_ultra: The compile_ultra command performs a high-effort
compile on the current design for better quality of results (QoR).

→ write –f Verilog –hierarchy synthesized_design.v : Genetare the gate

level netlist

47
Synthesis By Yosys Vs DC:
Yosys is free software licensed and it is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 sup.port and provides
a basic set of synthesis algorithms for various application domains.

• Yosys Mega Commands: • DesignCompiler Mega Comands:

→ read_verilog design.v : import the rtl file → read_verilog design.v : import the rtl file and Translates the
intermediate design into a technology-independent logic design
→ hierarchy –check –top top_design : Elaborate the design hierarchy using generic technology (GTECH) library elements OR you can use
“analyze & elaborate” instead
→ Opt: Perform design optimization.
→ target_library: variable specifies the library that Design Compiler
uses to select cells for optimization and mapping. It is typically set
→ techmap: Technology mapping to yosys's internal gatelibrary.
only to the standard cell library.
→ dfflibmap: Mapping FFs to FFs in SC library
→ link_library: variable specifies every library that has cells referenced
by the netlist. The tool uses the libraries specified in the link_library
→ abs –liberty std_cell.lib : used for technology mapping of yosys's variable for resolving references (linking). The link_library variable
internal gatelibrary to a target architecture (SC library) can include memory libraries (RAM, ROM, or any macro)

→ write_verilog synthesized_design.v : Genetare the gate level netlist. → compile_ultra: The compile_ultra command performs a high-effort
compile on the current design for better quality of results (QoR).

→ write –f Verilog –hierarchy synthesized_design.v : Genetare the gate

level netlist

48
Synthesis Labs:
Trial Clock Clock SYNTH_STARTGY Results
Period Uncertainty
1 15 0.25 Delay 0 WNS Setup 9.84
WNS Hold 3.31
Area 10783
2 2.5 0.26 Delay 0 WNS Setup -0.16
WNS Hold 0.81
Area 10783
3 15 0.25 Area 0 WNS Setup 7.89
WNS Hold 3.31
Area 9808
4 15 -10.25 Delay 0 WNS Setup 20.34
WNS Hold 13.81
Area 10783
5 25 0.25 Delay 0 WNS Setup 17.84
WNS Hold 5.31
Area 10783
49
Contents
• Design Constraints

• Logic Synthesis

• DFT

• LEC
DFT Problem
• Designing with taking into consideration
test problem
• What kind of problems we focus on in DFT?
• DFT Challenges
DFT Problem
• Designing with taking into consideration
test problem
• What kind of problems we focus on in DFT?
• DFT Challenges
DFT Problem
• Designing with taking into consideration
test problem
• What kind of problems we focus on in DFT?
• DFT Challenges
Ex. Physical Defects
Fault Models
• A logical model representing the effects of a physical defect
❖ Stuck-at
❖ At-speed
❖ Quiescent Current
❖ Bridge
Ex. STUCK AT
• A signal, or gate output/input, is stuck at a 0 or 1 value, independent
of the inputs to the circuit
D-Algorithm
• D-Algorithm (Discrepancy Algorithm) is a systematic approach that is suitable for
computer programing
• D-Algebra consists of 5 logic values 1, 0, D, D’, X
• D-Algebra rules:

0∩0=0∩x=x∩0=0
1∩1=1∩x=x∩1=1
x∩x=x
1∩0=D
0 ∩ 1 = D’
D-Algorithm
• Singular Cover (SC) of any logic gate is the compact form of truth-table. This is
done using don’t cares (x).
• AND Gate SC is produced as the following table:
D-Algorithm
• Primitive D-cube of a Fault
(PDCF) is used to specify the
minimum input conditions required at
inputs of a gate to produce an error at
its output.
• PDCF can be derived from the
intersection of singular covers of gates
in faulty and non-faulty conditions
having different outputs.
D-Algorithm
• Primitive D-cube of a Fault Sa0 Fault for AND Gate
(PDCF) is used to specify the
minimum input conditions required at
inputs of a gate to produce an error at
its output.
• PDCF can be derived from the
intersection of singular covers of gates
in faulty and non-faulty conditions
having different outputs.
D-Algorithm
• Primitive D-cube of a Fault Sa0 Fault for AND Gate
(PDCF) is used to specify the
minimum input conditions required at
inputs of a gate to produce an error at
its output.
• PDCF can be derived from the
intersection of singular covers of gates
in faulty and non-faulty conditions
having different outputs.
• PDCF of this faulty AND gate is
{a, b, out} = {1, 1, D}
But How will we achieve this on circuit level?
Multiplexed Flop Scan

• “compile –scan” command in Design Compiler causes the normal flops to be scan-replaced during
the synthesis process
• Adding scan flop in the design and connecting DFT circuit is called Scan Insertion
Scan Ready Design

• Shift in – Capture – Shift out

Automatic Test Pattern Generation “ATPG”
• Automatic generation of test
patterns for scan ready design
• Tools for pattern generation:
Synopsys Tetramax
Siemens (Mentor) Tessent
Cadence Modus DFT
• ATPG tool is used for generating
test pattern file and testbench for
simulating test patterns
• Test patterns are loaded into
automatic test equipment to
classify functioning / faulty ICs.
Automatic Test Pattern Generation “ATPG”
• Automatic generation of test
patterns for scan ready design
• Tools for pattern generation:
Synopsys Tetramax
Siemens (Mentor) Tessent
Cadence Modus DFT
• ATPG tool is used for generating
test pattern file and testbench for
simulating test patterns
• Test patterns are loaded into
automatic test equipment to
classify functioning / faulty ICs.
Contents
• Design Constraints

• Logic Synthesis

• DFT

• LEC
What is Formal Verification?
• Formal verification is an alternative to verification through simulation.
• As designs become larger and more complex and require more simulation vectors,
regression testing with traditional simulation tools becomes a bottleneck in the design
flow.
• A 100% coverage

• Equivalence checkers prove or disprove that one design representation is

logically equivalent to another. In other words, two circuits exhibit the same
exact behavior under all conditions despite different representations-.

68
What is Formality?
• The purpose of Formality is to detect unexpected differences that might have been
introduced into a design during development.
• It uses a formal verification comparison engine to prove or disprove the
equivalence of two given designs and presents any differences for follow-
on detailed analysis.
Design level 1 Design process Design level 2

Formality
Equivalent
Yes/No ?

69
Key Concepts
• Main concepts in Formality are
• Compare Point
• Primary output of a circuit
• Registers within a circuit
• Input to black boxes within a circuit
• Logic Cone
• A block of combinational logic which drives a compare point

70
Equivalence Checking Verification Process

• Equivalence checking is a four-phase process:

• Reading and elaborating language descriptions into logical
representations
• Setting Up Designs to Preempt Differences
• Mapping of corresponding compare points between pairs of designs
(Matching)
• Comparison of logic cones that drive the compare points (Verification)

71
• 0. Guidance (Load Automated Setup File)
•
• Before specifying the reference and implementation designs, an automated setup
file (.svf) can be optionally loaded into Formality. The automated setup file helps
Formality process design changes caused by other tools used in the design flow.
Formality uses this file to assist the compare point matching and verification
process. For each automated setup file that is loaded, Formality processes the
content and stores the information for use during the name-based compare point
matching period.

72
Formality Flow Overview

Start
Setup

Read Reference
Design + Libs Match
Debug
Read Implementation Verify
Design + Libs

No
Success?

Yes

End

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Guidance (Loading of Automated Setup File)
• The purpose of automated file (.svf) is to help Formality process design changes
caused by other tools, which it should have access to as the changes are made.

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 Exercise
-If a netlist ECO was wrongly implemented, removing one of the following cells by mistake..
When will it cause formality to fail?
-An inverter.
-A buffer.
-An unconnected net.

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 Exercise
- What are the possible causes that can cause formal verification to fail? [list at least 2]

-Is providing an .svf file mandatory for successful formal verification? Matching?

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 Static Timing Analysis Gatelevel Timing Simulation
Usage check timing requirements: setup, hold, Functional and timing simulation, checking
recovery, removal, Logical DRCs. functionality by comparing output VS expected output.

More accurate
Much faster than timing-driven simulation. Can catch issues like glitches.
Exhaustive, checks every possible constrained
timing path.
No vector generation is required.
The signal at the input is propagated through
the gates at each level till it reaches the output

Limitations Only useful for synchronous digital circuits, Analysis quality can be dependent on stimulus vectors
can’t analyze asynchronous systems Takes a lot if time and computational power.
Less accurate Non-exhaustive.
Must define timing requirements, false
paths..etc.

Required gatelevel netlist, .lib files, .sdc, derates, .spef gatelevel netlist, library .v, .sdf, test vectors, expected
inputs output.

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 Logical DFT LVS
equivalence
(Formality)
Usage Verify different Observability and Checking spice after
Pros
implementations Controllability to physical synthesis is
match each other validate fabrication has match GDS: devices are
(RTL VS netlist, completed properly matching,
netlist VS netlist) according to "stuck-at"
Model.
Limitations Only checking Extra area and power. Check physical
functionality/logi Coverage usually is not correctness only not
c didn't change 100%. logical or functionality,
after design Testing equipment and nor STA.
stages. testing time.
Required gatelevel netlist, Synthesize design post-PnR .gds, post-PnR
inputs
.lib, Scan .v netlist, SC library
RTL/gatelevel strategy/constraints .spice, macros .spice (if
netlist, .svf you have macros), LVS
.ruleset.
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