UNIT 8

INPUT OUTPUT ORGANIZATION

COA(3140707)
 Outline
• Input Output Interface
• Asynchronous Data Transfer
• Modes of Transfer
• Priority Interrupt
• DMA
• Input Output Processor(IOP)
• CPU-IOP Communication
• Serial Communication
Input Output Interface
• Input Output interface enables transfer of data between internal
storage and external I/O devices.
• In order to interface peripherals with the CPU, special
communication links are required.
• Due to this communication link , the difference between the CPU
and peripherals such as data transfer speed, mode of operation are
overcome.
 Peripherals CPU
■ There are ■ It is an electronic device.
electro-mechanical and
electromagnetic devices. ■ Data Transfer rate is
■ Data Transfer rate is faster.
slower. ■ Data is in word format.
■ Data is in form of codes.

• To Resolve these differences, computer systems include special

hardware components between the CPU and Peripherals to
supervises and synchronizes all input and out transfers.

• These components are called Interface Units because they

interface between the processor bus and the peripheral devices.
 I/O BUS and Interface Module
I/O Bus
Data
Processor Address

Control

(CPU) Interface Interface Interface

Keyboard
and Printer Magnetic
display disk
terminal
Peripheral
device
Connection of I/O bus to input-output devices
 I/O BUS and Interface Module
• It defines the typical link between the processor and several peripherals.
• The I/O Bus consists of data lines, address lines and control lines.
•
The I/O bus from the processor is attached to all peripherals interface.
•
To communicate with a particular device, the processor places a device

address on address lines.

•
Each Interface decodes the address and control received from the I/O bus,

interprets them for peripherals and provides signals for the peripheral

• controller.

It is also synchronizes the data flow and supervises the transfer between
• peripheral and processor.

Each peripheral has its own controller. For example, the printer controller
• The control lines are referred as an I/O command. The
commands are as following:
Control command- A control command is issued to activate the
peripheral and to inform it what to do.
Status command- A status command is used to test various status
conditions in the interface and the peripheral.
Output data command- A data output command causes the
interface to respond by transferring data from the bus into one
of its registers.
Input data command- The data input command is the opposite of
the data output. In this case the interface receives Data from
the peripheral and places it in its buffer register.
 Example of I/O Interface
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

Internal bus
CPU Chip select CS
I/O
Register select Control Control Device
RS1 Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
 I/O Versus Memory Bus
• To communicate with I/O, the processor must communicate with the
memory unit.
• Like the I/O bus, the memory bus contains data, address and read/write
control lines.
• There are 3 ways that computer buses can be used to communicate with
memory and I/O:

i. Use two Separate buses , one for memory and other for I/O.
ii. Use one common bus for both memory and I/O but separate
control lines for each.
iii. Use one common bus for memory and I/O with common control lines.
 GTU Questions

1. Draw and Explain block diagram of I/O interface.

2. Write a note on I/O bus and interface module.
3. What are three types of commands used in I/O bus and I/O devices interfacing?
4. Difference between CPU and Peripheral Device.
5. Prepare all the comparison and difference of this chapter from technical.
 Asynchronous Data Transfer
• “Data transfer between two independent units, where internal timing
in each unit is independent from the other. Such two units are said to
be asynchronous to each other”.

Strobe Control
• The Strobe control method of asynchronous data transfer employs a
single control line to time each transfer.
• The strobe may be activated by either the source or the

destination unit.
Fig: Source-initiated strobe for data transfer Fig: Destination-initiated strobe for
data transfer
 Source-initiated strobe for data transfer
• The strobe may be activated by either the source or the destination unit.
• Figure shows a source-initiated transfer.
• The data bus carries the binary information from source unit to the destination

unit.
•
The strobe is a single line that informs the destination unit when a valid data

word is available in the bus.

•
The source unit first places the data on the data bus.
•
After a delay to ensure that the data settle to a steady value, the source activates
the strobe pulse.
•
The information on the data bus and the strobe signal remain in the active state

• for a sufficient time period to allow the destination unit to receive the data.

The source removes the data from the bus a brief period after it disables its
 Destination-initiated strobe for data transfer
• Figure shows a data transfer initiated by the destination unit. In this case

the destination unit activates the strobe pulse, informing the source to provide the

data.
•
The source unit responds by placing the requested binary information on the data

bus.
•
The data must be valid and remain in the bus long enough for the destination unit to

• accept it.

The falling edge of the strobe pulse can be used again to trigger a destination
• register.
The destination unit then disables the strobe. The source removes the data from the
• bus after a predetermined time interval.

The transfer of data between the CPU and an interface unit is similar to the strobe
 Disadvantage of Strobe Signal
• The disadvantage of the strobe method is that, the source
unit initiates the transfer has no way of knowing whether
the destination unit has actually received the data item that
was places in the bus.
• Similarly, a destination unit that initiates the transfer has no
way of knowing whether the source unit has actually placed
the data on bus.
• The Handshaking method solves this problem.
 Handshaking

• The handshaking method solves the problem of

strobe method by introducing a second control
signal that provides a reply to the unit that
initiates the transfer.
 Principle of Handshaking
• The basic principle of the two-wire handshaking method of data transfer is as
follow:
•
One control line is in the same direction as the data flows in the bus from the
source to destination.
•
It is used by source unit to inform the destination unit whether there a valid data in
the bus.
•
The other control line is in the other direction from the destination to the source.
•
It is used by the destination unit to inform the source whether it can accept the
data.
•
The sequence of control during the transfer depends on the unit that initiates the
transfer.
Source Initiated Transfer using Handshaking
• The sequence of events shows four possible states that the
system can be at any given time.

• The source unit initiates the transfer by placing the data on

the bus and enabling its data valid signal.

• The data accepted signal is activated by the destination unit

after it accepts the data from the bus.

• The source unit then disables its data accepted signal and the
system goes into its initial state.
 Handshaking
Data Bus
Source Unit Data Valid Destination
Unit
Data accepted

(a) Block Diagram

Source unit Destination Unit
Place the data on bus.
Accept data from bus.
Enable data Valid.
Enable data accepted.
Disable data valid.
Disable data accepted.
Invalidate data on bus.
Ready to accept data.

(b) Sequence of events

Destination Initiated Transfer Using Handshaking
• The name of the signal generated by the destination unit has been
changed to ready for data to reflects its new meaning.

• The source unit in this case does not place data on the bus until
after it receives the ready for data signal from the destination unit.

• From there on, the handshaking procedure follows the same pattern
as in the source initiated case.

• The only difference between the Source Initiated and the

Destination Initiated transfer is in their choice of Initial sate.
 Data Bus

Source Data Valid Destination

Unit Unit
Ready for data

(a) Block Diagram

Destination Unit
Source unit
Place the data on bus. Ready to accept data.
Enable ready for data.
Enable data Valid.

Disable data valid. Accept data from bus.

Disable ready for data.
Invalidate data on bus.

(b) Sequence of events

Destination-Initiated transfer using Handshaking
Advantage of the Handshaking method
The Handshaking scheme provides degree of flexibility and
reliability because the successful completion of data transfer relies
on active participation by both units.

If any of one unit is faulty, the data transfer will not be completed.
Such an error can be detected by means of a Timeout mechanism

which provides an alarm if the data transfer is not completed within

time.
 GTU Questions

1. Explain asynchronous transmission with the help of timing

diagram.
2. What is asynchronous data transfer? List its method. Explain
any one with diagram.
3. Briefly explain source initiated transfer using handshaking.
4. Briefly explain destination initiated transfer using strobe control.
5. List disadvantages of strobe signal.
6. List advantages of Handshaking method.
7. Difference between strobe signal and handshaking method.
Modes of Data Transfer
• The data transfer can be handled by various modes.
• some of the modes use CPU as an intermediate path,
others transfer the data directly to and from the memory
unit and this can be handled by 3 following ways:
i. Programmed I/O
ii. Interrupt-Initiated I/O
iii. Direct Memory Access (DMA)
 Programmed I/O

Fig: Data transfer from I/O device to CPU

• In the programmed I/O method, the I/O device does not have direct access to
memory.
• An example of data transfer from an I/O device through an interface into the
CPU is shown in figure.
• When a byte of data is available, the device places it in the I/O bus and
enables its data valid line.
• The interface accepts the byte into its data register and enables the data
accepted line.
• The interface sets a bit in the status register that we will refer to as an F
or "flag" bit.
• The device can now disables the data valid line, but it will not transfer
another byte until the data accepted line is disables by the interface.
•
A program is written for the computer to check the flag in the
status register to determine if a byte has been placed in the data
register by the I/O device.
• This is done by reading the status register into a CPU register and
checking the value of the flag bit.
• line
Once the flag is cleared, the interface disables the data accepted
and the device can then transfer the next data byte.
Figure : Flowchart for CPU program to input data
 Example of Programmed I/O:
• A flowchart of the program that must be written for the CPU is shown in figure
• It is assumed that the device is sending a sequence of bytes that must be stored

in memory.
•
The transfer of each byte requires three instructions :
•
1. Read the status register.
•
2. Check the status of the flag bit and branch to step 1 if not set or to step 3 if
set.
•
3. Read the data register.
•
Each byte is read into a CPU register and then transferred to memory with a

store instruction.
•
A common I/O programming task is to transfer a block of words from an I/O
 Interrupt Initiated I/O
• In programmed initiated, CPU stays in a program loop until the I/O unit indicates that

it is ready for data transfer.

•
This is a time consuming process since it keeps the processor busy needlessly.
•
It can be avoided by using an interrupt facility and a special command to inform the
interface to issue an interrupt request signal when data are available from the device.
•
In the meantime CPU can proceed to execute another program.
•
The interface meanwhile keeps monitoring the device.
•
When the interface determines that the device is ready for data transfer, it generates an

• interrupt request to the computer.

While the CPU is running a program, it does not check the flag. However, when the flag

is set, the computer is momentarily interrupted from proceeding with the current

program and is informed of the fact that the flag has been set.
• The CPU deviates from what it is doing to take care of the input or output transfer.
• After the transfer is completed, the computer returns to the previous program to

continue what it was doing before the interrupt.

•
The CPU responds to the interrupt signal by storing the return address from the program

counter into a memory stack and then control branches to a service routine that processes

the required I/O transfer.

•
The way that the processor chooses the branch address of the service routine varies from

• one unit to another.

• In non-vectored interrupt, branch address is assigned to a fixed location in memory.

In a vectored interrupt, the source that interrupts, supplies the branch information to the
• computer. The information is called vector interrupt.
• In some computers the interrupt vector is the first address of the I/O service routine.
In other computers the interrupt vector is an address that points to a location in memory
where the beginning address of the I/O service routine is stored.
 Priority Interrupt
• When interrupt requests arrive from two or more devices

simultaneously, the processor has to decide which request should be

services first and which one should be delayed.

•
The processor takes the decision with the help of interrupt priorities.
•
It accepts the request having the highest priority.
•
It determines which interrupt is to be served first when two or more

• requests are made simultaneously.

It also determines which interrupts are permitted to interrupt the
computer while another is being serviced
• Higher priority interrupts can make requests while servicing a lower
priority interrupt.
 Daisy Chaining Priority

Figure : Daisy-chain priority interrupt

• The daisy-chaining method of establishing priority consists of a serial

connection of all devices that request an interrupt.
• The device with the highest priority is placed in the first position, followed by
lower- priority devices up to the device with the lowest priority, which is placed
last in the chain.
• This method of connection between three devices and the CPU is shown in
figure.
• If any device has its interrupt signal in the low-level state, the interrupt line
goes to the low-level state and enables the interrupt input in the CPU.
• When no interrupts are pending, the interrupt line stays in the high-level state

and no interrupts are recognized by the CPU.

•
The CPU responds to an interrupt request by enabling the interrupt

acknowledge line.
•
This signal passes on to the next device through the PO (priority out) output

• only if device 1 is not requesting an interrupt.

If device 1 has a pending interrupt, it blocks the acknowledge signal from the
• next device by placing a 0 in the PO output.
It then proceeds to insert its own interrupt vector address (VAD) into the
• A device with a 0 in its Pl input generates a 0 in its PO output to inform the
next-lower- priority device that the acknowledge signal has been blocked.
• A device that is requesting an interrupt and has a 1 in its Pl input will

intercept the acknowledge signal by placing a 0 in its PO output.

•
If the device does not have pending interrupts, it transmits the acknowledge

signal to the next device by placing a 1 in its PO output.

•
Thus the device with Pl = 1 and PO = 0 is the one with the highest priority

that is requesting an interrupt, and this device places its VAD on the data

• bus.
The daisy chain arrangement gives the highest priority to the device that
• receives the interrupt acknowledge signal from the CPU.
The further the device is from the first position; the lower is its priority.
 Direct Memory Access (DMA)
• In the Direct Memory Access (DMA) the interface transfer the data
into and out of the memory unit through the memory bus.

• The transfer of data between a fast storage device such as magnetic

disk and memory is often limited by the speed of the CPU.

• Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of
transfer.

• This transfer technique is called Direct Memory Access (DMA).

 Direct Memory Access (DMA)
• During the DMA transfer, the CPU is idle and has
no control of the memory buses.
• A DMA Controller takes over the buses to manage
the transfer directly between the I/O device and
memory.
 Direct Memory Access (DMA)
• The CPU may be placed in an idle state in a variety of ways.
• One common method extensively used in microprocessor is to disable
the buses through special control signals such as:
– Bus Request (BR)
– Bus Grant (BG)
• These two control signals in the CPU that facilitates the DMA transfer.
• The Bus Request (BR) input is used by the DMA controller to request

the CPU.
•
When this input is active, the CPU terminates the execution of the
current instruction and places the address bus, data bus and read write
• lines into a high Impedance state.
High Impedance state means that the output is disconnected.
 Direct Memory Access (DMA)

ABUS Address Bus

Bus Request
BR

DBUS Data Bus

High Impedance
(disable) when BG

is enable Read
RD
Bus Grant
BG
Write
WR

CPU bus Signals for DMA Transfer

 Direct Memory Access (DMA)
• The CPU activates the Bus Grant (BG) output to inform
the external DMA that the Bus Request (BR) can now take
control of the buses to conduct memory transfer without
processor.

• When the DMA terminates the transfer, it disables the Bus

Request (BR) line.

• The CPU disables the Bus Grant (BG), takes control of the
buses and return to its normal operation.
 Direct Memory Access (DMA)
• The transfer can be made in several ways that are:

i. DMA Burst transfer mode

ii. Cycle Stealing(Single transfer mode)

iii. Block Transfer mode

Cycle Stealing
(Single transfer mode)
Block Transfer mode
Demand or Burst transfer mode
 Direct Memory Access (DMA)
i) DMA Burst :- In DMA Burst transfer, a block sequence
consisting of a number of memory words is transferred in
continuous burst while the DMA controller is master of the
memory buses.
ii) Cycle Stealing :- Cycle stealing allows the DMA controller
to transfer one data word at a time, after which it must
returns control of the buses to the CPU.
 DMA Controller
The DMA controller needs the usual circuits of an interface to
communicate with the CPU and I/O device. The DMA
controller has three registers:

i. Address Register

ii. Word Count Register

iii. Control Register

 DMA Controller
i. Address Register :- Address Register contains an address to
specify the desired location in memory.
ii. Word Count Register :- WC holds the number of words to be
transferred. The register is incre/decre by one after each
word transfer and internally tested for zero.
iii. Control Register :- Control Register specifies the mode of
transfer.
 DMA Controller
• The unit communicates with the CPU via the data bus and control lines.
• The registers in the DMA are selected by the CPU through the address bus
by enabling the DS (DMA select) and RS (Register select) inputs.
•
The RD (read) and WR (write) inputs are bidirectional.
•
When the BG (Bus Grant) input is 0, the CPU can communicate with the
DMA registers through the data bus to read from or write to the DMA
registers.
•
When BG =1, the DMA can communicate directly with the memory by
specifying an address in the address bus and activating the RD or WR
control.
Address Bus

Data bus Address bus buffers

Data bus
buffers
I
N
DS T
DMA Select Address Register
E
R
Register Select RS N
A Word Count Register
Read RD L
B
Write WR U
S Control Register
Bus Request
BR
Bus Grant
BG DMA Request
Interrupt to I/O devices
Interrupt DMA Acknowledgment

Block Diagram of DMA Controller

 DMA Transfer
• The CPU communicates with the DMA through the address and data buses as
with any interface unit.

• The DMA has its own address, which activates the DS and RS lines. The CPU
initializes the DMA through the data bus.
• Once the DMA receives the start control command, it can transfer between the
peripheral and the memory.
• When BG = 0 the RD and WR are input lines allowing the CPU to
communicate with the internal DMA registers.
• When BG=1, the RD and WR are output lines from the DMA controller to
the random access memory to specify the read or write operation of data.
 GTU Questions

1. Write a detail note on DMA.

2. Write a detail note on DMA Controller.
3. What is priority interrupt? Explain Daisy Chaining priority.
4. Write a note on Interrupt Initiated I/O.
5. Explain Programmed I/O with example.
6. List modes of transfer. Explain any one with detail.
7. List three data transfer mode of DMA. Draw flow chart for all
and explain any one.
8. Prepare all the comparison and difference of this chapter from
technical.
Input- Output Processor (IOP)

Figure : Block diagram of a computer with I/O processor

• IOP processor has an ability to execute I/O instructions and it can have
complete control over I/O operation.
• The I/O instructions are stored in main memory.
• When I/O transfer is required, the CPU initiates an I/O transfer by instructing
the I/O channel to execute an I/O program stored in main memory.
• The block diagram of a computer with two processors is shown in figure.
• The CPU and I/O processor work independently and communicate with each

other using centrally located memory and DMA.

•
The CPU is responsible for processing data needed in the solution of

computational tasks.
•
The IOP provides a path for transfer of data between various peripheral
devices and memory unit.
 Feature and Function of IOP
• IOP can fetch and execute its own instructions.

• Instructions are specifically designed to for I/O processing.

• In addition to data transfer, IOP can perform other processing tasks, such as

arithmetic, logic, branching, and code translation.

• IOP can transfer data from an 8-bit source to 16 bit destination and vice versa.

• Communications between IOP and CPU is through memory based control blocks.

CPU defines tasks in the control blocks to locate a program sequence called a channel

program.

• IOP supports multiprocessing environment.

• IOP and CPU can do processing simultaneously.

• This distributed processing approach improves system performance and flexibility.

CPU-IOP Communication
• The communication between CPU and IOP may take different forms, depending on the
particular computer considered.
• In most cases the memory unit acts.
• The sequence of operations may be carried out as shown in the flowchart of figure.
• The CPU sends an instruction to test the IOP path.
• The IOP responds by inserting a status word in memory for the CPU to check.
• The bits of the status word indicate the condition of the IOP and I/O device, such as IOP

overload condition, device busy with another transfer, or device ready for I/O transfer.
•
The CPU refers to the status word in memory to decide what do next.
•
If all is in order, the CPU sends the instruction to start I/O transfer.
•
The memory address received with this instruction tells the IOP where to find

its program.
•
The CPU can now continue with another program while the IOP is busy with the I/O
program.
• Both programs refer to memory by means of DMA transfer.

• When the IOP terminates the execution of its program, it sends an interrupt request to the CPU.

• The CPU responds to the interrupt by issuing an instruction to read the status from the IOP.

• The IOP responds by placing the contents of its status report into a specified memory location.

• The status word indicates whether the transfer has been completed or if any errors occurred during

the transfer.

• From inspection of the bits in the status word, the CPU determines if the I/O operation was

completed satisfactorily without errors.

• The IOP takes care of all data transfers between several I/O units and the memory while the CPU is

processing another program.

• The IOP and CPU are competing for the use of memory, so the number of devices that can be in

operation is limited by the access time of the memory.

 Serial Communication
• Serial data transmission can be classified on the basis of
how transmission occurs.
– Simplex
– Half Duplex
– Full Duplex
• Simplex
• In simplex, the hardware exists such that data transfer takes place only in
one direction.
•
There is no possibility of data transfer in the other direction.
•
Example: transmission from computer to the printer.
• Half Duplex
•
The half duplex transmission allows the data transfer in both directions,
but not simultaneously.
•
Example: walkie-talkie.
•
Full Duplex:
•
The full duplex transmission allows the data transfer in both directions

• simultaneously.
Example: transmission through telephone lines.
 Brief Summary
• Interface is the point where a connection is made between two different parts
of a system.
• The strobe control method of Asynchronous data transfer employs a single
control line to time each transfer.
• The handshaking method solves the problem of strobe method by introducing
a second control signal that provides a reply to the unit that initiates the
transfer.
 Brief Summary
• Programmed I/O mode of data transfer the operations are the results in
I/O instructions which is a part of computer program.
• In the Interrupt Initiated I/O method an interrupt facility an interrupt
command is used to inform the device about the start and end of transfer.
• In the Direct Memory Access (DMA) the interface transfer the data into
and out of the memory unit through the memory bus.
 GTU Questions

1. Write a short note on I/O processor.

2. What is the function of IOP?
3. Explain IOP with block diagram.
4. Explain CPU-IOP communication with diagram.
5. Give the classification of serial communication.
6. Explain serial communication in detail.