SiRFstarV 5e CSRG0530 BGA

Production Information Data Sheet

80-19579-1 Rev. AC
October 29, 2020

Device description Applications

■ GNSS Location Platform Engine ■ Cameras ■ Cellular handset
■ Hybrid positioning system combining GPS, GLONASS, ■ Modules ■ Tablet computers
SBAS and MEMS sensor data ■ Asset tracking ■ Mobile gaming
■ Health and fitness

Features System architecture

■ High performance PVT engine ■ Low-power data logging Agile PMU Auxiliary
Subsystem
■ GPS, GLONASS, QZSS and ■ Designed for 2G, 3G and 4G Battery SMPS RTC Crystal

SBAS (WAAS, EGNOS, MSAS, coexistence Aux Temperature Temperature

GAGAN) reception ■ A-GNSS ready LDO ADC Sensor

■ High GNSS availability and ■ Active CW interference Reference

Power
Power Controls
Controller
accuracy rejection Clock
PLL

■ Concurrent tracking of multiple ■ Direct-to-battery support BBRAM Host Interface

constellations
■ Configurable low-power GNSS Radio
Host Interface
■ MEMS I²C
High-sensitivity tracking to -165 management and GPIO[11:0]

dBm
■ Programmable I/O SPI Flash
■ SiRFInstantFix™ extended GNSS Engine

ephemeris aiding

For additional information or to submit technical questions, go to https://createpoint.qti.qualcomm.com

Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets
NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to [email protected].
Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies International, Ltd. or its affiliated companies
without the express approval of Qualcomm Configuration Management. Distribution to anyone who is not an employee of either Qualcomm Incorporated or its
affiliated companies is subject to applicable confidentiality agreements.
Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express written permission of
Qualcomm Technologies International, Ltd.
Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. Other product and brand names may be trademarks or
registered trademarks of their respective owners.
This technical data may be subject to U.S. and international export, re-export, or transfer ("export") laws. Diversion contrary to U.S. and international law is strictly
prohibited.
Qualcomm Technologies International, Ltd. is a company registered in England and Wales with a registered office at:
Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom.
Registered Number: 3665875 | VAT number: GB787433096
© 2013, 2017, 2020 Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.
CSRG0530 BGA description

CSRG0530 BGA is a 5th generation SiRFstar product. It is a hybrid positioning system that combines GPS,
GLONASS, SBAS and MEMS sensor data to provide a high performance navigation solution.
The integrated DSP provides a flexible processing solution for future functions, extending the platform lifetime and
enabling future regional satellite overlays.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 2
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Ordering information

Package
Device Order Number
Type Size Shipment Method

SiRFStarV 5e BGA 116‑ball 6 x 6.5 x 1 mm, Tape and reel CSRG0530B01-IBBF-R

CSRG0530 BGA (Halogen free) 0.5 mm pitch

NOTE Minimum order quantity is 2kpcs taped and reeled.

Supply chain: The QTIL manufacturing policy is to multisource volume products. For further details,
contact your local sales account manager or representative.

QTIL contacts
General information http://www.qualcomm.com
Sales information [email protected]
Compliance and standards [email protected]

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 3
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Device details

Host interfaces Flexible power managemnet options

■ UART ■ Continuous mode
□ Baud rates to 1.2288 Mbps ■ Push-to-FixII™
□ Flow control support ■ TricklePower™
□ Baud rate accuracy within 2.0 % ■ TricklePowerII™
■ SPI Communications protocol support
□ Supports up to 6.84 MHz maximum clock input ■ OSP
□ Byte synchronization maintained during lowpower ■ NMEA
hibernate states
Configuration methods
□ Supports SPI mode 1 and SPI mode 3
■ OSP/NMEA message-level configuration
□ Supports most and least significant bit order
■ Hardware-level pin configuration
□ Slave mode operation
■ Customer Configuration Kit: QTIL CCK
■ I²C
□ Bit rate of 100 kbps or 400 kbps Clock and frequency aiding interfaces
□ Multi-master operation ■ RTC input 32.768 kHz
□ Configurable address ■ TCXO and crystal interface
□ 1 to 64 B of autonomous data transfer □ External reference clock input support at 16.369 or 26
MHz
■ Host port functional with active RTC
□ Dedicated TCXO voltage control output
External memory □ Power request input for TCXO sharing
■ 4 Mb or 8 Mb SPI flash
Agile power management
Sensor interfaces ■ Direct-to-battery capable
■ Master I²C interface ■ Power control and regulation
□ 2 GPIO pins available to accept interrupts from MEMS ■ Flexible I/O voltage
device(s)
□ MEMS interrupts programmable for positive-edge, External network aiding support
negative-edge, positive-level and negative-level triggers ■ Run as a separate application on a host platform
□ Bit rate of 100 kbps or 400 kbps ■ Provides the capability for a host platform to request and
□ Dual address response (7-bit and 10-bit) receive
□ Master transmit and receive ■ A-GNSS assistance via Qualcomm Synergy® Location
Library Support™
□ 1 to 64 B of autonomous data transfer
■ Server-generated EE data via
■ GPIO interfaces
□ Qualcomm Synergy Location Library Support
□ 9 programmable digital I/O
□ SGEE downloader source code available
□ 2 programmable analogue I/O
Receiver
Electrical requirements
■ Tracks GPS L1 C/A Code, GLONASS FDM signals
■ Supply voltage 1.8 V to 4.5 V
■ Channels: 52
■ Digital I/O voltage level 1.8 V to 3.6 V
■ Maximum update rate: 5 Hz
Environmental limits ■ Maximum altitude/velocity: <60,000 ft / <1,000 knots
■ Operating temperature: -40° C to 85° C
Package
■ Storage temperature: -40° C to 150° C
■ 116‑ball VFBGA 6 x 6.5 x 1 mm 0.5 mm pitch

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 4
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Device details

High performance GNSS reception GNSS performance

■ Single GNSS RF input All statistical performance data is listed at 50 % probability for
■ GNSS signals processed the conditions indicated unless stated otherwise.
Performance data may be improved with system updates. For
□ GPS detailed performance data, see SiRFstarV™ 5e CSRG0530
□ Galileo ready BGA Performance Specification.
□ GLONASS ■ Horizontal positioning accuracy (24 hr static, -130 dBm)
□ BDS ready □ Autonomous <2.5 m
□ A-GNSS ready ■ Velocity accuracy (@ 30 m/s)
■ Mitigation of signal interference □ Speed <0.01 m/s
□ Multipath □ Heading <0.01°
□ CW, narrowband and wideband ■ TTFF (-130 dBm)
□ Cross-correlation interference □ Hot start <1 s
□ Warm start <30 s
□ Cold start <35 s
■ Sensitivity
□ Acquisition (GPS -146 dBm)
□ Tracking (GLONASS -165 dBm, GPS -165 dBm)
□ Navigation (GLONASS -162 dBm, GPS -158 dBm)
Note:
Hot and warm start (commanded), with reference clock
uncertainty within 0.5 ppm, time uncertainty within 2 s and
position uncertainty within 30 km.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 5
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Functional block diagram

VDD
VSS
Agile PMU Auxiliary Subsystem

RTC_IN
SMPS
RTC
RTC_FB
Aux LDO
AIO[0]

ON_OFF
REF_IN
Power Controller WAKEUP
PLL
REF_FB RESET#

BBRAM

UART_TX
GNSS Radio Host Interface and GPIO[11:0] UART_RX
GPIO[11:0]

GNSS Engine

Measurement Subsystem Navigation Subsystem

DSP ARM CPU Host UART

ROM ROM Host SPI

RAM RAM Host I²C

G-TW-0012810.1.1
Functional block diagram

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 6
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Revision history

Revision Date Change reason

1 May 2013 Original publication of this document. Alternate document number

CS-00300734-DS.
2 July 2017 Moisture sensitivity level correct to MSL 3 and Qualcomm
Technologies International, Ltd. (QTIL) branding.
AC October 2020 Updated to QTIL branding.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 7
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Status information

QTIL Product Data Sheets progress according to the following formats: Advance Information, Engineering Sample,
Pre-production Information, and Production Information. The status of this document is Production Information.
Advance Information
Information for designers concerning QTIL product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.

Engineering Sample
Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an
Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum
values specified are only given as guidance to the final specification limits and must not be considered as the final
values.

All detailed specifications including pinouts and electrical specifications may be changed by QTIL without notice.

Pre-production Information
Pinout and mechanical dimension specifications finalized. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.

All electrical specifications may be changed by QTIL without notice.

Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

Production Data Sheets supersede all previous document versions.

Device implementation
As the feature-set of the CSRG0530 BGA is firmware build-specific, see the relevant software release note for the
exact implementation of features on the CSRG0530 BGA.

Life support policy and use in safety-critical applications

QTIL products are not authorized for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. QTIL will not warrant the use of its devices in such applications.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 8
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Contents

CSRG0530 BGA description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
QTIL contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Life support policy and use in safety-critical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Device terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.4 PCB design and assembly considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5 Typical solder reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Measurement subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.1 Constellation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1.2 Interference mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 Navigation subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.1 Navigation features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Auxiliary subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 GNSS radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 System interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Host ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.2 Slave SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.3 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.1 MEMS I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 SPI flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.3 Host port configuration and UART baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.4 Host UART flow control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.5 Host SPI clock and select function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 9
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Contents

3.2.6 Buffered RTC clock function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.7 External Interrupt 1 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.8 External Interrupt 2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.9 Timemark function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.10 Host wake-up/Message waiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.11 Frequency aiding function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.12 External LNA auto detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.13 Programmable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 Reset and power controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.1 ON_OFF input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.2 RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.3 WAKEUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 RF inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Analogue inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.1 RTC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.2 Reference clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Configuration methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 Hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 Message-level configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 Customer configuration kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4 Configuration management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Power control and regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1 Power interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2 Power supply configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3 Main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4 Power management modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4.1 Full Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4.2 Push-to-FixII mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4.3 Micro Power mode with awareness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4.4 TricklePower mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4.5 TricklePowerII mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 Example application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 System software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1.1 Processor quick start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1.2 SPI flash support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1.3 Battery-backed data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.4 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 10
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Contents

7.1.5 ROM code updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.1.6 GNSS navigation features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.7 Power mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.8 Comprehensive command and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.1.9 Production testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2 Application and support software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.1 GNSS_RF_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.2 REF_CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.3 RTC_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.4 Standard I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9 RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 Tape orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.2 Tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.3 Reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Document referneces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 11
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Tables

Table 1-1: Package dimensions................................................................................................................................................ 21

Table 3-1: Host port configuration options.............................................................................................................................. 27
Table 3-2: GPIO pins................................................................................................................................................................. 29
Table 3-3: MEMS I²C interface..................................................................................................................................................30
Table 3-4: SPI flash interface.................................................................................................................................................... 30
Table 3-5: Host port configuration and UART baud rate selection........................................................................................... 31
Table 3-6: Host UART flow control configuration..................................................................................................................... 31
Table 3-7: Host SPI clock and select configuration................................................................................................................... 31
Table 3-8: Buffered RTC clock configuration.............................................................................................................................32
Table 3-9: External Interrupt 1 configuration........................................................................................................................... 32
Table 3-10: External Interrupt 2 configuration......................................................................................................................... 32
Table 3-11: Timemark configuration........................................................................................................................................ 32
Table 3-12: Host wakeup/Message waiting configuration....................................................................................................... 32
Table 3-13: Frequencying aiding e waiting configuration.........................................................................................................33
Table 3-14: External LNA auto detection configuration........................................................................................................... 33
Table 3-15: External and internal LN configuration vs. implementation constraints............................................................... 35
Table 4-1: Hardware configuration inputs................................................................................................................................37
Table 5-1: Power supply configuration modes......................................................................................................................... 39
Table 8-1: Absolute maximum ratings......................................................................................................................................45
Table 8-2: Recommended operating conditions...................................................................................................................... 45
Table 8-3: Power input............................................................................................................................................................. 46
Table 8-4: Power input............................................................................................................................................................. 46
Table 8-5: Phase noise..............................................................................................................................................................46
Table 8-6: Spurious sidebands..................................................................................................................................................46
Table 8-7: Power input............................................................................................................................................................. 46
Table 8-8: Standard I/O............................................................................................................................................................ 47
Table 8-9: Typical values of average current............................................................................................................................ 48
Table 8-10: ESD handling range................................................................................................................................................ 49
Table 10-1: Tape dimensions.................................................................................................................................................... 52

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 12
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Figures

Functional block diagram........................................................................................................................................................... 6

Figure 1-1: Pinout diagram.......................................................................................................................................................14
Figure 1-2: CSRG0530 BGA package dimensions..................................................................................................................... 20
Figure 2-1: System architecture block diagram........................................................................................................................ 23
Figure 8-1: SiRFstarV current consumption measurement test platform................................................................................ 48
Figure 10-1: Tape orientation................................................................................................................................................... 51
Figure 10-2: Tape dimensions.................................................................................................................................................. 51
Figure 10-3: Reel dimensions................................................................................................................................................... 53

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 13
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
1 Package information

1.1 Pinout diagram

Orientation from Top of Device

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11

D1 D2 D3 D5 D6 D7 D9 D10 D11

E1 E2 E3 E4 E8 E9 E10 E11

F1 F2 F3 F4 F8 F9 F10 F11

G1 G2 G3 G4 G8 G9 G10 G11

H1 H2 H3 H4 H8 H9 H10 H11

J1 J2 J3 J5 J6 J7 J9 J10 J11

K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
G-TW-0007454.2.3

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11

Figure 1-1 Pinout diagram

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 14
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

1.2 Device terminal functions

State during
UART Ball Pad type Supply domain Description
reset

Digital: input, Host port connection:

UART_RX A8 open-drain VDD_IO Weak hold RX for UART, MOSI for
bidirectional SPI, SDA for I²C
Digital: output,
Host port connection:
tristate output,
UART_TX B9 VDD_IO Weak hold TX for UART, MISO for
open-drain
SPI, SCL for I²C
bidirectional

RF inputs Ball Pad type Description

GNSS_RF_IN A1 Analogue: input GNSS RF input

State during
GPIO Ball Pad type Supply domain Description
reset

Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[11] C5 bidirectional, VDD_IO Weak hold 11. For details, see
open-drain output, GPIO pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[10] C7 bidirectional, VDD_IO Weak hold 10. For details, see
open-drain output, GPIO pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[9] D5 bidirectional, VDD_IO Weak hold 9. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[8] B8 bidirectional, VDD_IO Weak hold 8. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[7] A10 bidirectional, VDD_IO Weak hold 7. For details, see GPIO
open-drain output, pins
open-drain
bidirectional

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 15
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

State during
GPIO Ball Pad type Supply domain Description
reset

Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[6] A9 bidirectional, VDD_IO Weak hold 6. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[5] C9 bidirectional, VDD_IO Weak hold 5. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[4] C8 bidirectional, VDD_IO Weak hold 4. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[3] E10 bidirectional, VDD_IO Weak hold 3. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[2] B7 bidirectional, VDD_IO Weak hold 2. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[1] D10 bidirectional, VDD_IO Weak hold 1. For details, see GPIO
open-drain output, pins
open-drain
bidirectional
Digital: input,
output, tristate
output, tristate Programmable I/O line
GPIO[0] B10 bidirectional, VDD_IO Weak hold 0. For details, see GPIO
open-drain output, pins
open-drain
bidirectional

AIO Ball Pad type Description

AIO[1] F3 Analogue: input Analogue temperature input 1

AIO[0] E3 Analogue: input Analogue temperature input 0

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 16
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

Clocks Ball Pad Type Description

REF_FB A5 Analogue: input Input from reference crystal

REF_IN A4 Analogue: input Input from reference crystal or reference clock
RTC_FB G2 Analogue: input Input from RTC crystal
RTC_IN G1 Analogue: input Input from RTC crystal or RTC clock

State During
Power Control and Reset Ball Pad Type Supply Domain Description
Reset

Power control
ON_OFF B11 Digital: input VDD_IO High Z
input
Active low device
RESET# C6 Digital: input VDD_IO Weak pull- up
reset
Active low request
to power on the
TCXO_REG_REQ# F9 Digital: input VDD_IO Weak pull- up
VDD_TCXO_REG
regulator
Wakeup output to
WAKEUP D11 Digital: output VDD_IO 0 enable an external
PMIC

Power Ball Pad Type Description

AUX_CAP K1 Power: capacitor Capacitor pad for auxiliary subsystem

1.8 V regulated output to power VDD_RF_1V8 only when
VDD_AUX is powered by a battery
Power: input,
VDD_1V8 G3
output If VDD_AUX is powered by a 1.8 V regulated
NOTE
supply, connect VDD_1V8 to the same supply
Auxiliarysubsystem power. Accepts regulated 1.8 V or battery
VDD_AUX H1 Power: input
voltage between 2.3 V and 4.2 V
A11, 1.2 V supply for digital logic, supplied only from
VDD_DIG_1V2 Power: input
E11 VDD_MAIN_REG_1V2
VDD_IO C11 Power: input 1.8 V to 3.3 V supply for digital I/O
J10,
VDD_MAIN Power: input 1.8 V to 4.2 V supply for main regulator
J11

Power Ball Pad type Description

AUX_CAP K1 Power: capacitor Capacitor pad for auxiliary subsystem

Power: input,
VDD_RF_1V8 G3 1.8 V supply for RF circuits
output
Auxiliary subsystem power. Accepts regulated 1.8 V or
VDD_AUX H1 Power: input
battery voltage between 2.3 V and 4.2 V
A11, 1.2 V supply for digital logic, supplied only from
VDD_DIG_1V2 Power: input
E11 VDD_MAIN_REG_1V2
VDD_IO C11 Power: input 1.8 V to 3.3 V supply for digital I/O
J10,
VDD_MAIN Power: input 1.8 V to 4.2 V supply for main regulator
J11
Regulated 1.2 V output to power only VDD_DIG_1V2 and
VDD_MAIN_REG_1V2 H11 Power: output
VDD_RF_1V2

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 17
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

Power Ball Pad type Description

1.2 V supply for RF circuits, supplied only from

VDD_RF_1V2 B2 Power: input
VDD_MAIN_REG_1V2
B1,
VDD_RF_1V8 Power: input 1.8 V supply for RF circuits, powered only from VDD_1V8
C2,H10
VDD_TCXO_REG J1 Power: output Regulated output to supply external TCXO
D6, D9,
E4,
G10,
VSS_DIG Ground Digital ground
G11,
J2, L4,
M7
H2, F2,
E2, D2,
VSS_RF C3, C4, Ground RF and analogue ground
A3, B3,
B4, A2

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 18
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

No Connect Ball Pad Type Description

NC A6, A7, C1, C10, D1, D3, E1, E8, E9, No connect These pins must be left unconnected
F1, F4, F8, F10, F11, G4, G8, G9, H3,
H4, H8, H9, J3, J5, J6, J7, J9, L2, L3,
L5, L6, L7, L8, L9, L10, L11, M1, M2,
M3, M4, M5, M6, M8, M9, M10, M11,
K2, K3, K4, K5, K6, K7, K8, K9, K10,
K11

TieLow Ball Pad type Description

TL B5, B6, D7, L1 Tie low These pins must be connected to

ground

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 19
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

1.3 Package dimensions

CSRG0530 BGA is available in a 6 x 6.5 x 1 mm, 0.8 mm pitch BGA package.

Top View A
A1 Corner A1
5 A2
1 2 3 4 5 6 7 8 9 10 11 A3
A4

A
B
C
D

E
F
E
G
H
J Z 3
K
L
M

D 0.1 Z 4 0.08 Z
Bottom View
1 2 3 4 5 6 7 8 9 10 11 Seating Plane

F
M
L
K

J
e
H
G
E1 SE Scale = 1mm
F
1
E

D
C
B

A
G

SD Øb
J
A1 Pad Corner H 2
D1

Figure 1-2 CSRG0530 BGA package dimensions

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 20
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

Table 1-1 Package dimensions

Dimension Min Typ Max Dimension Min Typ Max

A - 0.90 1.00 e - 0.5 -

A1 0.14 0.19 0.24 E1 - 5.50 -
A2 0.66 0.71 0.76 F - 0.50 -
A3 - 0.21 - G - 0.50 -
A4 - 0.50 - H 0.50
b 0.25 0.30 0.35 J - 0.50 -
D 5.90 6.00 6.10 N - 116 -
D1 - 5.00 - SD - - 0.00
E 6.40 6.50 6.60 SE - - 0.25
Notes 1. Midpoint of ball array is offset to centre of component.
2. Dimension b is measured at the maximum solder ball diameter parallel to datum plane Z.
3. Datum Z is defined by the spherical crowns of the solder balls..
4. Parallelism measurement shall exclude any effect of mark on top surface of package.
5. Pin A1 polarity mark.
6. All dimensions and tolerance conform to ASME Y14.5M-1994.
7. Terminal positions designation per JESD 95-1, SPP-010.
Ball Land Land diameter 300 µm Ø
Description 116-ball BGA
Size 6 x 6.5 x 1 mm JEDEC MO-225
Pitch 0.5 mm pitch Unit mm

1.4 PCB design and assembly considerations

This section lists recommendations to achieve maximum board-level reliability of the 6 x 6.5 x 1 mm VFBGA 116- ball
package:
■ NSMD lands (that is, lands smaller than the solder mask aperture) are preferred because of the greater accuracy
of the metal definition process compared to the solder mask process. With solder mask defined pads, the
overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress
concentration and act as a point for crack initiation.
■ Ideally, via-in-pad technology should be used to achieve truly NSMD lands. Where this is not possible, a
maximum of one trace connected to each land is preferred and this trace should be as thin as possible, taking
into consideration the current carried and RF requirements.
■ 35 μm thick (1 oz) copper lands are recommended rather than 17 μm thick (0.5 oz). This results in a greater
standoff which has been proven to provide greater reliability during thermal cycling.
■ Land diameter should be 300 μm ±10 μm to achieve optimum reliability.
■ Solder paste is preferred to flux during the assembly process, because this adds to the final volume of solder in
the joint, increasing its reliability.
■ Where a nickel gold plating finish is used, the gold thickness should be kept below 0.5 μm to prevent brittle
gold/tin intermetallics forming in the solder.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 21
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Package information

■ The VFBGA is designed so that ball lands do not lie on top of sensitive areas of the active silicon.
■ VFBGA components often have the ball array mid-point offset to the centre of the component outline. This
requires careful consideration during component PCB footprint design.

1.5 Typical solder reflow profile

For information, see Typical Solder Reflow Profile for Lead-free Devices Information Note.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 22
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
2 System architecture

Figure 2-1 shows CSRG0530 BGA contains several major subsystems.

VDD
VSS
Agile PMU Auxiliary Subsystem

RTC_IN
SMPS
RTC
RTC_FB
Aux LDO
AIO[0]

ON_OFF
REF_IN
Power Controller WAKEUP
PLL
REF_FB RESET#

BBRAM

UART_TX
GNSS Radio Host Interface and GPIO[11:0] UART_RX
GPIO[11:0]

GNSS Engine

Measurement Subsystem Navigation Subsystem

DSP ARM CPU Host UART

ROM ROM Host SPI

RAM RAM Host I²C

G-TW-0012810.1.1
Figure 2-1 System architecture block diagram
CSRG0531 BGA contains several major subsystems:
■ Measurement Subsystem, see Measurement subsystem
■ Navigation Subsystem, see Navigation subsystem
■ Auxiliary Subsystem, see Auxiliary subsystem
■ GNSS Radio, see GNSS radio
■ PMU, see Power control and regulation

2.1 Measurement subsystem

The measurement subsystem performs acquisition and tracking of GNSS signals, including GPS, GLONASS, BDS
and SBAS regional augmentation systems, to produce measurements up to a 5 Hz rate.
Multiple interference mitigation strategies address CW, narrowband and wideband interference, and cross-
correlation and multipath effects.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 23
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System architecture

The measurement subsystem features:

■ GNSS signal processing:
□ GNSS DSP core:
– GPS acquisition and tracking
– GLONASS acquisition and tracking
– BDS acquisition and tracking
– SBAS
□ Scanning, detection and tracking of CW tones in IF bandwidth
□ CW filtering
□ Cross-correlation mitigation
□ Multipath detection and mitigation
□ Wideband interference mitigation
□ Narrowband interference mitigation

2.1.1 Constellation support

The measurement subsystem provides constellation support for several configurations:
■ GPS: uses GPS L1 C/A Code
■ GLONASS: uses GLONASS-M
■ SBAS: uses GPS L1 SBAS signals for corrections and ranging. Regional systems include WAAS, MSAS,
GAGAN and EGNOS
□ QZSS satellites are used for ranging only

2.1.2 Interference mitigation

The measurement subsystem provides various interference mitigation features:
■ CW detection: enables scanning for narrowband interference in GPS and/or GLONASS signal paths
■ GPS narrowband rejection: rejects up to 8 narrowband interferers in the GPS band
■ GPS out-of-band detection and bandpass filtering
■ GLONASS interference cancellation: cancels up to 8 CW interferers in the GLONASS band

2.2 Navigation subsystem

The navigation subsystem provides various hybrid navigation modes:The navigation subsystem processes GNSS
measurements and forms a navigation solution that includes:
■ Position
■ Velocity
■ Time
The navigation subsystem contains all elements to run navigation software on the ARM processor.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 24
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System architecture

The navigation subsystem comprises:

■ ARM CPU
■ Program ROM
■ Data RAM
■ Cache and patch RAM
■ Host interfaces: selection of UART, I²C or Slave SPI
■ MEMS sensor drivers
■ SPI serial flash drivers

2.2.1 Navigation features

The navigation subsystem provides various hybrid navigation modes:
■ Autonomous mode.
■ A-GNSS aiding: MSA and MSB mode support.
■ EE mode: aiding with both CGEE and SGEE for GPS and GLONASS.
■ DGPS aiding: uses differential correction data received from SBAS signals.

2.3 Auxiliary subsystem

The auxiliary subsystem performs system platform management functions. It is normally supplied from continuously
available power and includes:
■ Battery-backed SRAMs for storage of data and patches
■ Power, clock and reset control
■ Power supply management
■ GPIO multiplexor and control:
□ 9 programmable digital I/Os
□ 2 programmable analogue I/Os

■ Temperature sensors for reference clock compensation:

□ 1 internal PTAT sensor
□ Support for 2 external sensors
■ RTC oscillator and health monitor
■ 48-bit RTC timer and alarms
■ Baseband clock generation
■ CPU watchdog monitor
■ VDD_AUX powered configuration, control and status registers

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 25
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System architecture

2.4 GNSS radio

The measurement subsystem interfaces with the GNSS radio subsystem.
The GNSS radio system contains:
■ Single input, dual receive paths for concurrent GPS and GLONASS
■ Harmonic-reject double balanced mixer
■ Fractional-N synthesizer
■ Integrated self-calibating filters
■ Adjustable-gain IF with AGC
■ High-sample rate ADCs with adaptive dynamic range
The GNSS radio subsystem supports:
■ GPS L1 signals
■ GLONASS L1 signals for frequency channels -7 to 6
■ Internal dual gain LNA supports optional external LNA
■ In-band 1 dB compression point of -68 dBm
■ Out-of-band 1 dB compression point of -15 dBm at LNA input
■ Driving with up to 24 dB of external gain (with the internal LNA in low gain)
■ RF input matching to 50 Ω with a single inductor

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 26
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
3 System interfaces

CSRG0530 BGA provides the following system interfaces:

■ Host UART, slave SPI and I²C ports
■ Programmable GPIO pins
■ Reset and power controls
■ RF inputs
■ Analogue inputs for temperature measurement
■ Clock interfaces for RTC and TCXO
For CSRG0530 BGA host port configuration options, see Host ports.
For CSRG0530 BGA PIO configuration options, see GPIO pins.

3.1 Host ports

The host interface is used for GNSS data reports and receiver control.
The CSRG0530 BGA supports 3 alternative host port electrical interfaces:
■ UART: a 2-wire or 4-wire UART port with a maximum data rate of 1.2288 Mbps. Hardware flow control is
available with UART_CTS and UART_RTR signalling.
■ Slave SPI: a 4-wire slave mode SPI port.
■ I²C: a 2-wire I²C operating at 100 kbps or 400 kbps.

Table 3-1 Host port configuration options

Host ports
Pins
UART SPI I²C

UART_TX TX MISO SCL

UART_RX RX MOSI SDA
GPIO[7] RTR CS# -
GPIO[6] CTS CLK -
GPIO[1] Baud Rate - -
GPIO[0] Baud Rate - -

For more information about the GPIO configuration options listed in Table 3-1, see GPIO pins.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 27
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.1.1 UART
The UART host port interface:
■ Serial data rates are selectable from 4800 bps to 1.2288 Mbps.
■ Standard UART speeds are:
□ 4.8 kbps
□ 9.6 kbps
□ 19.2 kbps
□ 38.4 kbps
□ 57.6 kbps
□ 115.2 kbps
□ 230.4 kbps
□ 460.9 kbps
□ 921.6 kbps
□ 1228.8 kbps

■ At boot up, UART speed choices by GPIO[1:0] are:

□ OSP protocol: 115.2 kbps
□ NMEA protocol: 4.8, 9.6 and 38.4 kbps
■ Run-time speed and protocol can be changed using an OSP or NMEA command.
■ All supported UART speeds have a clock error of less than 2 % when RTC frequency error is less than 200 ppm.

3.1.2 Slave SPI

The host interface SPI operates in slave mode:
■ Supports four-wire synchronous SPI bus operating in full-duplex mode. Transmitter and receiver have individual
software-defined 2-byte idle patterns of 0xa7 and 0xb4.
■ Supports a maximum clock of 6.840320 MHz.
■ SPI interface hardware detects synchronization errors and is reset by software.
■ SPI interface hardware is located in the keep-alive domain, therefore byte synchronization is maintained while
the main core is off and the slave SPI module is not clocked.
The 4 SPI signals are:
■ MISO: slave SPI data output
■ MOSI: slave SPI data input
■ SCK: slave SPI clock input
■ SS#: slave SPI chip select active low

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 28
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.1.3 I²C interface

The I²C host port interface supports:
■ Operation at 100 kbps or 400 kbps
■ Default I²C address values are:
□ Receive: 0x60
□ Transmit: 0x62

■ Operating mode is multi-master:

□ Transmit side operates as a master by seizing the I²C bus when detected as idle.
□ Receive side operates as a slave when another master seizes the bus and transmits a receive address.
□ I²C port hardware implements the I²C bus standard contention resolution mechanism.
■ Pins operate as open-drain and require pull-up resistors on the external bus

3.2 GPIO pins

Table 3-2 lists CSRG0530 BGA GPIO pins that provide configurable access to multiple functions, including
programmable control of the GPIO pads.
Table 3-2 GPIO pins

Aiding Memory Other functions

Pins
MEMS I²C SPI Flash RTC Clock EIT Timemark Message Waiting/ Host Wake- up ECLK EXT LNA

GPIO[8] - - RTC EIT2 - - - ✔

GPIO[7] - - - - - - - -
GPIO[6] - - - - - - - -
GPIO[5] - - RTC - TM ✔ - -
GPIO[4] - MOSI - EIT1 - ✔ - -
GPIO[3] - CS# - EIT2 - ✔ ECLK -
GPIO[2] - - - - TM ✔ ECLK -
GPIO[1] SCL CLK - - - - - -
GPIO[0] SDA MISO - EIT1 - - - -

NOTE ■ For GPIO pins associated with host port configuration options, see Host ports.
■ Some functions can only be assigned to a specific GPIO because of the hardware functionality
required. Other functions may be assigned to one of several GPIOs as they are primarily software
driven.
■ Some software versions do not support all function assignments or GPIO flexibility.
■ Some functions may be re-assigned through the CCK or by sending appropriate OSP commands.

System software, features an autodetect function to reduce the dependence on additional configuration settings and
commands.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 29
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

Autodetect features are:

■ Detection and verification of connected SPI flash memory
■ Detection of quick presets for host messaging protocol and UART speeds
■ Detection and loading of ROM Updates from SPI flash into internal RAM patch memory
■ Detection and loading of configuration settings from SPI flash into internal RAM patch memory
■ Detection and loading of aiding data from SPI flash into system memory
■ Detection of the enable control line for an external LNA to set the gain of internal LNA

NOTE The autodetect features function immediately and automatically at every start-up, by driving and
sensing for high and low levels on GPIO[8,4:3,1:0]. External connections on these GPIOs require
caution to prevent transient high current through low resistance to ground or supply voltage, or
inadvertent connections of a GPIO output to an opposing driver output. The configuration input settings
resulting from the autodetection process follow a priority sequence. For more information, see
SiRFstarV 5ea Designer's Guide. During autodetection, if SPI flash contains configuration settings, the
Host interface type, protocol and speed settings configured by GPIOs[7,6,1,0] are not checked.

3.2.1 MEMS I²C interface

A MEMS master I²C function (separate from the host I²C function) for interfacing with I²C MEMS sensors is
configured through GPIO[1] and GPIO[0]. Sensors include:
■ Gyroscope
■ Accelerometer
■ Compass
■ Altimeter
Table 3-3 MEMS I²C interface

GPIO Assignment Pad configuration

GPIO[1] MEMS I²C SCL (output) Open-drain bidirectioonal

GPIP[0] MEMS I²C SDA (bidirectional) Open-drain bidirectioonal

NOTE Pads are configured open-drain. I²C operation requires strong pull-up external resistors on the two I²C
bus lines.

3.2.2 SPI flash interface

GPIO[4:3,1:0] are configured as SPI flash control by system firmware. SPI flash is used for storage of ROM updates,
configurations and refreshable system-aiding data.
Table 3-4 SPI flash interface

GPIO Assignment Pad configuration

GPIO[4] SPI flash controller MOSI (output) Output

GPIO[3] SPI flash controller CS# (output) Output

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 30
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

Table 3-4 SPI flash interface (cont.)

GPIO Assignment Pad configuration

GPIO[1] SPI flash controller CLK (output) Output

GPIO[0] SPI flash controller MISO (output) Input with weak hold

NOTE Auto-detection of SPI flash is included in system ROM software to minimize the requirement for
hardware-based configuration settings. This implementation is intended only for the support of QTIL-
designated SPI flash devices and does not support other SPI-flash devices or general purpose SPI
usage. At CSRG0530 BGA CPU start up in ROM mode, GPIO[4:3,1:0] are driven high and low for auto-
detection of SPI flash.

3.2.3 Host port configuration and UART baud rate selection

If the system has no SPI flash or CCK patch, use GPIO[1] and GPIO[0] to set protocol modes.
If UART host port is selected, GPIO(1) and GPIO(0) also select baud rate.
Table 3-5 lists host port configuration and UART baud rate selection options.
Table 3-5 Host port configuration and UART baud rate selection

GPIO[1] GPIO[0] Protocol UART baud rate

Pull-high Pull-high NMEA 4800

Pull-low Pull-high NMEA 9600
Pull-high Pull-low NMEA 38400
Pull-low Pull-low OSP 115200

3.2.4 Host UART flow control function

If flow control is enabled for the host UART interface, flow control signals are activated with GPIO[7] and GPIO[6].
Table 3-6 Host UART flow control configuration

GPIO Assignment Pad configuration

GPIO[7] Host UART RTR#, active-low output Output

GPIP[6] Host UART CTS#, active-low output Input with weak hold

3.2.5 Host SPI clock and select function

If slave SPI is selected as the host interface, configure GPIO[7] and GPIO[6] to complete SPI interface SCK and SS#
signals. The other two signals of the slave SPI interface map to UART_TX (MISO) and UART_RX (MOSI).
Table 3-7 Host SPI clock and select configuration

GPIP Assignment Configuration

GPIO[7] Host SPI CS#, active-low input Input with weak pull-up
GPIO[6] Host SPI CLK input Input with weak pull-down

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 31
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.2.6 Buffered RTC clock function

In a system with a shared RTC crystal, configure GPIO[8] or GPIO[5] as a buffered 32.768 kHz RTC clock output.
This enables placement of the crystal closer to CSRG0530 BGA's integrated temperature sensor to more accurately
measure the crystal's temperature.
Table 3-8 Buffered RTC clock configuration

GPIO Assignment Pad configuration

GPIO[8] or GPIO[5] RTC clock (output) Output

3.2.7 External Interrupt 1 function

EIT1 accepts an interrupt at high or low logic level and can provide level-sensitive wake-up. The function of EIT1 is
configured through GPIO[4] or GPIO[0].
Table 3-9 External Interrupt 1 configuration

GPIO Assignment Pad configuration

GPIO[4] or GPIO[0] EIT1 interrupt (input) Input with weak pull-up

3.2.8 External Interrupt 2 function

EIT2 accepts an interrupt at high logic level, low logic level, positive edge or negative edge and can provide edge or
level-sensitive wake-up. The function of EIT2 is configured through GPIO[8] or GPIO[3].
Table 3-10 External Interrupt 2 configuration

GPIO Assignment Pad configuration

GPIO[8] or GPIO[3] EIT2 interrupt (input) Input with weak pull-up

3.2.9 Timemark function

TM is an output timing pulse for receiver time, GPS time or UTC time. Pulse duration and period are programmable.
The TM function is configured on GPIO[5] or GPIO[2].
Table 3-11 Timemark configuration

GPIO Assignment Pad configuration

GPIO[5] or GPIO[2] Timemark (output) Output

3.2.10 Host wake-up/Message waiting function

Use a host wake-up/message waiting signal, as part of system level power management, to indicate to a host that
CSRG0530 BGA has data available for transfer over the host port. This signal is used when the host interface is in
slave SPI mode or in UART mode with flow control.
Table 3-12 Host wakeup/Message waiting configuration

GPIO Assignment Pad configuration

GPIO[5:2] Message Waiting/Host Wake-up Output

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 32
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.2.11 Frequency aiding function

ECLK is an input for frequency aiding applications. ECLK input counter function can be configured on GPIO[3] or
GPIO[2].
Table 3-13 Frequencying aiding e waiting configuration

GPIO Assignment Pad configuration

GPIO[3] or GPIO[2] ECLK (input) Input with weak pull-down

3.2.12 External LNA auto detection

OSP commands and CCK allow explicit setting of internal LNA gain.
On start-up, the boot strap on GPIO[8] indicates use of an external LNA.
Logic values are:
■ High: indicates no external LNA. The pin assignment is cleared and available for other uses.
■ Low: indicates an external LNA. GPIO[8] is assigned as GNSS_ON output
Software auto-select configures GPIO[8] as an output and drives the pin high to pre-condition a floating input. The
pin is then configured as an input with a weak pull-up and sampled.

NOTE A valid OSP configuration command, prior configuration stored in BBRAM or CCK loaded from SPI
flash or patch RAM always over-rides start-up strapping logic.

Table 3-14 External LNA auto detection configuration

GPIO Assignment Pad configuration

GPIO[8] External LNA auto-detection/LNA Input/Output

enable

3.2.13 Programmable function

The 9 GPIO pins are configurable as programmable digital I/Os.
In this mode, configurable characteristics are:
■ Direction (input or output)
■ Value, if output (0 or 1)
■ Drive strength, if output (2 mA or 4 mA)
■ Pull (enable or disable)
■ Pull select (up or down)

NOTE Unassigned GPIOs are available as simple digital inputs to support other functions. For example,
reporting the status of a monitoring device for external two or four-state antenna current using OSP
messages.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 33
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.3 Reset and power controls

CSRG0530 BGA has a full set of reset and power control functions, including:
■ ON_OFF input
■ RESET#
■ WAKEUP
■ TCXO_REG_REQ#
ON_OFF input, RESET# and WAKEUP are described in ON_OFF input to WAKEUP. For information on the use of
TCXO_REG_REQ#, see Reference clock interface. In conjunction with configuration settings that are set using OSP
or NMEA commands, these functions control and allow monitoring of the operation of all full- power and low-power
modes.

3.3.1 ON_OFF input

After initial power up and the functioning of an RTC, a signal to the ON_OFF port is the primary means of turning
CSRG0530 BGA on and off.
On CSRG0530 BGA, a low-to-high input rising edge initiates system transitions from the keep-alive/start-up or
HIBERNATE state to the RUN state. A subsequent low-to-high rising edge initiates an orderly shutdown. This input is
sampled at the RTC rate to detect levels and a rising edge. It requires four consecutive RTC ticks, two at low and two
at high levels to detect a rising edge. At the first application of supply voltage to VDD_AUX, a logic high input level
detected at ON_OFF causes CSRG0530 BGA to transition to RUN state.

3.3.2 RESET#
An external reset applied to this pin overrides all other internal controls. RESET# is an active-low signal. Pulling this
pin low for at least 20 µs causes a system reset.
Use external reset:
■ To force CSRG0530 BGA to restart in the event of a malfunction or catastrophic crash.
■ When changing CSRG0530 BGA system program mode configurations between ROM, parallel flash and loading
flash for test purposes.
When RESET# is asserted:
■ All internal logic is reset, except BBRAM, RTC counter and RTC monitor.
■ All internal supplies and clocks and the external TCXO supply output are turned off. The contents of the patch
RAM and program SRAM are lost.
When RESET# is de-asserted:
■ CSRG0530 BGA waits for an ON_OFF.
■ The contents of patch RAM and program SRAM are lost.

3.3.3 WAKEUP
A high on WAKEUP output indicates a high current demand for operation of CSRG0531 BGA. A low indicates
thatCSRG0530 BGA can operate with less than 5 mA.
WAKEUP can control an external main LDO or SMPS device that supplies high current to CSRG0531 BGA and
other systems. After initial application of power, a momentary pulse on WAKEUP indicates that CSRG0531 BGA is
ready to process ON_OFF inputs.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 34
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.4 RF inputs
The GNSS_RF_IN pin accepts input from a SAW filter into an internal LNA. The LNA requires external matching
components to maintain its noise figure
Set the gain of the internal LNA depending on the implementation:
■ High gain:
□ When the RF link has a good GNSS antenna immediately adjacent, with low RF path loss to GNSS_RF_IN.

■ Low gain (add an external active antenna):

□ If product constraints and the environment limit antenna size, require additional external filters and induce
excessive RF path loss from RF cables and connectors between the antenna and GNSS_RF_IN.

NOTE ■ To select high or low gain for the internal LNA use OSP commands or CCK.
■ To auto-detect an external LNA use a GPIO preset or auto-detect function.

Table 3-15 lists external and internal LNA configuration.

Table 3-15 External and internal LN configuration vs. implementation constraints

SAW insertion Recommended Recommended Internal LNA bias

Antenna gain Receiver NF
and path loss external LNA gain external LNA NF current

>0 dBi < 2 dB N/A N/A 2 4.5 mA

<-6 dB > 2 dB 16 to 24 dB <1.5 8 1.5 mA

3.5 Analogue inputs

The analogue inputs AIO[0] and AIO[1] measures the temperature of external frequency sources.

3.6 Clock sources

CSRG0530 BGA requires two clock sources:
■ A real-time clock
■ A temperature-compensated crystal oscillator

3.6.1 RTC interface

The RTC interface provides the RTC clock signal RTC_CLK, to the main baseband circuits and to GNSS DSP timing
functions.
The RTC oscillator has 2 pins:
■ RTC_IN: connects to a 32.768 kHz crystal or a 32.768 kHz CMOS clock source. The pin tolerates up to 3.6 V for
digital input signals and is fail-safe.
■ RTC_FB: is the output of the RTC oscillator circuit. Connect a 32.768 kHz crystal to RTC_IN and RTC_FB to
form a low-power oscillator.

NOTE Leave RTC_FB unconnected when using a CMOS clock source as input.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 35
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet System interfaces

3.6.2 Reference clock interface

The reference clock interface provides support for an external reference TCXO or crystal clock. The default
reference clock frequency is 26.000 MHz, 16.369 MHz is available.
The reference clock interface has 2 pins:
■ REF_IN: connects to a 26 MHz crystal or a 26 MHz CMOS clock source. The pin tolerates up to 3.6 V for digital
input signals and is fail-safe.
■ REF_FB: is the output of the reference clock oscillator cell.

NOTE Leave REF_FB unconnected when using a CMOS clock source as input.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 36
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
4 Configuration methods

Three methods of configuration are available on the CSRG0530 BGA:

■ Message-level
■ Hardware-level
■ CCK

4.1 Hardware configuration

Table 4-1 shows the Hardware configuration requests for host-port selection and bootstrap configuration are made
by connecting pull-up and pull-down resistors to host port inputs GPIO[7] and GPIO[6]. CSRG0530 BGA reads the
state of these inputs during initial power-up to determine and retain the configuration request.
Table 4-1 Hardware configuration inputs

GPIO[7] pull direction GPIO[6] pull direction Host port selection

Do not install an external pull Do not install an external pull SPI

Do not install an external pull Pull-up UART
Pull-down Do not install an external pull I²C

4.2 Message-level configuration

Message level configuration uses either NMEA or OSP commands. Messages from a host containing configuration
requests are decoded and the data retained.
For details on NMEA commands, see NMEA Reference Guide and SiRFstarV Engine NMEA Reference Guide. For
details on OSP commands, see One Socket Protocol Interface Control Document (OSP ICD) and other OSP
documents listed in Document References.

4.3 Customer configuration kit

The CCK is used with external flash memory and enables custom patch code tailored for specific configuration
needs. Contact customer support for details on CCKs.

4.4 Configuration management

An internal configuration management function receives the hardware and software configuration requests and
stores and maintains them in BB SRAM and registers. This data determines CSRG0530 BGA's operating
configuration.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 37
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
5 Power control and regulation

CSRG0530 BGA provides an agile PMU that supports a variety of power configurations, including 1.8 V supply or
direct connection to a battery. The main regulator is configured as an LDO or switched-mode power supply.
.

5.1 Power interface

CSRG0530 BGA has three primary input supply pins:
■ VDD_AUX supplies the auxiliary subsystem and low-power mode functions. It also supplies backup power to the
RTC and battery-backed RAM:
□ The supply is 1.8 V or battery voltages between 2.3 V and 4.5 V.
□ When supplied by battery, an internal regulator is enabled which provides 1.8 V on VDD_1V8.

■ VDD_MAIN supplies power to the main regulator that operates in linear or switched mode:
□ The output of the regulator is VDD_MAIN_REG_1V2, which regulates to 1.2 V and supplies secondary input
supply pins.
□ The supply is 1.8 V, or in switched mode only, a battery voltage between 2.3 V and 4.5 V.
■ VDD_IO supplies digital I/O pads with 1.8 V to 3.3 V.
CSRG0530 BGA has three secondary input supply pins:
■ VDD_DIG_1V2 is a 1.2 V digital supply input provided by the main regulator.
■ VDD_RF_1V2 is a 1.2 V analogue and RF supply input provided by the main regulator.
■ VDD_RF_1V8 is 1.8 V analogue and RF supply input. If VDD_AUX is supplied by:
□ Battery: VDD_RF_1V8 is a secondary supply input supplied by VDD_1V8.
□ 1.8 V: VDD_RF_1V8 is a primary supply input connected to the same 1.8 V source as VDD_AUX.

CSRG0530 BGA provides regulated power on three pins:

■ VDD_MAIN_REG_1V2 provides the main regulator output of 1.2 V for VDD_DIG_1V2 and VDD_RF_1V2.
■ VDD_1V8 provides 1.8 V regulator output for VDD_RF_1V8. The 1.8 V regulator is supplied by VDD_AUX. If
VDD_AUX is 1.8 V the 1.8 V regulator is automatically disabled. In this case, connect VDD_1V8 to the same 1.8
V supply as VDD_AUX.
■ VDD_TCXO_REG provides a programmable voltage source to power a reference TCXO.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 38
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Power control and regulation

5.2 Power supply configuration modes

Table 5-1 shows CSRG0530 BGA power supply configuration modes.
Table 5-1 Power supply configuration modes

Mode Connections

Single-1.8 V One continuous 1.8 V supply to both VDD_AUX and VDD_MAIN. One continuous 1.8 V
to 3.6 V supply to VDD_IO.
Dual-1.8 V Two 1.8 V supplies: One continuous supply to VDD_AUX and one controllable supply to
VDD_MAIN. One continuous 1.8 V to 3.6 V supply to VDD_IO.
Battery plus 1.8 V One continuous battery supply to VDD_AUX. One 1.8 V controllable supply to
VDD_MAIN. One continuous 1.8 V to 3.6 V supply for VDD_IO.
Battery-only One continuous battery supply to both VDD_AUX and VDD_MAIN. One continuous 1.8 V
to 3.6 V supply for VDD_IO.

NOTE In all modes:

■ VDD_AUX is a continuous (always-on) supply.
■ VDD_MAIN can be switched on and off except when a common voltage source supplies both
VDD_AUX and VDD_MAIN.
■ VDD_IO is a continuous (always-on) and independent supply.

See Qualcomm website, for CSRG0530 BGA example schematics.

5.3 Main regulator

The main regulator is the primary power supply. The main regulator operates in LDO mode or switch-mode. Switch-
mode provides higher efficiency and reduced power consumption, especially with higher VDD_MAIN supply
voltages. Switch-mode operation is enabled by connecting an inductor between VDD_MAIN_REG_1V2 and
VDD_DIG_1V2.
The main regulator feature-set includes::
■ Switch-mode: 1.8 V to 4.5 V supply/input voltage
■ Linear mode: 1.8 V input only
■ Fixed 1.2 V output voltage
■ Output current up to 200 mA

5.4 Power management modes

The initial start up mode is Full Power mode, but it has a number of reduced power modes as described in sections
Full Power mode to TricklePowerII mode.
CSRG0530 BGA accepts host OSP configuration commands to transfer between modes.
The lowest non-operating power state is Hibernate. This consumes the least power and maintains the system in
readiness for fast restart.
For more information on power management mode hardware requirements and implementation details, see
SiRFstarV™ Power Managed Modes.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 39
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Power control and regulation

5.4.1 Full Power mode

CSRG0530 BGA operates in continuous Full Power mode to create position fixes at a 1 Hz rate.

5.4.2 Push-to-FixII mode

Push-to-FixII mode has a preset long duty-cycle operation with periodic maintenance mode wake-ups to report a
position fix. It also responds to immediate demands by a host for a position fix. Specific periods, allow
synchronization with data streams from GNSS satellites. This minimises power used searching for data framing
patterns.

5.4.3 Micro Power mode with awareness

In Micro Power mode with awareness, the system is commanded to enter a very low-power mode with dynamically
scheduled periodic wake-ups for calibration updates and in response to a changes in the environment.

5.4.4 TricklePower mode

TricklePower mode is a major duty-cycle mode. When signal conditions are adequate to maintain a position fix, the
entire receiver is controlled by a preset duty cycle to a slower navigation reporting rate. This maintains reasonable
position accuracy and reduces power consumption.

5.4.5 TricklePowerII mode

In TricklePowerII mode, power consumption of the RF section is reduced, but modulated under strong signal
conditions. This maintains high performance while reducing overall power consumption.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 40
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
6 Example application schematic

For the latest example application schematic, contact your local QTIL sales representative or see QTIL Support.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 41
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
7 Software

7.1 System software

CSRG0530 BGA's ROM-based system software is embedded firmware responsible for handling:
■ Search acquisition and tracking of GPS and GLONASS satellites.
■ Position solution computation.
■ Quick start ability to compute fast fix, based on current receiver status.
■ Hardware configuration.
■ Jamming mitigation.
■ Autonomous management of low-power modes (detects no-satellite, ephemeris (in low-power)).
■ Discovery and connecting to external devices (MEMS, SPI flash).
■ Data logging.
■ Host messaging using OSP or NMEA.
■ Host interfacing with host wake-up facility.
■ SPI, UART, I²C support.
■ Multiple SPI flash vendors and sizes supported

7.1.1 Processor quick start

The embedded processor has accelerated startup that uses:
■ Peripheral devices (for example SPI flash) including EE information
■ Data stored in battery-backed SRAM:
□ Current constellation information.
□ Receiver calibration information.
□ Last valid location.
■ Persistent configuration information

7.1.2 SPI flash support

CSRG0530 BGA supports 4 Mb and 8 Mb configurations from several SPI flash vendors:
■ 4 Mb SPI flash parts support 7 days of SGEE capability for GPS and GLONASS satellites.
■ 8 Mb SPI flash part support 31 days of SGEE capability for GPS satellites and 14 days of SGEE capability for
GLONASS satellites.

NOTE CSRG0530 BGA only supports QTIL-specified SPI flash devices for storing data and code updates. A
list of all the SPI flash parts supported can be found on example reference schematics and BOM
documents.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 42
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Software

7.1.3 Battery-backed data

Data is stored in BBRAM to achieve high performance quick position fix data. The system requires internal SRAM,
powered by a continuous non-volatile supply voltage (VDD_AUX) to retain critical data when the main processor
system is unpowered.

7.1.4 Host interface

Software supports:
■ Internal buffering to support high speed.
■ Configurable high rate for fast download of firmware update and EE data.
■ OSP and NMEA protocols.
■ Easy configuration using hardware pull resistors, CCK and host commands.
■ Host wake-up for optimized host power.

7.1.5 ROM code updates

Internal storage is provided for updates to ROM code. Updates are loaded from the host or from attached SPI flash.
Updates are retained in Hibernate state, but lost on reset or removal of the VDD_AUX voltage supply.

7.1.6 GNSS navigation features

■ Concurrently supports positioning using GPS, GLONASS and MEMS.
■ GPS-only mode available for low-power operation.
■ Ranging using GPS, GLONASS, and QZSS for increased accuracy in urban canyons.
■ MEMS aiding for deep urban canyon positioning accuracy.
■ SBAS corrections for improved position accuracy.

7.1.7 Power mode management

Power control does not rely on host intervention. Detecting and adjusting to no-signal conditions is done by:
■ Autonomous operation for all power modes. Auto-handling Ephemeris, EE, information.
■ Wide range of Push-to-Fix periods with autonomous maintenance and on-request reports.
■ TricklePower duty-cycles reduce navigation rate and automatically adapt to signal conditions.
■ TricklePowerII saves power in strong-signal conditions while maintaining position accuracy.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 43
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Software

7.1.8 Comprehensive command and control

QTIL provides comprehensive application notes and reference documents for OSP and NMEA messages, to
integrate host support tools for message processing and aiding functions.
The advantages of OSP messaging are:
■ Greater flexibility.
■ Finer control of the behaviour of the system.
■ Enables optimization of operation to match the user environment.
However, using NMEA sentences makes it easier to adapt industry-standard location applications. For more
information, see QTIL OSP/ICD and QTIL NMEA documents in Document referneces.

7.1.9 Production testing

CSRG0530 BGA is equipped with internal test modefunctions to facilitate rapid production testing.
Test modes support verification of analogue and digital circuitry and components. They also provide information on
performance characteristics that depend on the quality of external components.
For application notes, see QTIL Support.

7.2 Application and support software

Performance evaluation support tools are available from QTIL for prototype development and setting up unique
configurations as required by the end-product designer. The CGT creates a ROM configuration with customer
selections.
Support software in the host system is available for:
■ Loading of software updates into RAM and SPI flash.
■ Downloading of SGEE files into CSRG0530 BGA.
■ Managing storage of EE files on the host.
■ A-GNSS network support.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 44
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
8 Electrical characteristics

8.1 Absolute maximum ratings

Table 8-1 Absolute maximum ratings

Parameter Symbol/Pin Max Unit

Storage temperature - 150.0 °C

Auxiliary supply voltage VDD_AUX 4.50 V
Main switch-mode supply voltage VDD_MAIN 4.50 V
1.8 V supply voltage VDD_1V8 2.20 V
I/O supply voltage VDD_IO 3.60 V
RF 1.8 V supply voltage VDD_RF_1V8 2.20 V
DC RF pin voltage All RF inputs 1.50 V
I/O pin voltage All digital inputs 3.60 V
Analogue input pin voltage AIO input 2.20 V
RF input power All RF inputs 10.0 dBm
Analogue clock inputs All clock inputs 3.6 V

NOTE These are stress ratings only. Stressing the device beyond Absolute Maximum Ratings causes
permanent damage.

8.2 Recommended operating conditions

Voltage supply stability, sequencing and noise requirements are described in the SiRFstarV™ Designer’s Guide.

Table 8-2 Recommended operating conditions

Parameter Symbol Min Typ Max Units

Operating temperature range – -40 - 85 °C

Battery supply voltage VDD_AUX 1.71 - 4.50 V
Main switch-mode supply voltage VDD_MAIN 1.71 1.80 4.50 V
1.8 V supply voltage VDD_1V8 1.71 1.80 1.89 V
1.80 or V
I/O supply voltage VDD_IO 1.71 3.60
3.30
RF 1.8 V supply voltage VDD_RF_1V8 1.71 1.80 1.89 V

NOTE Operation beyond Recommended Operating Conditions is not recommended and extended exposure
beyond them may affect device reliability.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 45
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Electrical characteristics

8.2.1 GNSS_RF_IN
Table 8-3 Power input

Parameter Min Typ Max Units

DC input - No, external DC Bias, must be AC coupled - -

Signal power range -165 - -110 dBm

8.2.2 REF_CLK_IN
Table 8-4 Power input

Parameter Min Typ Max Unit

Peak-to-Peak 0.25 - 3.6 V

Table 8-5 Phase noise

Phase noise (Hz) at 26 MHz SSB magnitude Unit

10 -50 dBc/Hz
100 -75 dBc/Hz
1000 -92 dBc/Hz
10000 -110 dBc/Hz
100000 -120 dBc/Hz
>100000 -120 dBc/Hz

Table 8-6 Spurious sidebands

Spuriouse sidebands (Hz) at 26 MHz SSB magnitude Unit

1 to 10 -38 dBc
10 to 100 -76 dBc
100 to 1000 -76 dBc
1000000 to 5000000 -66 dBc

8.2.3 RTC_IN
Table 8-7 Power input

Parameter Conditions Min Typ Max Unit

Frequency - - 32768 - Hz
Low level input
- -0.4 - 0.3 V
voltage
High level input
- 0.9 - 3.6 V
voltage
Frequency limits - 200 - 50 ppm
AVAR tau = 100 ms - - 1x 10-8 -

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 46
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Electrical characteristics

8.2.4 Standard I/O

Standard I/O includes I/O in the VDD_IO supply domain as described in Device terminal functions.

Table 8-8 Standard I/O

Parameter Conditions Symbol Min Typ Max Unit

Low level output

IOL = 2 mA or 4 mA VOL - - 0.40 V
voltage
High level output
IOH = 2 mA or 4 mA VOH 0.75 × VDD_IO - - V
voltage
Low level input
- VIL -0.30 - 0.40 V
voltage
High level input
- VIH 0.7 × VDD_IO - 3.60 V
voltage
Internal pull-up
resistor - RPU 0.11 1 2.75 MΩ
equivalent a
Internal pull-down
resistor - RPD 0.11 1 2.80 MΩ
equivalent b
Input leakage VI = 1.8 V or 0 V II -10 - 10 µA
Tristate output
Vo = 1.8 V or 0 V IOZ -10 - 10 µA
leakage
Input capacitance - CIN - 5 - µA
a Typical value for internal pull-up in weak mode.
b Typical value for internal pull-down in weak mode.

8.3 Current consumption

Figure 8-1 shows CSRG0530 BGA baseline configuration for current consumption data with:
■ No SPI flash current.
■ Internal LNA at high gain. No external LNA current.
■ TCXO current not included.
■ CMOS input loads on all output signals.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 47
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Electrical characteristics

■ Main regulator in SMPS mode.

■ All currents as average typical values, except maximum current which is maximum expected and includes the
impact of process, temperature and voltage variation.

_ GNSS RF In VDD_AUX
+ A
Simulator
RTC
V Supply

Reference Clock VDD_MAIN

_
+ SiRFstarV

V Supply

Host Interface and GPIOs VDD_IO

+
_
+ V Supply

_
V Supply

_ Flash,
+
MEMS, etc.

G-TW-0012757.2.3
V Supply

Figure 8-1 SiRFstarV current consumption measurement test platform

Table 8-9 Typical values of average current

Main Reg in switcher Main Reg in linear

mode mode
State Conditions VDD_AUX, VDD_AUX, Unit
VDD_MAIN and VDD_MAIN and
VDD_IO at 1.8 V VDD_IO at 1.8 V

The highest
instantaneous total
Maximum current current drawn by in 119 131 mA
CSRG0530 BGAany
operating state
GPS and GLONASS
Acquisition mode with input signal 38.4 46.7 mA
strength of -130 dBm
GPS and GLONASS
Track: full mode with input signal 37.8 45.9 mA
strength of -130 dBm
Track: TricklePower Strong signals
7.2 7.9 mA
(100/1)
Hibernate state - 50 µA

NOTE Internal LNA at Low Gain setting reduces current by 3 mA.

Position data logging increases current by 30 μA.
For more information, see SiRFstarV™ 5e CSRG0530 BGA Performance Specification.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 48
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Electrical characteristics

8.4 ESD protection

Apply ESD static handling precautions during manufacturing.

Table 8-10 shows the ESD handling maximum ratings.

Table 8-10 ESD handling range

Condition Class Max rating

Human Body Model Contact Discharge 2 2000 V (all pins)

per ANSI/ESDA/JEDEC JS‑001
Charged Device Model Contact II 400 V (all pins except GNSS_RF_IN), 200 V
Discharge per JEDEC EIA/ (GNSS_RF_IN only)
JESD22‑C101

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 49
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
9 RoHS compliance

This device meets the substance restriction requirement of the EU RoHS directive.
For further information, refer to the Product Material Declaration (PMD) for this device in CreatePoint.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 50
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
10 Tape and reel information

For tape and reel packing and labelling see IC Packing and Labelling Specification.

10.1 Tape orientation

Figure 10-1 shows the general orientation of the CSRG0530 BGA package in the carrier tape.

Circular Holes
Pin A1 Marker

A≥B

G-TW-0002434.3.2
B

User Direction of Feed

Figure 10-1 Tape orientation

10.2 Tape dimensions

Figure 10-2 shows the dimensions of the tape for the CSRG0530 BGA.

P1
P2 D0
See Note 5
P0 A A B E F W T
See Note 1 See Note 5

B0

A0
B
G-TW-0011515.1.2

K0
SECTION B - B
SECTION A - A

Figure 10-2 Tape dimensions

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 51
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Tape and reel information

Table 10-1 Tape dimensions

A0 B0 K0 E F D0 P0 P1 P2 10P0 T W Unit Notes

1. 10 sprocket hole pitch cumulative tolerance ±0.10

mm.
2. Carrier camber not to exceed 1 mm per 250 mm
3. A0 and B0 measured on a place in the middle of
the corner radii.
4. K0 measured from a place on the inside bottom of
2.32 ± 3.27 ± 0.65 ± 1.75 ± 5.50 ± 1.50 4.00 ± 4.00 ± 2.00 ± 40.0 ± 0.20 ± 12.10 ±
mm the pocket to the top surface of the carrier.
0.06 0.06 0.05 0.10 0.03 (0.05/-0) 0.05 0.05 0.05 0.10 0.03 0.10
5. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole.
6. A0 and B0 measured on a place in the bottom of
the corner radii.
7. Surface resistivity ≥1.0 × 105 Ω/sq and≤1.0 ×
1012Ω/sq.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 52
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Tape and reel information

10.3 Reel information

Reel Dimensions
All dimensions in mm

Full Radius Includes Flange Distortion

Access Hole at Slot Location W3 at Outer Edge
Φ40 min.

W2 Measured at Hub
D*

A N Hub Diameter
Arbor Hole Diameter

C
Tape Slot in Core
For Tape Start

G-TW-0005634.1.1
2.5 min width x 10.0 min depth W1 Measured at Hub

B*
* Drive spokes optional. If used, B and D apply.

Figure 10-3 Reel dimensions

Tape W2 W3
Package type A Max B C D Min N Min W1 Unit
width Max Min Max

6 x 6.5 x 1 mm 12 330 1.5 13.0 20.2 100 12.4 18.4 11.9 15.4 mm
BGA (0.5/-0.2) (2.00/-
0.00)

10.4 Moisture sensitivity level

CSRG0530 BGA is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 53
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Document referneces

Document Reference

ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Human Body ANSI/ESDA/JEDEC JS-001-201
Model (HBM) - Component Level
Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand JESD22-C101E
Thresholds of Microelectronic Components
IC Packing and Labelling Specification 80-CF403-1 / CS-00112584-SP
Moisture / Reflow Sensitivity Classification for Nonhermitic Solid State Surface Mount IPC / JEDEC J-STD-020
Devices
NMEA 0183 Standard For Interfacing Marine Electronic Devices Version 4.00, November 1, 2008
NMEA Reference Guide 80-CT901-1 / CS-00129435-MA
SiRFstar One Socket Protocol Interface Control Document (OSP ICD) 80-CF619-1 / CS-00129291-DC
SiRFstarV™ 5e CSRG0530 BGA Performance Specification CS-00300764-SP
SiRFstarV™ Designer's Guide 80-CG001-1 / CS-00235891-AN
SiRFstarV™ Power Managed Modes 80-CF632-1 / CS-00233787-AN
Typical Solder Reflow Profile for Lead-free Devices Information Note 80-CT462-1 / CS-00116434-AN

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 54
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
Glossary

Term Definition
2G 2nd generation of mobile communications technology
3G 3rd generation of mobile communications technology
ADC Analog-to-digital converter
AGC Automatic gain control
A-GNSS Assisted Global Navigation Satellite System
AIO Analog input/output
ARM Advanced RISC Machines
AVAR Allan VARiance. A measure of frequency stability.
B Byte
BB BaseBand
BBRAM Battery-backed RAM
BDS BeiDou system
BOM Bill of materials
bps Bits per second
C/A Code Coarse/acquisition code
CCK Customer configuration kit
CGEE Client generated extended ephemeris
CGT Configuration generator tool
CLK Clock
CMOS Complementary metal oxide semiconductor
CPU Central processing unit
CS Chip select
CTS Clear to send
CW Carrier wave
CW Continuous wave
dBc Decibels of power relative to carrier power
dBc/Hz dBc within a bandwidth of one Hertz. Used to measure a phase noise profile at
frequencies offset from a carrier frequency
DGPS Differential global positioning system
DSP Digital signal processor
EE Extended ephemeris
EGNOS European Geostationary Navigation Overlay Service. European SBAS system

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 55
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Glossary

Term Definition
EIA Electronic Industries Alliance
EIT External interrupt
ESD Electrostatic discharge
FDM Frequency division multiplexing
GAGAN India's SBAS system
Galileo Europe's GNSS system
GLONASS Global Orbiting Navigational Satellite System
GLONASS-M 2nd generation of GLONASS
GNSS Global navigation satellite system
GPIO General purpose input/output
GPS Global Positioning System, the US GNSS
HBM Human body model
I/O Input/output
ICD Interface control document
IF Intermediate frequency
ITU International telecommunication union
I²C Inter-integrated circuit interface
JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology
Association)
KA Keep-alive block containing non-volatile circuits
L1 ITU designator for microwave frequency band assigned to satellite-based radio-navigation
systems. GPS band-center has satellite signals at nominal 1575.42 MHz
LDO Low-voltage drop out
LNA Low noise amplifier
Mb Megabit
MB Main board
Mbps Megabits per second
MEMS Micro electro mechanical system
MISO Master in slave out
MOSI Master out slave in
MSA Mobile-station assisted
MSAS Multi-functional Satellite Augmentation System (Japan)
MSB Mobile-station Based
MTSAT Multi-functional transport satellite
N/A Not applicable
NC Not connect

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 56
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Glossary

Term Definition
NMEA National marine electronics association
NSMD Nonsolder mask defined
OSP Organic solderability preservative
PCB Printed circuit board
plc Public limited company
PLL Phase locked loop
PMIC Power management integrated circuit
PMU Power management unit
ppm Parts per million
PTAT Proportional to absolute temperature
PVT Position, velocity and time
QTIL Qualcomm Technologies International, Ltd.
QZSS Quasi-Zenith satellite system
RAM Random access memory
RF Radio frequency
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive
(2002/95/ EC)
ROM Read only memory
RTC Real-time clock
RTR Ready to receive
Rx Receive or receiver
SAW Surface acoustic wave
SBAS Satellite based augmentation system
SCL Serial clock line
SDA Serial data (line)
SGEE Server generated extended ephemeris
SMPS Switch-mode power supply
SPI Serial peripheral interface
SRAM Static random access memory
SSB Single side-band
TCXO Temperature compensated crystal oscillator
TL Terminal
TM Transport manager
TTFF Time to first fix
Tx Transmit or transmitter
UART Universal asynchronous receiver transmitter

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 57
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
SiRFstarV 5e CSRG0530 BGA Data Sheet Glossary

Term Definition
UTC Co-ordinated universal time
WAAS Wide area augmentation system
Z Usually in the phrase high Z to mean high impedance

80-19579-1 Rev. AC Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets 58
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION