Department of Electrical Engineering

Faculty Member: Dr Shahzad Younis Dated: 15th February 2024

Semester: 06th Section: C

EE-371: Digital Systems Design

Lab: Introduction to Verilog HDL & Quartus Software

PLO4/ PLO4/ PLO5/ PLO8/ PLO9/

CLO6 CLO7 CLO8
CLO5 CLO5

Name Reg. No Viva / Analysis Modern Ethics Individual

Quiz / Lab of data in Tool and and Team
Performa Lab Usage Safety Work
nce Report

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

Abdul Hannan Adil 407165

Abdullah Mir 407857

Hasnat Ahmed Gill 406264

Muhammad Talha 427108

Rapid Silicon Training Programme – Lab 1: Introduction to Verilog HDL and Quartus Software
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1. OBJECTIVE

The objective of this lab is to familiarize yourself with Verilog Hardware descriptive language
and familiarity with Intel Quartus Software:
� Familiarize yourself with all basic Verilog Concepts
� Create a Quartus Project and Program the FPGA

2. SOFTWARE

Quartus

3. INTRODUCTION

This lab entails the introduction to Quartus software and creating a design in it.

VERILOG:

Verilog is a Hardware Description Language; a textual format for describing electronic

circuits and systems. Applied to electronic design, Verilog is intended to be used for
verification through simulation, for timing analysis, for test analysis (testability analysis and
fault grading) and for logic synthesis.

Quartus:

Quartus is a comprehensive software tool suite used for FPGA (Field Programmable Gate
Array) and CPLD (Complex Programmable Logic Device) design. Developed by Intel
(formerly Altera), Quartus Prime is widely used in the field of digital circuit design and is
known for its advanced features and capabilities. Here are some key aspects of Quartus
Prime:

Key Features of Quartus

Design Entry and Synthesis:

Quartus allows for design entry using schematic diagrams, VHDL, Verilog, and System
Verilog. It includes a sophisticated synthesis engine to convert high-level design descriptions
into lower-level representations (like RTL - Register Transfer Level).

Simulation and Verification:

The software integrates with simulation tools like ModelSim to verify the logic and
functionality of the design before hardware implementation.

Hardware Support:

Quartus supports a wide range of Intel FPGA and CPLD hardware, enabling designers to
create complex digital systems that can be programmed into these devices.
Timing Analysis:

The tool includes powerful timing analysis features, helping designers ensure that their
designs meet the required performance criteria.

Device Programming and Configuration:

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Quartus also supports device programming, enabling users to upload their designs to
physical FPGA or CPLD devices.

IP Core Integration:

It includes a range of Intellectual Property (IP) cores that can be integrated into designs,
speeding up the development process.

FPGA BOARD:

A FPGA is an integrated circuit designed to be configured by a customer or a designer after

manufacturing – hence the term field-programmable. The FPGA configuration is generally
specified using a hardware description language (HDL), similar to that used for
an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to
specify the configuration, but this is increasingly rare due to the advent of electronic design
automation tools.

FPGAs enable manufacturers to implement systems that can be updated when necessary. A
good example of FPGA use is high-speed search: Microsoft is using FPGAs in its data
centres to run Bing search algorithms. The FPGA can change to support new algorithms as
they are created.

4. Gate Level Modelling in Quartus

Lab Task 1
Our very first design in Quartus will be a very to describe a circuit in gate level modelling. In
gate level modelling we specify a circuit using the gate level primitives. In verilog we are
provided with these game level primitives. and, or, not, nand, xnor, xor. When you type these
in the editor these will be highlighted in blue indicating that these are key words. For
example, in order to define an and gate using gate level primitive we will use the following
structure

and u1(output,input1, input 2, …… input n);

In gate level modelling we have
a single output and multiple inputs. For
example in Verilog we will define a 2
bit input and gate as shown in figure
10.

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Figure 10: Simple and gate
Observe the Results by Providing inputs to the switches and observing LEDS.

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Rapid Silicon Training Programme – Lab 1: Introduction to Verilog HDL and Quartus Software
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Lab Task 2
The purpose of this exercise is to learn how to connect simple input and output devices to an
FPGA chip and implement a circuit that uses these devices. We will use the SW9-0 switches

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on the Intel DE1-SoC board as inputs to the circuit. We will use light emitting diodes (LEDs)
and 7-segment displays as output devices.

The DE1-SoC board has 10 toggle switches, called SW17-0, that can be used as inputs to a
circuit, and 10 red lights, called LEDR9-0, that can be used to display output values. Figure
31 shows a simple Verilog module that uses these switches and shows their states on the
LEDs. Since there are 10 switches and lights it is convenient to represent them as vectors in
the Verilog code, as shown. We have used a single assignment statement for all 10 LEDR
outputs, which is equivalent to the individual assignments.

assign LEDR[9] = SW[9];

assign LEDR[8] = SW[8];
...
assign LEDR[0] = SW[0];

Figure 39: Assign Statements

The board has hardwired connections between its FPGA chip and the switches and lights.
To use SW9-0 and LEDR9-0 it is necessary to include in your Quartus project the correct pin
assignments, which are given in the User Manual. For example, the manual specifies that
SW0 is connected to the FPGA pin N25 and LEDR0 is connected to pin AE23. A good way
to make the required pin assignments is to import into the Quartus software the file called
DE2 pin assignments.csv file.

In case you are modifying .csv file, it is important to realise that the pin assignments in the
DE1 pin assignments.csv file are useful only if the pin names given in the file are exactly the
same as the port names used in your Verilog module. The file uses the names SW[0] . . .
SW[17] and LEDR[0] . . . LEDR[17] for the switches and lights, which is the reason we used
these names in figure 32.
Figure 40. Verilog code that uses the DE1 board switches and lights.

Perform the following steps to implement a circuit corresponding to the code in figure 41 on
the DE10 board.

1. Create a new Quartus II project for your circuit. Select Cyclone II EPCQ256 as the target
chip, which is the FPGA chip on the DE1 board.

2. Create a Verilog module for the code in figure 40 and include it in your project.

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3. Include in your project the required pin assignments for the DE1 board, as discussed
above. Compile the project.

4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by
toggling the switches and observing the LEDs.

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NOTE: Due to some issues in Pin Assignments, our LED 1 was not lighting up

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Lab Task 2

Write gate level code for or, not, xor , xnor gates and test their working on FPGA board.

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Lab Task 3

In this exercise you will learn how to construct a 4 bit and gate using 2 bit and gates. In the
working example of and gate you saw that and gate can be constructed by using its gate
primitive. To construct a 4 bit and gate we will use three instances of 2 bit and gates as
shown in the figure 41 below

Figure 41: A 4 bit and gate constructed using two bit and gates only

Recall from your and gate activity we saw in figure 10 that a simple two bit and gate has the
following port list

andgate( output f, input a, input b)

using this structure the gates will have this form

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 Figure 42: Using gates from figure 10

We will make use of this. This method is called module instantiation. We will create three
instances and connect them using module instances. We name these instances as
G1,G2,G3.

First we will declare the inputs and outputs of the circuit of our design.

module andgate_4bit(input a,b,c,d, output f);

Concept of Wire

A wire in verilog is a net that connects two components or two modules of a circuit. In figure
42 the output of G1 is acting as one of the inputs of G3. Similarly the output of G1 is acting
as the second input of G3.

In verilog we declare these nets as wires.

wire w1, w2;

In figure 43 wires w1 and w2 are outputs of gate G1 and G2 respectively.

Figure 43: Internal Connections w1 and w2

Now we will connect the output f and inputs a,b,c,d specified in blue colour in figure 44.

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 Figure 44: Inputs and Outputs of 4 bit and gate are in blue

To connect we copy paste the port list and add a dot (.) operator with the original inputs for
example for andgate G1

andgate G1( .f, .a, .b);

We will connect our inputs a and b and first output of G1 which is w1. We do this by making
use of parentheses ()

andgate G1( .f(w1) , .a(a) , .b(b) );

Similarly for and gate G2

andgate G2( .f(w2) , .a(c) , .b (d) );

and finally for and gate G3

andgate G3( .f(f) , .a(w1) , .b (w2) );

The complete verilog code of figure 44 is shown below

module andgate_4bit(input a,b,c,d, output f);

wire w1, w2;

andgate G1( .f(w1) , .a(a) , .b(b) );

andgate G2( .f(w2) , .a(c) , .b (d) );

andgate G3( .f(f) , .a(w1) , .b (w2) );

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endmodule
Complete this task by simulating the 4 bit and gate and test it on the FPGA board

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Lab Task 5

1.Design a half adder circuit on paper using a truth table.

2.Use gate level modelling for the half adder.

3.Write a test bench for half adder circuit

4.Verify the simulation using a test bench.

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Lab Task 6

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1.Create a full adder circuit using half adder designed in task 5. Make a paper design first

2.Use gate level modelling for full adder circuit.

3.Write a test bench for the full adder circuit

4.Verify the simulation of full adder using a test bench.

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Conclusion
In this lab, we explored the fundamentals of Verilog HDL and its implementation using the
Intel Quartus software. Through various tasks, we gained hands-on experience in designing
basic digital circuits using gate-level modeling and implementing them on the DE1 FPGA
board. We successfully created and tested logic gates, a 4-bit AND gate, a half adder, and a
full adder, reinforcing our understanding of hardware description languages and FPGA
programming.

This lab provided valuable insights into modern digital system design, including Verilog
coding, Quartus project setup, simulation, and FPGA hardware testing. By completing these
exercises, we developed essential skills in circuit synthesis, debugging, and hardware
implementation, which are crucial for advanced digital design applications.

5. Learning Outcomes Checklist

After this lab, you will be able to:

� Understand basic Verilog coding
� Make a project in Quartus and programming the FPGA
� Create, simulate, and implement your codes on the DE1 board

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