Computer Organization &

Architecture(EET2211)
Computer Organization & Architecture(EET2211)
 CALCULATE CPI AND MIPS RATE

INSTRUCTION TYPE INSTRUCTION COUNT CYCLES PER

INSTRUCTION

INTEGER ARUTHMETIC 4,00,000 1

DATA TRANSFER 3,50,000 2
FLOATING POINT 2,00,000 3
CONTROL TRANSFER 50000 2

16 LECTURE 4 6/1/2021
 CALCULATE CPI AND MIPS RATE

17 LECTURE 4 6/1/2021
PROBLEMS

2.1 What will be the overall speed up if 90% of the program run 10
times faster ?
Here N =10 f =.9 1-f = 0.1

Speedup = 100/19 = 5.2632

Computer Organization & Architecture

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2.2 What fraction of the computation should be able to use the
floating point processor in order to achieve an overall speedup of
2.25. Assume the enhancement factor as 15?
Here N=15 speedup=2.25

Hence f = 0.59

Computer Organization & Architecture (EET 2211)

2.3 Initially a processor consists of 60% fixed point instructions and
40% floating point instructions . After enhancement 60% fixed
point remains the same and the rest is enhanced by 25%.
Determine the performance of the processor.
Here initially i.e before enhancement
f = .4 1-f = .6
After enhancement
1-f = .6 f= .4/4 = 0.1

Hence Speedup = 0.7/1 = 0.7

Computer Organization & Architecture

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2.4 The speed of floating point unit has been increased by 20% and
fixed point has been increased by 10%. What is the overall speed
up that is achieved if the ratio of number of floating point
instruction by fixed point instruction is 2:3. (Assume that fixed
point instruction takes x time and floating point instruction
takes 2x time.

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 The execution time before enhancement(Ew)
= (3x + 4x)/5
The execution time after enhancement(Ee)
= ((3x/1.1) +( 4x/1.2))/5

Speedup= 7*33/200 = 1.155

Computer Organization & Architecture

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2.5.A doctor in a hospital observes that on average 6 patients per
hour arrive and there are typically 3 patient in the hospital. What
is the average range of time each patient spend in the hospital?

Here λ = 6 and L= 3
According to Little’s Law i.e. L = λ W
Therefore,W= L/ λ = 0.5 hrs = 30mins

Computer Organization & Architecture

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2.6 Two benchmark programs are executed on three computers with the
following results:

Computer A Computer B Computer C

Program 1 50 20 10
Program 2 100 200 40

The table shows the execution time in seconds, with 10,000,000 instructions
executed in each of the two programs. Calculate the MIPS values for each
computer for each program. Then calculate the arithmetic and harmonic
means assuming equal weights for the two programs, and rank the computers
based on arithmetic mean and harmonic mean.

Computer Organization & Architecture

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MIPS rate:
Computer A Computer B Computer C

Program 1 .2 .5 1

Program 2 .1 .05 .25

Mean calculation

Computer A Computer B Computer C

AM rate .15 .275 .625

HM rate .133 .09 0.4

Computer Organization & Architecture

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Rank

Computer A Computer B Computer C

AM rate 3rd 2nd 1st

HM rate 2nd 3rd 1st

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2.7 Two benchmark programs are executed on three computers
with the following result:
a. Compute the arithmetic mean value for each system using
X as the reference machine and then using Y as the reference
machine. Argue that intuitively the three machines have roughly
equivalent performance and that the arithmetic mean gives
misleading results.

b. Compute the geometric mean value for each system

using X as the reference machine and then using Y as the
reference machine. Argue that the results are more realistic than
with the arithmetic mean.

Computer Organization & Architecture (EET 2211)

 Benchmar Processor
k X Y Z
1 20 10 40
2 40 80 20

Normalized w.r.t X

Benchmar Processor
k
X Y Z
1 1 .5 2
2 1 2 .5
AM 1 1.25 1.25
GM 1 1 1
Computer Organization & Architecture
(EET 2211)
Normalized w.r.t Y

Benchmark Processor

X Y Z
1 2 1 4
2 .5 1 .25
AM 1.25 1 2.125
GM 1 1 1

Computer Organization & Architecture

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2.8 Assume that a benchmark program executes in x seconds
on a reference machine M1. The same program executes on
systems M2, M3, and M4 in 0.75x, 1.5x, and 0.4x seconds,
respectively.
a. Show the speedup of each of the three systems
under test relative to M2.
b. Now show the relative speedup of the three systems.
Comment on the three ways of comparing machines
(execution time, speedup, relative speedup).

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Benchmark M1 M2 M3 M4
Speedup 0.75 1 0.57 1.875
Relative Speed -.25 0 -0.5 .875

Hence
Speed up M4 > M2 > M1 > M3
Relative Speed M4 > M2 > M1 > M3

Computer Organization & Architecture

(EET 2211)
Q1. Consider a hypothetical 32-bit microprocessor having 32-bit instructions
composed of two fields: the first byte contains the opcode and the
remainder the immediate operand or an operand address.

a. What is the maximum directly addressable memory capacity (in bytes)?

b. Discuss the impact on the system speed if the microprocessor bus has:
1. 32-bit local address bus and a 16-bit local data bus, or
2. 16-bit local address bus and a 16-bit local data bus.

c. How many bits are needed for the program counter and the instruction
register?
6/1/2021 Computer Organization and Architecture 3
Answer:
(a) The maximum directly addressable memory capacity in bytes is :
2^(32-8) = 2^24 = 16,777,216 bytes = 16 MB ,(8 bits = 1 byte for he
opcode).
(b)1. A 32-bit local address bus and a 16-bit local data bus. Instruction
and data transfers would take three bus cycles each, one for the
address and two for the data.
Since If the address bus is 32 bits, the whole address can be
transferred to memory at once and decoded there; however, since the
data bus is only 16 bits, it will require 2 bus cycles (accesses to
memory) to fetch the 32-bit instruction or operand.
6/1/2021 Computer Organization and Architecture 4
(b) 2. A 16-bit local address bus and a 16-bit local data bus. Instruction
and data transfers would take four bus cycles each, two for the address
and two for the data.
Therefore, that will have the processor to perform two
transmissions in order to send to memory the whole 32-bit address;
this will require more complex memory interface control to latch the
two halves of the address before it performs an access to it.
In addition to this two-step address issue, since the data bus is
also 16 bits, the microprocessor will need 2 bus cycles to fetch the 32-
bit instruction or operand.
(c) For the PC needs 24 bits (24-bit addresses), and for the IR needs 32
bits (32-bit addresses).
6/1/2021 Computer Organization and Architecture 5
• Q2. Consider a 32-bit microprocessor whose bus cycle is the same
duration as that of a 16-bit microprocessor. Assume that, on average,
20% of the operands and instructions are 32 bits long, 40% are 16 bits
long, and 40% are only 8 bits long. Calculate the improvement
achieved when fetching instructions and operands with the 32-bit
microprocessor.

6/1/2021 Computer Organization and Architecture 6

Answer:
• By assuming that we have a mix of 100 instructions and operands. From
the question:
• 20% of the operands and instructions are 32-bits long, so it is 20 32-bit.
• 40% of the operands and instructions are 16-bits long, so it is 40 16-bit.
• 40% of the operands and instructions are only 8-bits= 1 byte long, so it is
40 bytes.
• The number of bus cycles needed for the16-bit microprocessor will equal
to:(20 *2) + 40 + 40 = 120bus cycles.
• The number of bus cycles needed for the 32-bit microprocessor will equal
to: 20 + 40 + 40 = 100bus cycles.

• By calculating the improvement achieved with the 32-bit

microprocessor to the 16-bit microprocessor will equal to 20/120 =
16.6%.
6/1/2021 Computer Organization and Architecture 7
Q3. A set-associative cache consists of 64 lines, or slots, divided into four-
line sets. Main memory contains 4K blocks of 128 words each. Show the
format of main memory addresses.
Answer: Number of sets = 64/4 = 16
The cache is divided into 16( = 2⁴) sets
Therefore, 4 bits are needed to identify the set number.
Main memory consists of 4K = 2¹² blocks.
Therefore, the set + tag lengths must be 12 bits tag length = 12 - 4 = 8
Each block contains 128 words = 2⁷ words, therefore, 7 bits are needed
to specify the word field
So the main memory can be represented as
TAG SET WORD
8 4 7
6/1/2021 Computer Organization and Architecture 8
Q4: Consider two microprocessors having 8- and 16-bit-wide external
data buses, respectively. The two processors are identical otherwise and
their bus cycles take just as long.

a. Suppose all instructions and operands are two bytes long. By what
factor do the maximum data transfer rates differ?

b. Repeat assuming that half of the operands and instructions are one
byte long.

6/1/2021 Computer Organization and Architecture 9

Answer:
(a) Through a single bus cycle, the 8-bit microprocessor transfers
one byte while the 16-bit microprocessor transfers two bytes. The 16-
bit microprocessor has twice the data transfer rate.

(b) By assuming that we have to perform 50 transfers of operands and

instructions which 25 are one byte long and 25 are two bytes long. The
8-bit microprocessor needs 25+ (2 x25) = 75 bus cycles for the
transfer. The 16-bit microprocessor needs 25 + 25= 50 bus cycles.
Therefore, the data transfer rates differ by a factor of 1.5.

6/1/2021 Computer Organization and Architecture 10

Q5. Consider a hypothetical microprocessor generating a 16-bit address (for
example, assume that the program counter and the address registers are 16
bits wide) and having a 16-bit data bus.

• a. What is the maximum memory address space that the processor can
access directly if it is connected to a “16-bit memory”?

• b. What is the maximum memory address space that the processor can
access directly if it is connected to an “8-bit memory”?

• c. What architectural features will allow this microprocessor to access a

separate “I/O space”?

• d. If an input and an output instruction can specify an 8-bit I/O port

number, how many 8-bit I/O ports can the microprocessor support? How
many 16-bit I/O ports? Explain.
6/1/2021 Computer Organization and Architecture 11
• Q6. Consider a 32-bit microprocessor, with a 16-bit external data bus,
driven by an 8-MHz input clock. Assume that this microprocessor has
a bus cycle whose minimum duration equals four input clock cycles.

• What is the maximum data transfer rate across the bus that this
microprocessor can sustain, in bytes/sec?

• To increase its performance, would it be better to make its external

data bus 32 bits or to double the external clock frequency supplied to
the microprocessor? State any other assumptions you make, and
explain. Hint: Determine the number of bytes that can be transferred
per bus cycle.
6/1/2021 Computer Organization and Architecture 12
Q7. A microprocessor has an increment memory direct instruction,
which adds 1 to the value in a memory location. The instruction has
five stages: fetch opcode (four bus clock cycles), fetch operand address
(three cycles), fetch operand (three cycles), add 1 to operand (three
cycles), and store operand (three cycles).

a. By what amount (in percent) will the duration of the instruction

increase if we have to insert two bus wait states in each memory
read and memory write operation?

b. Repeat assuming that the increment operation takes 13 cycles

instead of 3 cycles.

6/1/2021 Computer Organization and Architecture 13