EE2102 Analog Electronics

Tutorial 8
Assoc Prof See Kye Yak
Office: S2-B2C-112
email: [email protected]
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1 1
Q1: The DC operating point of the common-drain amplifier in Figure 1 has been calculated in
Question 2 of Tutorial 7 to be and . The n-MOS transistor
has , and . Assume that the capacitors have infinite
value, , , , , and ,
calculate the voltage gain, input resistance and output resistance of the amplifier. What is the
maximum input signal amplitude for small signal operation?

Figure 1
2
Under AC condition, the capacitors are treated as short-circuit and DC power source is
shorted to ground.

3
4
3k 250=228.8

5
 Apply KCL at node “s”:

-------- (1)

: -------- (2)

Substitute (2) into (1):

6
For small signal operation,
.
= V

V
7
Q2: What are the voltage gain, input resistance and output resistance for the amplifier in
Figure 2 if , , , and ?
What is the maximum input signal for the amplifier that satisfies the small-signal limit? Use
and for your calculation.

VDD VSS

RS RD
RI M1

+
+
vi Rin Rout RL vo



Figure 2 8
 VDD VSS Under DC condition, all capacitors are treated as open-circuit.
Apply KVL from VDD to ground:
RS RD
RI
M1

+
+
vi Rin Rout RL vo


Assume the PMOS operates in saturation region:
×
𝑇𝑃

Substitute (2) into (1):

Only

9
Apply KVL from VDD to VSS:

PMOS is indeed working in the saturation region.

Since is not given, let assume

10
AC small signal model:

VDD VSS

RS RD
RI
M1

+
+
vi Rin Rout RL vo



11


12
Since we need to find the complete expression of output resistance, ro must be included.

---- (1)
--- (2)
Substitute (2) into (1):

13
 

14
 For small signal operation:

Therefore, the maximum input signal voltage is 292 mV. 15

Q3: The gate resistor RG in Figure 3 is said
to be “bootstrapped” by the action of the
source follower. +VDD
a. Assume that the MOSFET is operating
with and can be M1
neglected. Draw the small signal model
+
and find the voltage gain, input vi
 Rin RG
resistance and output resistance for the
amplifier if , , +
and . RS RL vo
L= Rout 
b. What would be if were exactly
+1? VSS

Figure 3
Small-signal model (all capacitors are treated as shorts and the inductor is treated as
opened):

+VDD

M1
+
vi RG
 R
in

+
L= RS RL vo
Rout 

VSS

17
 + vgs  S
G
RG +
+
vi  gmvgs RS RL vo

D

Apply KCL at node S:

18
 + vgs  S
G
ii RG ii +
+
vi  gmvgs RS RL vo

D

19
Output resistance: + vgs  S ix
G
RG
+
+
RS
gmvgs
= 2k  vx

D

Apply KCL at node S:

=0.004

20
 + vgs  S
G
ii RG +
+
vi  gmvgs RS RL vo

D

If exactly, then

21