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AprilMay 2023

This document is the examination paper for the B. Tech II Year I Semester in Digital System Design at Jawaharlal Nehru Technological University Hyderabad, scheduled for April/May 2023. It consists of two parts: Part A, which is compulsory and carries 25 marks, and Part B, where students must answer one question from each unit, totaling 50 marks. The questions cover various topics in digital systems, including Boolean algebra, flip-flops, encoders, and circuit design.

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27 views2 pages

AprilMay 2023

This document is the examination paper for the B. Tech II Year I Semester in Digital System Design at Jawaharlal Nehru Technological University Hyderabad, scheduled for April/May 2023. It consists of two parts: Part A, which is compulsory and carries 25 marks, and Part B, where students must answer one question from each unit, totaling 50 marks. The questions cover various topics in digital systems, including Boolean algebra, flip-flops, encoders, and circuit design.

Uploaded by

YakaiahKomire
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Code No: 153AN R18

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD


B. Tech II Year I Semester Examinations, April/May - 2023
DIGITAL SYSTEM DESIGN
JN
(Electronics and Communication Engineering)
Time: 3 Hours Max. Marks: 75

Note: i) Question paper consists of Part A, Part B.


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ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks
and may have a, b as sub questions.
H
PART – A
(25 Marks)
U
1.a) Given that (292)10 = (1204)b, determine the value of b. [2]
b) Write short notes on weighted binary codes. [3]
se
c) What is the difference between Decoder and Demultiplexer? [2]
d) Define a combinational logic circuit and give some examples. [3]
e) What is a Flip-Flop? What is the difference between Flip Flop and Latch [2]
d
f) Give the excitation table and characteristic equations of SR and JK Flip Flops [3]
g) What is Meely and Moore models? [2]
h) What are Finite State Machines and what are their limitations? [3]
pa
i) Draw the circuit diagram of OR gates using discrete components. [2]
j) State advantages and disadvantages of TTL. [3]

PART – B
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(50 Marks)

2.a) Perform the following using BCD arithmetic.


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i) (79)10 + (177)10 ii) (481)10 + (178)10
b) Obtain the Dual and complement to the following Boolean expressions [4+6]
i) 𝐹 = 𝐴𝐵 + 𝐴(𝐵 + 𝐶) + 𝐵̅ (𝐵 + 𝐷) ii) 𝐹 = 𝐴 + 𝐵 + 𝐴̅𝐵̅ 𝐶
20
OR
3.a) Place the following equations into proper canonical form.
i) 𝐹(𝐴, 𝐵, 𝐶) = 𝐴𝐵̅ + 𝐴𝐶̅ + 𝐵𝐶 ii) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = (𝐴 + 𝐵̅ )(𝐴 + 𝐵̅ + 𝐷)
b) State and prove consensus theorem. [6+4]
23
4.a) Simplify F(A,B,C,D) = ∑ (4,5,6,7,12,13,14) +d(1,9,11,15) using K-map
b) With a neat design procedure, explain the implementation of a 4-bit Magnitude
Comparator. [5+5]
OR
5.a) What is Encoder? Design an octal to binary Encoder.
b) Reduce the expression using Quine McCluskey's method F(x1, x2, x3, x4, x5) =
∑m (0, 2, 4, 5, 6, 7, 8, 10, 14, 17, 18, 21, 29, 31) + ∑d (11, 20, 22). [5+5]
6.a) With a neat diagram, explain the operation of bidirectional shift register.
b) Describe the conversion of SR-FlipFlop to JK-FlipFlop. [6+4]
OR
JN
7.a) With a neat diagram, explain the operation of a 10-bit ring counter.
b) Explain the operation of synchronous and asynchronous counter. [5+5]

8.a) Design a sequential circuit for the diagram shown in the below figure.
TU
H
U
se
d
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b) Discuss about the capabilities of Finite State Machines. [6+4]
OR
9.a) Explain in detail about state equivalence and machine minimization.
b) With an example, describe state reduction in an incompletely specified machine. [5+5]
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10.a) Draw the circuit of CMOS NOR gate and explain its operation. List some of the
advantages of CMOS over other logic families.
rs
b) Explain about Fan-In, Fan-Out, Tri-state gate. [5+5]
OR
11.a) Draw and explain the circuit of 2-input NAND and 2-input NOR gates using CMOS.
b) Draw the symbol of CMOS transmission gate and write its advantages and applications.
20
[5+5]
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---ooOoo---

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